Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	170424	1			T1	7		T2	4		T3	3
all_pins[1]	170424	1			T1	7		T2	4		T3	3
all_pins[2]	170424	1			T1	7		T2	4		T3	3
all_pins[3]	170424	1			T1	7		T2	4		T3	3
all_pins[4]	170424	1			T1	7		T2	4		T3	3
all_pins[5]	170424	1			T1	7		T2	4		T3	3
all_pins[6]	170424	1			T1	7		T2	4		T3	3
all_pins[7]	170424	1			T1	7		T2	4		T3	3
all_pins[8]	170424	1			T1	7		T2	4		T3	3
all_pins[9]	170424	1			T1	7		T2	4		T3	3
all_pins[10]	170424	1			T1	7		T2	4		T3	3
all_pins[11]	170424	1			T1	7		T2	4		T3	3
all_pins[12]	170424	1			T1	7		T2	4		T3	3
all_pins[13]	170424	1			T1	7		T2	4		T3	3
all_pins[14]	170424	1			T1	7		T2	4		T3	3
all_pins[15]	170424	1			T1	7		T2	4		T3	3
all_pins[16]	170424	1			T1	7		T2	4		T3	3
all_pins[17]	170424	1			T1	7		T2	4		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5451339	1			T1	222		T2	128		T3	95
values[0x1]	2229	1			T1	2		T3	1		T27	1
transitions[0x0=>0x1]	1996	1			T1	2		T3	1		T27	1
transitions[0x1=>0x0]	1996	1			T1	2		T3	1		T27	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	170309	1			T1	7		T2	4		T3	3
all_pins[0]	values[0x1]	115	1			T33	1		T539	1		T540	1
all_pins[0]	transitions[0x0=>0x1]	100	1			T33	1		T539	1		T540	1
all_pins[0]	transitions[0x1=>0x0]	861	1			T30	12		T34	1		T36	12
all_pins[1]	values[0x0]	169548	1			T1	7		T2	4		T3	3
all_pins[1]	values[0x1]	876	1			T30	12		T34	1		T36	12
all_pins[1]	transitions[0x0=>0x1]	861	1			T30	12		T34	1		T36	12
all_pins[1]	transitions[0x1=>0x0]	101	1			T41	1		T56	1		T71	1
all_pins[2]	values[0x0]	170308	1			T1	7		T2	4		T3	3
all_pins[2]	values[0x1]	116	1			T41	1		T56	1		T71	1
all_pins[2]	transitions[0x0=>0x1]	101	1			T41	1		T56	1		T71	1
all_pins[2]	transitions[0x1=>0x0]	42	1			T21	1		T215	2		T281	1
all_pins[3]	values[0x0]	170367	1			T1	7		T2	4		T3	3
all_pins[3]	values[0x1]	57	1			T21	1		T215	4		T212	1
all_pins[3]	transitions[0x0=>0x1]	48	1			T21	1		T215	4		T212	1
all_pins[3]	transitions[0x1=>0x0]	62	1			T212	3		T214	2		T281	2
all_pins[4]	values[0x0]	170353	1			T1	7		T2	4		T3	3
all_pins[4]	values[0x1]	71	1			T212	3		T214	2		T281	2
all_pins[4]	transitions[0x0=>0x1]	57	1			T212	2		T281	1		T282	2
all_pins[4]	transitions[0x1=>0x0]	51	1			T212	1		T214	1		T281	2
all_pins[5]	values[0x0]	170359	1			T1	7		T2	4		T3	3
all_pins[5]	values[0x1]	65	1			T212	2		T214	3		T281	3
all_pins[5]	transitions[0x0=>0x1]	51	1			T212	2		T214	2		T281	3
all_pins[5]	transitions[0x1=>0x0]	97	1			T73	1		T74	1		T75	1
all_pins[6]	values[0x0]	170313	1			T1	7		T2	4		T3	3
all_pins[6]	values[0x1]	111	1			T73	1		T74	1		T75	1
all_pins[6]	transitions[0x0=>0x1]	100	1			T73	1		T74	1		T75	1
all_pins[6]	transitions[0x1=>0x0]	40	1			T58	1		T212	2		T214	1
all_pins[7]	values[0x0]	170373	1			T1	7		T2	4		T3	3
all_pins[7]	values[0x1]	51	1			T58	1		T215	2		T212	2
all_pins[7]	transitions[0x0=>0x1]	37	1			T58	1		T215	1		T212	2
all_pins[7]	transitions[0x1=>0x0]	70	1			T20	1		T64	1		T65	1
all_pins[8]	values[0x0]	170340	1			T1	7		T2	4		T3	3
all_pins[8]	values[0x1]	84	1			T20	1		T64	1		T65	1
all_pins[8]	transitions[0x0=>0x1]	71	1			T20	1		T64	1		T65	1
all_pins[8]	transitions[0x1=>0x0]	59	1			T1	2		T69	2		T70	2
all_pins[9]	values[0x0]	170352	1			T1	5		T2	4		T3	3
all_pins[9]	values[0x1]	72	1			T1	2		T69	2		T70	2
all_pins[9]	transitions[0x0=>0x1]	58	1			T1	2		T69	2		T70	2
all_pins[9]	transitions[0x1=>0x0]	45	1			T215	2		T214	2		T283	4
all_pins[10]	values[0x0]	170365	1			T1	7		T2	4		T3	3
all_pins[10]	values[0x1]	59	1			T215	2		T214	3		T283	4
all_pins[10]	transitions[0x0=>0x1]	50	1			T215	2		T214	3		T283	2
all_pins[10]	transitions[0x1=>0x0]	106	1			T17	1		T77	1		T78	1
all_pins[11]	values[0x0]	170309	1			T1	7		T2	4		T3	3
all_pins[11]	values[0x1]	115	1			T17	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	98	1			T17	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	64	1			T79	1		T80	1		T81	1
all_pins[12]	values[0x0]	170343	1			T1	7		T2	4		T3	3
all_pins[12]	values[0x1]	81	1			T79	1		T80	1		T81	1
all_pins[12]	transitions[0x0=>0x1]	52	1			T79	1		T80	1		T81	1
all_pins[12]	transitions[0x1=>0x0]	98	1			T3	1		T85	1		T86	1
all_pins[13]	values[0x0]	170297	1			T1	7		T2	4		T3	2
all_pins[13]	values[0x1]	127	1			T3	1		T85	1		T86	1
all_pins[13]	transitions[0x0=>0x1]	115	1			T3	1		T85	1		T86	1
all_pins[13]	transitions[0x1=>0x0]	34	1			T214	1		T281	1		T282	4
all_pins[14]	values[0x0]	170378	1			T1	7		T2	4		T3	3
all_pins[14]	values[0x1]	46	1			T214	1		T281	1		T282	4
all_pins[14]	transitions[0x0=>0x1]	36	1			T214	1		T281	1		T282	3
all_pins[14]	transitions[0x1=>0x0]	52	1			T212	3		T214	2		T281	1
all_pins[15]	values[0x0]	170362	1			T1	7		T2	4		T3	3
all_pins[15]	values[0x1]	62	1			T212	3		T214	2		T281	1
all_pins[15]	transitions[0x0=>0x1]	53	1			T212	3		T214	2		T281	1
all_pins[15]	transitions[0x1=>0x0]	59	1			T22	4		T76	4		T215	2
all_pins[16]	values[0x0]	170356	1			T1	7		T2	4		T3	3
all_pins[16]	values[0x1]	68	1			T22	4		T76	4		T215	2
all_pins[16]	transitions[0x0=>0x1]	55	1			T22	4		T76	4		T215	2
all_pins[16]	transitions[0x1=>0x0]	40	1			T27	1		T66	1		T67	1
all_pins[17]	values[0x0]	170371	1			T1	7		T2	4		T3	3
all_pins[17]	values[0x1]	53	1			T27	1		T66	1		T67	1
all_pins[17]	transitions[0x0=>0x1]	53	1			T27	1		T66	1		T67	1