Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4775	1			T118	1		T121	101		T119	11
invalid_ep[0xd]	4761	1			T118	1		T121	103		T119	13
invalid_ep[0xe]	4660	1			T118	1		T121	104		T119	13
invalid_ep[0xf]	4737	1			T42	1		T117	4		T118	3
endpoints[0x0]	15678	1			T3	1		T42	3		T30	2
endpoints[0x1]	14342	1			T30	2		T31	5		T36	2
endpoints[0x2]	12239	1			T42	1		T43	8		T30	2
endpoints[0x3]	13788	1			T2	1		T28	1		T30	2
endpoints[0x4]	12838	1			T30	2		T31	5		T34	2
endpoints[0x5]	14550	1			T29	19		T30	2		T31	3
endpoints[0x6]	11143	1			T27	1		T42	1		T30	2
endpoints[0x7]	14907	1			T30	2		T31	2		T36	2
endpoints[0x8]	10827	1			T42	3		T43	6		T30	2
endpoints[0x9]	14580	1			T30	2		T31	3		T32	3
endpoints[0xa]	13407	1			T43	5		T30	2		T36	2
endpoints[0xb]	14145	1			T30	2		T31	6		T36	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24748	1			T2	1		T27	1		T42	1
pkt_types[PidTypeOutToken]	76354	1			T3	1		T42	1		T29	8
pkt_types[PidTypeInToken]	62066	1			T28	1		T42	4		T29	11

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1018	1			T121	28		T400	1		T122	20
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1046	1			T121	25		T122	27		T123	19
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1016	1			T121	20		T400	2		T122	19
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1074	1			T118	2		T121	27		T122	25
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1676	1			T59	1		T60	1		T164	5
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1797	1			T57	1		T227	1		T104	2
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1794	1			T42	1		T43	2		T4	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1665	1			T2	1		T39	7		T66	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1545	1			T87	1		T5	2		T117	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1701	1			T5	3		T121	26		T400	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1744	1			T27	1		T38	8		T4	4
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1738	1			T398	1		T121	30		T168	2
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1674	1			T43	2		T6	3		T63	8
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1739	1			T6	4		T171	23		T117	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1786	1			T43	2		T4	6		T173	7
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1735	1			T20	8		T5	5		T175	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1674	1			T118	1		T121	27		T119	11
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1592	1			T121	28		T119	13		T120	11
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1600	1			T121	23		T119	13		T120	6
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1545	1			T117	1		T121	26		T119	8
pkt_types[PidTypeOutToken]	endpoints[0x0]	8239	1			T3	1		T42	1		T30	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	6494	1			T30	1		T31	2		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	4125	1			T43	3		T30	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5878	1			T30	1		T31	1		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5665	1			T30	1		T31	3		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	6580	1			T29	8		T30	1		T31	2
pkt_types[PidTypeOutToken]	endpoints[0x6]	3753	1			T30	1		T31	1		T33	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	7050	1			T30	1		T31	2		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	3780	1			T43	2		T30	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	6226	1			T30	1		T31	2		T36	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5620	1			T43	1		T30	1		T36	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	6533	1			T30	1		T31	3		T36	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1083	1			T121	29		T122	26		T123	23
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1075	1			T121	26		T122	24		T123	31
pkt_types[PidTypeInToken]	invalid_ep[0xe]	988	1			T121	30		T122	22		T123	26
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1070	1			T42	1		T117	2		T121	27
pkt_types[PidTypeInToken]	endpoints[0x0]	4641	1			T42	1		T30	1		T31	2
pkt_types[PidTypeInToken]	endpoints[0x1]	4863	1			T30	1		T31	3		T36	1
pkt_types[PidTypeInToken]	endpoints[0x2]	5116	1			T43	1		T30	1		T31	4
pkt_types[PidTypeInToken]	endpoints[0x3]	5058	1			T28	1		T30	1		T31	2
pkt_types[PidTypeInToken]	endpoints[0x4]	4467	1			T30	1		T31	2		T34	1
pkt_types[PidTypeInToken]	endpoints[0x5]	5067	1			T29	11		T30	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4439	1			T30	1		T31	1		T36	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4980	1			T30	1		T36	1		T163	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4220	1			T42	2		T30	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0x9]	5481	1			T30	1		T31	1		T32	3
pkt_types[PidTypeInToken]	endpoints[0xa]	4818	1			T43	1		T30	1		T36	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4700	1			T30	1		T31	3		T36	1