Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T215	7		T212	7		T214	7
all_values[1]	278	1			T215	7		T212	7		T214	7
all_values[2]	278	1			T215	7		T212	7		T214	7
all_values[3]	278	1			T215	7		T212	7		T214	7
all_values[4]	278	1			T215	7		T212	7		T214	7
all_values[5]	278	1			T215	7		T212	7		T214	7
all_values[6]	278	1			T215	7		T212	7		T214	7
all_values[7]	278	1			T215	7		T212	7		T214	7
all_values[8]	278	1			T215	7		T212	7		T214	7
all_values[9]	278	1			T215	7		T212	7		T214	7
all_values[10]	278	1			T215	7		T212	7		T214	7
all_values[11]	278	1			T215	7		T212	7		T214	7
all_values[12]	278	1			T215	7		T212	7		T214	7
all_values[13]	278	1			T215	7		T212	7		T214	7
all_values[14]	278	1			T215	7		T212	7		T214	7
all_values[15]	278	1			T215	7		T212	7		T214	7
all_values[16]	278	1			T215	7		T212	7		T214	7
all_values[17]	278	1			T215	7		T212	7		T214	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6574

1

T215

163

T212

181

T214

156

auto[1]

2322

1

T215

61

T212

43

T214

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6070

1

T215

148

T212

143

T214

156

auto[1]

2826

1

T215

76

T212

81

T214

68

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5192

1

T215

129

T212

117

T214

127

auto[1]

3704

1

T215

95

T212

107

T214

97

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	87	1			T215	1		T212	4		T214	3
all_values[0]	auto[0]	auto[1]	auto[0]	64	1			T214	2		T281	2		T282	1
all_values[0]	auto[1]	auto[0]	auto[1]	63	1			T215	5		T212	1		T281	1
all_values[0]	auto[1]	auto[1]	auto[1]	64	1			T215	1		T212	2		T214	2
all_values[1]	auto[0]	auto[0]	auto[0]	85	1			T215	2		T212	3		T214	3
all_values[1]	auto[0]	auto[1]	auto[0]	75	1			T215	2		T212	1		T214	2
all_values[1]	auto[1]	auto[0]	auto[1]	66	1			T215	2		T212	1		T214	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1			T215	1		T212	2		T282	1
all_values[2]	auto[0]	auto[0]	auto[0]	46	1			T215	1		T212	1		T281	1
all_values[2]	auto[0]	auto[0]	auto[1]	46	1			T215	2		T212	1		T281	1
all_values[2]	auto[0]	auto[1]	auto[0]	40	1			T215	1		T212	1		T214	1
all_values[2]	auto[0]	auto[1]	auto[1]	33	1			T215	1		T212	2		T214	2
all_values[2]	auto[1]	auto[0]	auto[1]	68	1			T215	1		T212	1		T214	2
all_values[2]	auto[1]	auto[1]	auto[1]	45	1			T215	1		T212	1		T214	2
all_values[3]	auto[0]	auto[0]	auto[0]	44	1			T215	1		T212	1		T214	2
all_values[3]	auto[0]	auto[0]	auto[1]	41	1			T214	1		T281	2		T282	2
all_values[3]	auto[0]	auto[1]	auto[0]	56	1			T215	1		T212	2		T214	1
all_values[3]	auto[0]	auto[1]	auto[1]	22	1			T215	2		T282	1		T283	1
all_values[3]	auto[1]	auto[0]	auto[1]	66	1			T215	1		T212	2		T214	2
all_values[3]	auto[1]	auto[1]	auto[1]	49	1			T215	2		T212	2		T214	1
all_values[4]	auto[0]	auto[0]	auto[0]	65	1			T214	2		T281	3		T282	3
all_values[4]	auto[0]	auto[0]	auto[1]	27	1			T212	1		T214	1		T284	2
all_values[4]	auto[0]	auto[1]	auto[0]	42	1			T215	5		T279	1		T285	1
all_values[4]	auto[0]	auto[1]	auto[1]	21	1			T212	2		T214	1		T282	1
all_values[4]	auto[1]	auto[0]	auto[1]	64	1			T212	4		T214	2		T282	1
all_values[4]	auto[1]	auto[1]	auto[1]	59	1			T215	2		T214	1		T281	4
all_values[5]	auto[0]	auto[0]	auto[0]	57	1			T215	2		T214	1		T281	1
all_values[5]	auto[0]	auto[0]	auto[1]	37	1			T215	1		T212	3		T282	1
all_values[5]	auto[0]	auto[1]	auto[0]	44	1			T214	2		T281	1		T282	1
all_values[5]	auto[0]	auto[1]	auto[1]	28	1			T212	1		T214	1		T281	1
all_values[5]	auto[1]	auto[0]	auto[1]	59	1			T215	4		T212	2		T214	1
all_values[5]	auto[1]	auto[1]	auto[1]	53	1			T212	1		T214	2		T281	3
all_values[6]	auto[0]	auto[0]	auto[0]	63	1			T215	1		T212	1		T281	2
all_values[6]	auto[0]	auto[0]	auto[1]	31	1			T215	2		T212	3		T283	1
all_values[6]	auto[0]	auto[1]	auto[0]	41	1			T214	2		T281	4		T279	1
all_values[6]	auto[0]	auto[1]	auto[1]	27	1			T215	2		T283	1		T279	2
all_values[6]	auto[1]	auto[0]	auto[1]	66	1			T215	1		T212	2		T214	2
all_values[6]	auto[1]	auto[1]	auto[1]	50	1			T215	1		T212	1		T214	3
all_values[7]	auto[0]	auto[0]	auto[0]	99	1			T215	3		T212	1		T214	2
all_values[7]	auto[0]	auto[1]	auto[0]	76	1			T212	2		T214	3		T281	5
all_values[7]	auto[1]	auto[0]	auto[1]	54	1			T215	2		T212	3		T282	1
all_values[7]	auto[1]	auto[1]	auto[1]	49	1			T215	2		T212	1		T214	2
all_values[8]	auto[0]	auto[0]	auto[0]	82	1			T212	2		T281	3		T283	2
all_values[8]	auto[0]	auto[1]	auto[0]	87	1			T215	4		T212	1		T214	4
all_values[8]	auto[1]	auto[0]	auto[1]	53	1			T215	1		T212	1		T214	1
all_values[8]	auto[1]	auto[1]	auto[1]	56	1			T215	2		T212	3		T214	2
all_values[9]	auto[0]	auto[0]	auto[0]	46	1			T212	2		T283	2		T279	1
all_values[9]	auto[0]	auto[0]	auto[1]	36	1			T215	1		T214	2		T281	1
all_values[9]	auto[0]	auto[1]	auto[0]	44	1			T215	2		T212	1		T214	1
all_values[9]	auto[0]	auto[1]	auto[1]	24	1			T214	1		T282	2		T283	2
all_values[9]	auto[1]	auto[0]	auto[1]	78	1			T215	2		T212	2		T214	3
all_values[9]	auto[1]	auto[1]	auto[1]	50	1			T215	2		T212	2		T281	3
all_values[10]	auto[0]	auto[0]	auto[0]	58	1			T215	1		T212	2		T281	3
all_values[10]	auto[0]	auto[0]	auto[1]	29	1			T214	3		T283	1		T279	2
all_values[10]	auto[0]	auto[1]	auto[0]	52	1			T215	1		T212	1		T281	3
all_values[10]	auto[0]	auto[1]	auto[1]	27	1			T215	2		T214	1		T283	2
all_values[10]	auto[1]	auto[0]	auto[1]	53	1			T215	2		T212	3		T214	1
all_values[10]	auto[1]	auto[1]	auto[1]	59	1			T215	1		T212	1		T214	2
all_values[11]	auto[0]	auto[0]	auto[0]	59	1			T215	1		T212	3		T214	1
all_values[11]	auto[0]	auto[0]	auto[1]	25	1			T215	2		T279	1		T284	1
all_values[11]	auto[0]	auto[1]	auto[0]	46	1			T212	1		T214	3		T281	3
all_values[11]	auto[0]	auto[1]	auto[1]	27	1			T215	1		T283	3		T279	1
all_values[11]	auto[1]	auto[0]	auto[1]	63	1			T215	2		T212	1		T214	1
all_values[11]	auto[1]	auto[1]	auto[1]	58	1			T215	1		T212	2		T214	2
all_values[12]	auto[0]	auto[0]	auto[0]	54	1			T215	2		T212	2		T214	1
all_values[12]	auto[0]	auto[0]	auto[1]	35	1			T212	1		T214	2		T281	1
all_values[12]	auto[0]	auto[1]	auto[0]	48	1			T214	1		T283	1		T279	1
all_values[12]	auto[0]	auto[1]	auto[1]	32	1			T215	1		T212	1		T214	1
all_values[12]	auto[1]	auto[0]	auto[1]	51	1			T212	2		T214	1		T281	2
all_values[12]	auto[1]	auto[1]	auto[1]	58	1			T215	4		T212	1		T214	1
all_values[13]	auto[0]	auto[0]	auto[0]	44	1			T212	3		T214	1		T279	2
all_values[13]	auto[0]	auto[0]	auto[1]	24	1			T212	2		T281	1		T282	1
all_values[13]	auto[0]	auto[1]	auto[0]	59	1			T215	6		T214	2		T281	2
all_values[13]	auto[0]	auto[1]	auto[1]	32	1			T214	1		T283	1		T284	1
all_values[13]	auto[1]	auto[0]	auto[1]	53	1			T212	2		T214	3		T281	2
all_values[13]	auto[1]	auto[1]	auto[1]	66	1			T215	1		T281	2		T282	1
all_values[14]	auto[0]	auto[0]	auto[0]	73	1			T215	4		T212	1		T214	1
all_values[14]	auto[0]	auto[0]	auto[1]	18	1			T212	1		T281	1		T282	1
all_values[14]	auto[0]	auto[1]	auto[0]	64	1			T215	2		T212	1		T214	4
all_values[14]	auto[0]	auto[1]	auto[1]	14	1			T282	2		T286	1		T287	1
all_values[14]	auto[1]	auto[0]	auto[1]	54	1			T212	3		T214	1		T281	1
all_values[14]	auto[1]	auto[1]	auto[1]	55	1			T215	1		T212	1		T214	1
all_values[15]	auto[0]	auto[0]	auto[0]	55	1			T215	1		T212	1		T214	2
all_values[15]	auto[0]	auto[0]	auto[1]	29	1			T215	1		T212	1		T214	1
all_values[15]	auto[0]	auto[1]	auto[0]	53	1			T215	2		T214	1		T282	3
all_values[15]	auto[0]	auto[1]	auto[1]	29	1			T212	1		T281	1		T282	1
all_values[15]	auto[1]	auto[0]	auto[1]	62	1			T215	3		T212	3		T281	2
all_values[15]	auto[1]	auto[1]	auto[1]	50	1			T212	1		T214	3		T281	1
all_values[16]	auto[0]	auto[0]	auto[0]	60	1			T215	1		T212	3		T214	3
all_values[16]	auto[0]	auto[0]	auto[1]	27	1			T215	2		T212	1		T284	1
all_values[16]	auto[0]	auto[1]	auto[0]	46	1			T212	1		T214	2		T281	3
all_values[16]	auto[0]	auto[1]	auto[1]	27	1			T215	1		T282	3		T279	1
all_values[16]	auto[1]	auto[0]	auto[1]	67	1			T215	2		T212	1		T281	1
all_values[16]	auto[1]	auto[1]	auto[1]	51	1			T215	1		T212	1		T214	2
all_values[17]	auto[0]	auto[0]	auto[0]	92	1			T215	2		T212	2		T214	3
all_values[17]	auto[0]	auto[1]	auto[0]	72	1			T215	1		T212	1		T214	2
all_values[17]	auto[1]	auto[0]	auto[1]	68	1			T215	3		T212	3		T214	1
all_values[17]	auto[1]	auto[1]	auto[1]	46	1			T215	1		T212	1		T214	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal