Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	172057	1			T1	3		T2	4		T3	6
all_values[1]	172057	1			T1	3		T2	4		T3	6
all_values[2]	172057	1			T1	3		T2	4		T3	6
all_values[3]	172057	1			T1	3		T2	4		T3	6
all_values[4]	172057	1			T1	3		T2	4		T3	6
all_values[5]	172057	1			T1	3		T2	4		T3	6
all_values[6]	172057	1			T1	3		T2	4		T3	6
all_values[7]	172057	1			T1	3		T2	4		T3	6
all_values[8]	172057	1			T1	3		T2	4		T3	6
all_values[9]	172057	1			T1	3		T2	4		T3	6
all_values[10]	172057	1			T1	3		T2	4		T3	6
all_values[11]	172057	1			T1	3		T2	4		T3	6
all_values[12]	172057	1			T1	3		T2	4		T3	6
all_values[13]	172057	1			T1	3		T2	4		T3	6
all_values[14]	172057	1			T1	3		T2	4		T3	6
all_values[15]	172057	1			T1	3		T2	4		T3	6
all_values[16]	172057	1			T1	3		T2	4		T3	6
all_values[17]	172057	1			T1	3		T2	4		T3	6

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5496137

1

T1

96

T2

128

T3

189

auto[1]

9687

1

T3

3

T16

5

T17

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4717967

1

T1

87

T2

110

T3

177

auto[1]

787857

1

T1

9

T2

18

T3

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142999	1			T1	3		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	25739	1			T2	1		T3	3		T27	2
all_values[0]	auto[1]	auto[0]	3216	1			T42	3		T43	3		T44	3
all_values[0]	auto[1]	auto[1]	103	1			T406	1		T407	1		T408	1
all_values[1]	auto[0]	auto[0]	167567	1			T1	3		T2	4		T3	6
all_values[1]	auto[0]	auto[1]	3093	1			T18	2		T19	2		T32	1
all_values[1]	auto[1]	auto[0]	529	1			T26	2		T8	1		T33	2
all_values[1]	auto[1]	auto[1]	868	1			T26	12		T8	1		T33	1
all_values[2]	auto[0]	auto[0]	4408	1			T1	1		T2	1		T3	5
all_values[2]	auto[0]	auto[1]	167388	1			T1	2		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	134	1			T20	1		T58	1		T59	1
all_values[2]	auto[1]	auto[1]	127	1			T20	1		T58	1		T59	1
all_values[3]	auto[0]	auto[0]	170151	1			T1	3		T2	4		T3	6
all_values[3]	auto[0]	auto[1]	299	1			T30	1		T40	1		T60	1
all_values[3]	auto[1]	auto[0]	1530	1			T40	1428		T196	4		T197	3
all_values[3]	auto[1]	auto[1]	77	1			T40	1		T200	2		T197	2
all_values[4]	auto[0]	auto[0]	4393	1			T1	1		T2	1		T3	5
all_values[4]	auto[0]	auto[1]	167523	1			T1	2		T2	3		T3	1
all_values[4]	auto[1]	auto[0]	80	1			T41	1		T201	2		T200	5
all_values[4]	auto[1]	auto[1]	61	1			T41	1		T201	3		T198	1
all_values[5]	auto[0]	auto[0]	171545	1			T1	2		T2	4		T3	6
all_values[5]	auto[0]	auto[1]	342	1			T1	1		T7	1		T8	1
all_values[5]	auto[1]	auto[0]	109	1			T201	2		T200	4		T197	2
all_values[5]	auto[1]	auto[1]	61	1			T201	3		T197	2		T297	2
all_values[6]	auto[0]	auto[0]	171634	1			T1	3		T2	4		T3	6
all_values[6]	auto[0]	auto[1]	222	1			T8	1		T62	1		T152	1
all_values[6]	auto[1]	auto[0]	87	1			T201	1		T200	1		T196	1
all_values[6]	auto[1]	auto[1]	114	1			T61	1		T63	1		T64	1
all_values[7]	auto[0]	auto[0]	115133	1			T1	2		T3	1		T7	2
all_values[7]	auto[0]	auto[1]	56734	1			T1	1		T2	4		T3	2
all_values[7]	auto[1]	auto[0]	118	1			T3	2		T45	2		T46	2
all_values[7]	auto[1]	auto[1]	72	1			T3	1		T45	1		T46	1
all_values[8]	auto[0]	auto[0]	171124	1			T1	3		T2	4		T3	6
all_values[8]	auto[0]	auto[1]	256	1			T28	2		T51	2		T366	2
all_values[8]	auto[1]	auto[0]	601	1			T47	10		T49	10		T50	10
all_values[8]	auto[1]	auto[1]	76	1			T47	1		T52	1		T53	1
all_values[9]	auto[0]	auto[0]	171801	1			T1	3		T2	4		T3	6
all_values[9]	auto[0]	auto[1]	75	1			T201	3		T196	1		T198	2
all_values[9]	auto[1]	auto[0]	108	1			T16	3		T56	3		T57	3
all_values[9]	auto[1]	auto[1]	73	1			T16	2		T56	2		T57	2
all_values[10]	auto[0]	auto[0]	171516	1			T1	3		T2	4		T3	6
all_values[10]	auto[0]	auto[1]	376	1			T19	1		T29	1		T30	1
all_values[10]	auto[1]	auto[0]	98	1			T200	3		T196	4		T197	1
all_values[10]	auto[1]	auto[1]	67	1			T200	1		T197	3		T198	1
all_values[11]	auto[0]	auto[0]	171100	1			T1	3		T2	4		T3	6
all_values[11]	auto[0]	auto[1]	674	1			T17	1		T31	4		T65	4
all_values[11]	auto[1]	auto[0]	149	1			T68	1		T69	1		T70	1
all_values[11]	auto[1]	auto[1]	134	1			T68	1		T69	1		T70	1
all_values[12]	auto[0]	auto[0]	171676	1			T1	3		T2	4		T3	6
all_values[12]	auto[0]	auto[1]	215	1			T72	1		T75	1		T76	1
all_values[12]	auto[1]	auto[0]	104	1			T71	2		T73	2		T74	2
all_values[12]	auto[1]	auto[1]	62	1			T71	1		T73	1		T74	1
all_values[13]	auto[0]	auto[0]	171728	1			T1	3		T2	4		T3	6
all_values[13]	auto[0]	auto[1]	74	1			T72	1		T75	1		T76	1
all_values[13]	auto[1]	auto[0]	140	1			T17	1		T77	1		T78	1
all_values[13]	auto[1]	auto[1]	115	1			T17	1		T77	1		T78	1
all_values[14]	auto[0]	auto[0]	35562	1			T1	3		T2	4		T3	6
all_values[14]	auto[0]	auto[1]	136336	1			T20	1		T8	2		T29	1
all_values[14]	auto[1]	auto[0]	98	1			T201	3		T200	1		T196	5
all_values[14]	auto[1]	auto[1]	61	1			T200	2		T197	2		T299	1
all_values[15]	auto[0]	auto[0]	4436	1			T1	1		T2	1		T3	5
all_values[15]	auto[0]	auto[1]	167459	1			T1	2		T2	3		T3	1
all_values[15]	auto[1]	auto[0]	98	1			T201	4		T200	3		T196	2
all_values[15]	auto[1]	auto[1]	64	1			T196	2		T197	3		T198	1
all_values[16]	auto[0]	auto[0]	171001	1			T1	3		T2	4		T3	6
all_values[16]	auto[0]	auto[1]	862	1			T19	1		T60	1		T67	1
all_values[16]	auto[1]	auto[0]	125	1			T31	4		T65	4		T66	4
all_values[16]	auto[1]	auto[1]	69	1			T31	4		T65	4		T66	4
all_values[17]	auto[0]	auto[0]	113966	1			T1	2		T7	2		T16	5
all_values[17]	auto[0]	auto[1]	57932	1			T1	1		T2	4		T3	6
all_values[17]	auto[1]	auto[0]	105	1			T54	2		T55	2		T201	2
all_values[17]	auto[1]	auto[1]	54	1			T54	1		T55	1		T201	2