Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 98.23 96.05 97.44 96.61 98.42 98.21 98.46


Total tests in report: 3905
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.03 65.03 86.73 86.73 65.96 65.96 60.55 60.55 50.85 50.85 79.20 79.20 91.07 91.07 20.81 20.81 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.164227865
73.31 8.29 91.60 4.87 80.49 14.53 63.33 2.77 52.54 1.69 91.76 12.56 91.47 0.40 41.99 21.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.2149301851
80.15 6.84 94.26 2.66 85.18 4.69 87.42 24.09 62.71 10.17 95.05 3.29 93.45 1.98 42.99 1.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.3224015642
82.11 1.96 94.26 0.00 85.18 0.00 89.13 1.71 62.71 0.00 95.05 0.00 93.45 0.00 55.02 12.04 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.3880454242
84.02 1.90 94.77 0.51 86.54 1.36 90.09 0.96 71.19 8.47 95.88 0.83 93.45 0.00 56.20 1.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.2890457020
85.36 1.35 94.94 0.17 87.80 1.26 90.09 0.00 76.27 5.08 96.09 0.21 93.45 0.00 58.91 2.71 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.267686052
86.52 1.16 96.05 1.10 88.32 0.52 90.94 0.85 76.27 0.00 96.13 0.04 96.23 2.78 61.72 2.81 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4144329440
87.16 0.64 96.06 0.02 88.39 0.07 94.56 3.62 76.27 0.00 96.17 0.04 96.43 0.20 62.26 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.3152641228
87.73 0.57 96.10 0.04 89.44 1.05 94.67 0.11 76.27 0.00 96.30 0.12 96.63 0.20 64.71 2.44 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.3502954866
88.29 0.56 96.81 0.70 89.56 0.12 95.31 0.64 76.27 0.00 96.30 0.00 96.63 0.00 67.15 2.44 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.1369962544
88.83 0.55 96.98 0.17 89.65 0.10 95.31 0.00 79.66 3.39 96.46 0.17 96.63 0.00 67.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2359146156
89.33 0.49 97.00 0.02 89.65 0.00 95.31 0.00 83.05 3.39 96.51 0.04 96.63 0.00 67.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.3808162057
89.81 0.48 97.00 0.00 89.65 0.00 95.31 0.00 86.44 3.39 96.51 0.00 96.63 0.00 67.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/301.usbdev_tx_rx_disruption.2834794298
90.24 0.43 97.74 0.74 90.77 1.12 95.31 0.00 86.44 0.00 97.67 1.16 96.63 0.00 67.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.2471183778
90.59 0.34 97.74 0.00 90.82 0.05 95.52 0.21 88.14 1.69 97.67 0.00 96.63 0.00 67.60 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.3315130853
90.93 0.34 97.79 0.06 91.98 1.17 95.52 0.00 88.14 0.00 97.75 0.08 96.63 0.00 68.69 1.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.2785254006
91.23 0.30 97.79 0.00 92.01 0.02 95.52 0.00 88.14 0.00 97.75 0.00 96.63 0.00 70.77 2.08 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.2885518538
91.49 0.26 97.81 0.02 92.06 0.05 95.52 0.00 89.83 1.69 97.80 0.04 96.63 0.00 70.77 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.1221627190
91.74 0.25 97.83 0.02 92.08 0.02 95.52 0.00 91.53 1.69 97.84 0.04 96.63 0.00 70.77 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/292.usbdev_tx_rx_disruption.854138931
92.00 0.25 97.87 0.04 92.08 0.00 95.52 0.00 93.22 1.69 97.88 0.04 96.63 0.00 70.77 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_reset.1533152790
92.25 0.25 97.89 0.02 92.15 0.07 95.52 0.00 93.22 0.00 97.92 0.04 96.63 0.00 72.40 1.63 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3278793195
92.49 0.24 97.89 0.00 92.15 0.00 95.52 0.00 94.92 1.69 97.92 0.00 96.63 0.00 72.40 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/157.usbdev_tx_rx_disruption.3803521921
92.73 0.24 97.89 0.00 92.15 0.00 95.52 0.00 96.61 1.69 97.92 0.00 96.63 0.00 72.40 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.4203375683
92.94 0.21 97.89 0.00 92.20 0.05 95.52 0.00 96.61 0.00 97.92 0.00 98.02 1.39 72.40 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.3351522301
93.12 0.18 97.89 0.00 92.65 0.45 95.52 0.00 96.61 0.00 97.92 0.00 98.02 0.00 73.21 0.81 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2885621643
93.26 0.14 97.89 0.00 92.65 0.00 95.52 0.00 96.61 0.00 97.92 0.00 98.02 0.00 74.21 1.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.56533324
93.40 0.14 97.89 0.00 92.65 0.00 95.52 0.00 96.61 0.00 97.92 0.00 98.02 0.00 75.20 1.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_types.3254968841
93.54 0.14 97.91 0.02 92.82 0.17 95.74 0.21 96.61 0.00 97.96 0.04 98.02 0.00 75.75 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.1356244393
93.68 0.14 97.91 0.00 93.22 0.40 96.06 0.32 96.61 0.00 98.13 0.17 98.02 0.00 75.84 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.1273027446
93.82 0.13 97.91 0.00 93.98 0.76 96.06 0.00 96.61 0.00 98.13 0.00 98.02 0.00 76.02 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3029489345
93.95 0.13 97.91 0.00 93.98 0.00 96.06 0.00 96.61 0.00 98.13 0.00 98.02 0.00 76.92 0.90 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/131.usbdev_endpoint_types.575521866
94.06 0.12 97.91 0.00 93.98 0.00 96.06 0.00 96.61 0.00 98.13 0.00 98.02 0.00 77.74 0.81 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/161.usbdev_endpoint_types.1112423076
94.18 0.11 97.91 0.00 94.03 0.05 96.27 0.21 96.61 0.00 98.13 0.00 98.02 0.00 78.28 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.3725907623
94.28 0.10 97.91 0.00 94.03 0.00 96.27 0.00 96.61 0.00 98.13 0.00 98.02 0.00 79.00 0.72 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/10.usbdev_endpoint_types.453130729
94.38 0.10 97.91 0.00 94.03 0.00 96.27 0.00 96.61 0.00 98.13 0.00 98.02 0.00 79.73 0.72 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/113.usbdev_endpoint_types.4157662636
94.49 0.10 97.91 0.00 94.03 0.00 96.27 0.00 96.61 0.00 98.13 0.00 98.02 0.00 80.45 0.72 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/79.usbdev_endpoint_types.1013888618
94.59 0.10 97.91 0.00 94.08 0.05 96.48 0.21 96.61 0.00 98.13 0.00 98.02 0.00 80.90 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.29300824
94.69 0.10 97.91 0.00 94.12 0.05 96.70 0.21 96.61 0.00 98.13 0.00 98.02 0.00 81.36 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.3680777435
94.78 0.09 97.95 0.04 94.29 0.17 96.70 0.00 96.61 0.00 98.21 0.08 98.02 0.00 81.72 0.36 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.3057771582
94.87 0.09 97.95 0.00 94.29 0.00 96.70 0.00 96.61 0.00 98.21 0.00 98.02 0.00 82.35 0.63 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/141.usbdev_endpoint_types.3543444263
94.96 0.08 97.95 0.00 94.31 0.02 96.70 0.00 96.61 0.00 98.21 0.00 98.02 0.00 82.90 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/6.usbdev_device_address.3825933084
95.03 0.08 97.95 0.00 94.31 0.00 96.70 0.00 96.61 0.00 98.21 0.00 98.02 0.00 83.44 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.1315252870
95.11 0.08 97.95 0.00 94.31 0.00 96.70 0.00 96.61 0.00 98.21 0.00 98.02 0.00 83.98 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/132.usbdev_endpoint_types.4082122257
95.19 0.08 97.95 0.00 94.31 0.00 96.70 0.00 96.61 0.00 98.21 0.00 98.02 0.00 84.52 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/14.usbdev_endpoint_types.1216777893
95.27 0.08 97.95 0.00 94.31 0.00 96.70 0.00 96.61 0.00 98.21 0.00 98.02 0.00 85.07 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_types.3429289698
95.34 0.08 97.95 0.00 94.31 0.00 96.70 0.00 96.61 0.00 98.21 0.00 98.02 0.00 85.61 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.660197930
95.42 0.08 98.00 0.06 94.34 0.02 96.70 0.00 96.61 0.00 98.29 0.08 98.02 0.00 85.97 0.36 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/6.usbdev_fifo_levels.1225491700
95.48 0.06 98.00 0.00 94.34 0.00 96.70 0.00 96.61 0.00 98.29 0.00 98.02 0.00 86.43 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/24.usbdev_data_toggle_restore.1653422121
95.55 0.06 98.00 0.00 94.34 0.00 96.70 0.00 96.61 0.00 98.29 0.00 98.02 0.00 86.88 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/34.usbdev_endpoint_types.1553161770
95.61 0.06 98.00 0.00 94.34 0.00 96.70 0.00 96.61 0.00 98.29 0.00 98.02 0.00 87.33 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/39.usbdev_endpoint_types.480744993
95.67 0.06 98.08 0.08 94.34 0.00 97.01 0.32 96.61 0.00 98.29 0.00 98.02 0.00 87.33 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_disconnect.1255800433
95.72 0.06 98.08 0.00 94.46 0.12 97.01 0.00 96.61 0.00 98.29 0.00 98.02 0.00 87.60 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.2070272999
95.78 0.05 98.08 0.00 94.46 0.00 97.01 0.00 96.61 0.00 98.29 0.00 98.02 0.00 87.96 0.36 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.3254689267
95.83 0.05 98.14 0.06 94.48 0.02 97.01 0.00 96.61 0.00 98.29 0.00 98.02 0.00 88.24 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.1932477988
95.88 0.05 98.19 0.06 94.55 0.07 97.23 0.21 96.61 0.00 98.29 0.00 98.02 0.00 88.24 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.565055406
95.92 0.04 98.19 0.00 94.58 0.02 97.23 0.00 96.61 0.00 98.29 0.00 98.02 0.00 88.51 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.3429126116
95.96 0.04 98.19 0.00 94.67 0.10 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.20 88.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_stress_usb_traffic.4102433380
96.00 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 88.78 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.2286041791
96.04 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 89.05 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.2401897489
96.08 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 89.32 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk.2640784253
96.12 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 89.59 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/163.usbdev_endpoint_types.4090368363
96.15 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 89.86 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/166.usbdev_endpoint_types.2921296753
96.19 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 90.14 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/173.usbdev_endpoint_types.929987564
96.23 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 90.41 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/22.usbdev_device_address.567223621
96.27 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 90.68 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/31.usbdev_data_toggle_restore.4081975843
96.31 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 90.95 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/37.usbdev_endpoint_types.4280159329
96.35 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 91.22 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/4.usbdev_device_address.721406471
96.39 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 91.49 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/47.usbdev_endpoint_types.462886730
96.43 0.04 98.19 0.00 94.67 0.00 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 91.76 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.328607999
96.46 0.03 98.19 0.00 94.91 0.24 97.23 0.00 96.61 0.00 98.29 0.00 98.21 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.3599000244
96.49 0.03 98.19 0.00 94.91 0.00 97.44 0.21 96.61 0.00 98.29 0.00 98.21 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/5.usbdev_tx_rx_disruption.2182366523
96.52 0.03 98.19 0.00 94.93 0.02 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 91.95 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.2758903186
96.55 0.03 98.19 0.00 95.12 0.19 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 91.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.1175540893
96.57 0.03 98.19 0.00 95.12 0.00 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 92.13 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.4147722929
96.60 0.03 98.19 0.00 95.12 0.00 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 92.31 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/136.usbdev_endpoint_types.2656789344
96.62 0.03 98.19 0.00 95.12 0.00 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 92.49 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/148.usbdev_endpoint_types.1374670319
96.65 0.03 98.19 0.00 95.12 0.00 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 92.67 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/15.usbdev_endpoint_types.1716403932
96.68 0.03 98.19 0.00 95.12 0.00 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 92.85 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_freq_hiclk_max.485296359
96.70 0.03 98.19 0.00 95.12 0.00 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 93.03 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/35.usbdev_rx_full.4087942904
96.73 0.03 98.19 0.00 95.12 0.00 97.44 0.00 96.61 0.00 98.29 0.00 98.21 0.00 93.21 0.18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_types.401789009
96.75 0.02 98.21 0.02 95.12 0.00 97.44 0.00 96.61 0.00 98.34 0.04 98.21 0.00 93.30 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/15.usbdev_fifo_levels.3178366481
96.77 0.02 98.21 0.00 95.27 0.14 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.30 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/11.usbdev_phy_pins_sense.4034833883
96.79 0.02 98.21 0.00 95.29 0.02 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.39 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.1499494091
96.80 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.48 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.3561166914
96.81 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.57 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.2444327771
96.82 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.67 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.3599628027
96.84 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.76 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.2738811856
96.85 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.85 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.852836207
96.86 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 93.94 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.57183577
96.88 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.03 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.4114008742
96.89 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.12 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.86255795
96.90 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.21 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/10.usbdev_fifo_levels.3016341413
96.91 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.30 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/100.usbdev_fifo_levels.4280161080
96.93 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.39 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/102.usbdev_endpoint_types.3147180763
96.94 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.48 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/103.usbdev_fifo_levels.2523091626
96.95 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.57 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/105.usbdev_fifo_levels.313661353
96.97 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.66 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/106.usbdev_fifo_levels.240482337
96.98 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.75 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/108.usbdev_fifo_levels.2094954725
96.99 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.84 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/109.usbdev_fifo_levels.3110443453
97.01 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 94.93 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/11.usbdev_device_address.1248937677
97.02 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.02 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/110.usbdev_endpoint_types.2902184218
97.03 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.11 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/111.usbdev_fifo_levels.3351487674
97.04 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.20 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/112.usbdev_fifo_levels.4214249134
97.06 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.29 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/114.usbdev_fifo_levels.3785374371
97.07 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.38 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/115.usbdev_fifo_levels.2288536379
97.08 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.48 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/116.usbdev_fifo_levels.2580248607
97.10 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.57 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/117.usbdev_fifo_levels.2704877738
97.11 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.66 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/118.usbdev_endpoint_types.3981665039
97.12 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.75 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/118.usbdev_fifo_levels.524505372
97.13 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.84 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/119.usbdev_fifo_levels.34536226
97.15 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 95.93 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/120.usbdev_fifo_levels.703858260
97.16 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.02 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/125.usbdev_fifo_levels.3884612907
97.17 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.11 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/128.usbdev_fifo_levels.1266709863
97.19 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.20 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/129.usbdev_endpoint_types.3700497977
97.20 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.29 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/13.usbdev_fifo_levels.2372458952
97.21 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.38 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/130.usbdev_fifo_levels.3905895453
97.23 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.47 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/137.usbdev_fifo_levels.1685891505
97.24 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.56 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/139.usbdev_fifo_levels.1038629450
97.25 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.65 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/14.usbdev_fifo_levels.3847937455
97.26 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.74 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/141.usbdev_fifo_levels.960091564
97.28 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.83 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/142.usbdev_endpoint_types.819428605
97.29 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 96.92 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/143.usbdev_fifo_levels.302091396
97.30 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.01 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/144.usbdev_endpoint_types.1458057735
97.32 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.10 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/148.usbdev_fifo_levels.1252818111
97.33 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.19 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/151.usbdev_fifo_levels.3092791005
97.34 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.29 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/156.usbdev_fifo_levels.4179026337
97.35 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.38 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/157.usbdev_endpoint_types.622352956
97.37 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.47 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/158.usbdev_endpoint_types.1048054104
97.38 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.56 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/159.usbdev_fifo_levels.961082951
97.39 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.65 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/16.usbdev_data_toggle_restore.2612723966
97.41 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.74 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/16.usbdev_rx_full.1969766686
97.42 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.83 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/160.usbdev_endpoint_types.1586698553
97.43 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 97.92 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/180.usbdev_endpoint_types.1874747542
97.44 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 98.01 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_levels.2953017921
97.46 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 98.10 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/23.usbdev_endpoint_types.2673740928
97.47 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 98.19 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/28.usbdev_fifo_levels.3364849832
97.48 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 98.28 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/37.usbdev_fifo_levels.4222352298
97.50 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 98.37 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/52.usbdev_endpoint_types.1783659192
97.51 0.01 98.21 0.00 95.29 0.00 97.44 0.00 96.61 0.00 98.34 0.00 98.21 0.00 98.46 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.3234089496
97.52 0.01 98.21 0.00 95.34 0.05 97.44 0.00 96.61 0.00 98.38 0.04 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.3269897155
97.53 0.01 98.23 0.02 95.36 0.02 97.44 0.00 96.61 0.00 98.42 0.04 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_reset.1419348229
97.54 0.01 98.23 0.00 95.43 0.07 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.1809117135
97.55 0.01 98.23 0.00 95.48 0.05 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.173244687
97.56 0.01 98.23 0.00 95.53 0.05 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.1463200805
97.56 0.01 98.23 0.00 95.58 0.05 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.3343400572
97.57 0.01 98.23 0.00 95.62 0.05 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.95151434
97.58 0.01 98.23 0.00 95.67 0.05 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.3299161277
97.59 0.01 98.23 0.00 95.72 0.05 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.2226530163
97.59 0.01 98.23 0.00 95.74 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.4275272499
97.59 0.01 98.23 0.00 95.77 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.3665877732
97.60 0.01 98.23 0.00 95.79 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2919158933
97.60 0.01 98.23 0.00 95.81 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.1023627842
97.60 0.01 98.23 0.00 95.84 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/10.usbdev_nak_trans.2403483341
97.61 0.01 98.23 0.00 95.86 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/11.usbdev_nak_trans.2446227783
97.61 0.01 98.23 0.00 95.88 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/12.usbdev_nak_trans.1105024105
97.61 0.01 98.23 0.00 95.91 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/13.usbdev_nak_trans.4051803878
97.62 0.01 98.23 0.00 95.93 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/16.usbdev_nak_trans.1530512869
97.62 0.01 98.23 0.00 95.96 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/19.usbdev_nak_trans.957184803
97.62 0.01 98.23 0.00 95.98 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/20.usbdev_nak_trans.2680980543
97.63 0.01 98.23 0.00 96.00 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/29.usbdev_nak_trans.424540279
97.63 0.01 98.23 0.00 96.03 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.2343825316
97.63 0.01 98.23 0.00 96.05 0.02 97.44 0.00 96.61 0.00 98.42 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.1998531537

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.1264768272
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4108421724
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2522238796
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.3299370051
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.93820589
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.805111370
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3403647121
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.3324403371
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.3587546444
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3449678684
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.701316729
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3799932230
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2638617265
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.2948442065
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.2145461638
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.537796270
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.90902779
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.1938177744
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2453725518
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.1802405695
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1086920856
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.1912287447
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3882644455
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.548150829
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.2620145266
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1623836059
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.1765966176
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.341633989
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1020676949
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.3391846308
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.297001233
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.552137689
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.1081321386
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.4293809588
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2623712357
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.1719289458
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.3664449814
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.554299162
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.2296402419
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.1799130507
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.157108155
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.598714773
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.1682812915
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2178697925
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.2591968788
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.309393808
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.544770242
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1515234660
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.3664717617
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.228334901
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.3337867464
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.1530289030
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4064173890
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.943654435
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.359526663
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1943088972
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.57863443
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.1866056066
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1692544770
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.2636101963
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.1527025424
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3898419211
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.3551476145
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.1902858904
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1917494481
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.1637059526
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.2302757645
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1858427471
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.1128462925
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.946400664
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.412051815
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.2671513797
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.2774882799
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2000920659
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3430229904
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.745202673
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.24894366
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.1890150268
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.3917928346
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.2197618744
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.105107943
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.4175355232
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.3283078788
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.3712379530
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.4066825759
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.4240160686
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.2506782807
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.880205603
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.2008413018
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.61964437
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.2226162463
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.889602954
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.2150793811
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.434084388
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.761227695
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2675697268
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1742277120
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.579179825
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.890340279
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.748719734
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3299982038
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.2973902729
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.1659221253
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.1968076435
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.2888832479
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.2395155368
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.1714983735
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.3291248933
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.2184164676
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.3133547061
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.1800844967
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.2973242948
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.3875841985
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.768173596
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1204959014
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.978299530
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.342159429
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.3688785360
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.2291302978
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.3494777985
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.1602493105
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4058520672
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.1525170194
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.3700125630
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.93712858
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.823686532
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.3559767703
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.2967135044
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.1918438106
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.932134693
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.766815961
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.957687888
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2433832142
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.3859157979
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.1159416396
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.122545795
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.2121311752
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.3088120142
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1426684648
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.3558329116
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2314214036
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.3151250309
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.1016019440
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.553854394
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.2718939229
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/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/9.usbdev_low_speed_traffic.4192308420
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/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/9.usbdev_max_non_iso_usb_traffic.4081598355
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/9.usbdev_max_usb_traffic.1436625835
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/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.93851035
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/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.1830848517
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Total test records in report: 3905
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.1391048291 Oct 12 04:34:53 PM UTC 24 Oct 12 04:35:00 PM UTC 24 4167340502 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.1439042536 Oct 12 04:35:35 PM UTC 24 Oct 12 04:35:38 PM UTC 24 184147517 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.173244687 Oct 12 04:35:35 PM UTC 24 Oct 12 04:35:38 PM UTC 24 195484458 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.3224015642 Oct 12 04:35:01 PM UTC 24 Oct 12 04:35:40 PM UTC 24 14611478027 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.1175540893 Oct 12 04:35:39 PM UTC 24 Oct 12 04:35:42 PM UTC 24 167072796 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.3725907623 Oct 12 04:35:39 PM UTC 24 Oct 12 04:35:42 PM UTC 24 158431396 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3635407965 Oct 12 04:35:41 PM UTC 24 Oct 12 04:35:44 PM UTC 24 188984410 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.164227865 Oct 12 04:35:44 PM UTC 24 Oct 12 04:35:48 PM UTC 24 716774949 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.3315130853 Oct 12 04:35:54 PM UTC 24 Oct 12 04:35:56 PM UTC 24 184903859 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.3676849890 Oct 12 04:35:54 PM UTC 24 Oct 12 04:35:56 PM UTC 24 364544502 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_enable.856808140 Oct 12 04:35:58 PM UTC 24 Oct 12 04:36:00 PM UTC 24 54213374 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.2297960646 Oct 12 04:36:02 PM UTC 24 Oct 12 04:36:09 PM UTC 24 994042479 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.2444327771 Oct 12 04:36:10 PM UTC 24 Oct 12 04:36:14 PM UTC 24 247403170 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.3599628027 Oct 12 04:36:14 PM UTC 24 Oct 12 04:36:17 PM UTC 24 170755923 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.4117104090 Oct 12 04:36:18 PM UTC 24 Oct 12 04:36:24 PM UTC 24 415724025 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.2890457020 Oct 12 04:35:11 PM UTC 24 Oct 12 04:36:32 PM UTC 24 28663585628 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.709139497 Oct 12 04:35:50 PM UTC 24 Oct 12 04:36:37 PM UTC 24 1815032497 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.1463200805 Oct 12 04:35:46 PM UTC 24 Oct 12 04:36:41 PM UTC 24 5554135223 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.743632992 Oct 12 04:36:43 PM UTC 24 Oct 12 04:36:47 PM UTC 24 514806721 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.2332424636 Oct 12 04:36:49 PM UTC 24 Oct 12 04:36:52 PM UTC 24 264430207 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.788469654 Oct 12 04:36:53 PM UTC 24 Oct 12 04:36:56 PM UTC 24 143372503 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.3343400572 Oct 12 04:36:37 PM UTC 24 Oct 12 04:36:59 PM UTC 24 4178332410 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.3529371131 Oct 12 04:36:57 PM UTC 24 Oct 12 04:37:00 PM UTC 24 197449272 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.1143012418 Oct 12 04:37:00 PM UTC 24 Oct 12 04:37:02 PM UTC 24 170653024 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.95151434 Oct 12 04:37:02 PM UTC 24 Oct 12 04:37:04 PM UTC 24 165898138 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.3057771582 Oct 12 04:37:02 PM UTC 24 Oct 12 04:37:05 PM UTC 24 519939154 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.1520701151 Oct 12 04:37:06 PM UTC 24 Oct 12 04:37:21 PM UTC 24 3358103628 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.872545265 Oct 12 04:36:49 PM UTC 24 Oct 12 04:37:34 PM UTC 24 3121456972 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.4106542703 Oct 12 04:37:34 PM UTC 24 Oct 12 04:37:37 PM UTC 24 232298647 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.4220037430 Oct 12 04:37:38 PM UTC 24 Oct 12 04:37:41 PM UTC 24 202868940 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.2738811856 Oct 12 04:37:06 PM UTC 24 Oct 12 04:37:49 PM UTC 24 3880378148 ps
T619 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.1340127929 Oct 12 04:37:51 PM UTC 24 Oct 12 04:37:53 PM UTC 24 173900621 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.2149301851 Oct 12 04:35:44 PM UTC 24 Oct 12 04:37:57 PM UTC 24 40875441640 ps
T620 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.598467362 Oct 12 04:37:55 PM UTC 24 Oct 12 04:37:57 PM UTC 24 137146731 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.3364003107 Oct 12 04:37:04 PM UTC 24 Oct 12 04:38:01 PM UTC 24 27123267177 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.3059122257 Oct 12 04:38:00 PM UTC 24 Oct 12 04:38:03 PM UTC 24 180322766 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.1932477988 Oct 12 04:38:00 PM UTC 24 Oct 12 04:38:03 PM UTC 24 263120736 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.32830990 Oct 12 04:38:00 PM UTC 24 Oct 12 04:38:04 PM UTC 24 470727705 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.165199053 Oct 12 04:38:02 PM UTC 24 Oct 12 04:38:05 PM UTC 24 155805819 ps
T552 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.1350425936 Oct 12 04:38:02 PM UTC 24 Oct 12 04:38:05 PM UTC 24 187663251 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.1999857366 Oct 12 04:38:04 PM UTC 24 Oct 12 04:38:07 PM UTC 24 157636159 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2467076443 Oct 12 04:38:04 PM UTC 24 Oct 12 04:38:07 PM UTC 24 169281121 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.1273027446 Oct 12 04:38:04 PM UTC 24 Oct 12 04:38:07 PM UTC 24 240796336 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.645016118 Oct 12 04:38:06 PM UTC 24 Oct 12 04:38:09 PM UTC 24 218449805 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.917378174 Oct 12 04:38:06 PM UTC 24 Oct 12 04:38:09 PM UTC 24 242989173 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.3269897155 Oct 12 04:38:09 PM UTC 24 Oct 12 04:38:11 PM UTC 24 148472051 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2296544531 Oct 12 04:38:09 PM UTC 24 Oct 12 04:38:11 PM UTC 24 236622112 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2359146156 Oct 12 04:38:09 PM UTC 24 Oct 12 04:38:12 PM UTC 24 314545156 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.2471183778 Oct 12 04:38:11 PM UTC 24 Oct 12 04:38:13 PM UTC 24 70634992 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.2401897489 Oct 12 04:38:13 PM UTC 24 Oct 12 04:38:15 PM UTC 24 155689134 ps
T589 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.3945136649 Oct 12 04:38:13 PM UTC 24 Oct 12 04:38:15 PM UTC 24 156828440 ps
T621 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.811573131 Oct 12 04:38:13 PM UTC 24 Oct 12 04:38:16 PM UTC 24 224246750 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.3301081579 Oct 12 04:38:15 PM UTC 24 Oct 12 04:38:18 PM UTC 24 210364764 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.1716099107 Oct 12 04:37:22 PM UTC 24 Oct 12 04:38:23 PM UTC 24 1948740939 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.2063310560 Oct 12 04:37:41 PM UTC 24 Oct 12 04:38:24 PM UTC 24 3092513223 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.29300824 Oct 12 04:38:26 PM UTC 24 Oct 12 04:38:28 PM UTC 24 159781146 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.1356244393 Oct 12 04:38:26 PM UTC 24 Oct 12 04:38:29 PM UTC 24 268948009 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.3299161277 Oct 12 04:38:30 PM UTC 24 Oct 12 04:38:32 PM UTC 24 164244385 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.1695215149 Oct 12 04:38:30 PM UTC 24 Oct 12 04:38:33 PM UTC 24 206278024 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.3429126116 Oct 12 04:38:30 PM UTC 24 Oct 12 04:38:33 PM UTC 24 400666239 ps
T622 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.2165706075 Oct 12 04:38:34 PM UTC 24 Oct 12 04:38:36 PM UTC 24 170448930 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.852836207 Oct 12 04:38:34 PM UTC 24 Oct 12 04:38:37 PM UTC 24 177347816 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.2827108667 Oct 12 04:38:34 PM UTC 24 Oct 12 04:38:37 PM UTC 24 220499537 ps
T559 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.228071500 Oct 12 04:38:38 PM UTC 24 Oct 12 04:38:41 PM UTC 24 162017341 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.57183577 Oct 12 04:38:38 PM UTC 24 Oct 12 04:38:41 PM UTC 24 197727178 ps
T623 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.502238208 Oct 12 04:38:43 PM UTC 24 Oct 12 04:38:47 PM UTC 24 831238846 ps
T624 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.690943272 Oct 12 04:39:00 PM UTC 24 Oct 12 04:39:02 PM UTC 24 185334161 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.3957974383 Oct 12 04:38:17 PM UTC 24 Oct 12 04:38:52 PM UTC 24 6154104646 ps
T581 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.3272940586 Oct 12 04:35:58 PM UTC 24 Oct 12 04:38:54 PM UTC 24 5151458163 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.1924593735 Oct 12 04:39:02 PM UTC 24 Oct 12 04:39:04 PM UTC 24 162264096 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.2454761236 Oct 12 04:38:53 PM UTC 24 Oct 12 04:38:56 PM UTC 24 545584356 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.565055406 Oct 12 04:38:55 PM UTC 24 Oct 12 04:38:57 PM UTC 24 43171308 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.3152641228 Oct 12 04:38:53 PM UTC 24 Oct 12 04:38:58 PM UTC 24 1264709274 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.3502954866 Oct 12 04:38:17 PM UTC 24 Oct 12 04:38:58 PM UTC 24 6670559198 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.1984453094 Oct 12 04:37:51 PM UTC 24 Oct 12 04:38:59 PM UTC 24 1935807195 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.547910335 Oct 12 04:39:00 PM UTC 24 Oct 12 04:39:02 PM UTC 24 143962889 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.2642537029 Oct 12 04:39:00 PM UTC 24 Oct 12 04:39:02 PM UTC 24 161882072 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.1221627190 Oct 12 04:38:19 PM UTC 24 Oct 12 04:39:03 PM UTC 24 20213631427 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.3609264577 Oct 12 04:39:04 PM UTC 24 Oct 12 04:39:07 PM UTC 24 346683326 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.1670392512 Oct 12 04:39:04 PM UTC 24 Oct 12 04:39:07 PM UTC 24 169728772 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.3505124624 Oct 12 04:38:57 PM UTC 24 Oct 12 04:39:07 PM UTC 24 3980714777 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.3712291184 Oct 12 04:39:04 PM UTC 24 Oct 12 04:39:08 PM UTC 24 483377843 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_enable.2815873178 Oct 12 04:39:09 PM UTC 24 Oct 12 04:39:11 PM UTC 24 49573417 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.3429828881 Oct 12 04:39:09 PM UTC 24 Oct 12 04:39:11 PM UTC 24 142515020 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.2341224660 Oct 12 04:39:08 PM UTC 24 Oct 12 04:39:13 PM UTC 24 743712699 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.463193871 Oct 12 04:39:11 PM UTC 24 Oct 12 04:39:14 PM UTC 24 302359090 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.2979687815 Oct 12 04:39:09 PM UTC 24 Oct 12 04:39:14 PM UTC 24 891164521 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.4122269335 Oct 12 04:38:43 PM UTC 24 Oct 12 04:39:15 PM UTC 24 2611971148 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.4114008742 Oct 12 04:39:13 PM UTC 24 Oct 12 04:39:16 PM UTC 24 274418083 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.3901300396 Oct 12 04:39:13 PM UTC 24 Oct 12 04:39:16 PM UTC 24 334515170 ps
T611 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk.3473722596 Oct 12 04:36:25 PM UTC 24 Oct 12 04:39:16 PM UTC 24 90180355319 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.2667130425 Oct 12 04:38:57 PM UTC 24 Oct 12 04:39:20 PM UTC 24 15339939743 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.3889149854 Oct 12 04:39:18 PM UTC 24 Oct 12 04:39:21 PM UTC 24 192581502 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.3665877732 Oct 12 04:36:58 PM UTC 24 Oct 12 04:39:23 PM UTC 24 13346820874 ps
T625 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.369257034 Oct 12 04:39:22 PM UTC 24 Oct 12 04:39:25 PM UTC 24 133226876 ps
T626 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.1242804220 Oct 12 04:39:22 PM UTC 24 Oct 12 04:39:25 PM UTC 24 208738341 ps
T627 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.3847888502 Oct 12 04:39:27 PM UTC 24 Oct 12 04:39:29 PM UTC 24 196331757 ps
T612 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk_max.1484203177 Oct 12 04:36:29 PM UTC 24 Oct 12 04:39:31 PM UTC 24 97328926705 ps
T613 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk_max.725511051 Oct 12 04:36:33 PM UTC 24 Oct 12 04:39:39 PM UTC 24 101174403173 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.1096658047 Oct 12 04:39:00 PM UTC 24 Oct 12 04:39:43 PM UTC 24 30965508348 ps
T628 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.1109682362 Oct 12 04:39:06 PM UTC 24 Oct 12 04:39:46 PM UTC 24 3372569313 ps
T629 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.2285023490 Oct 12 04:39:44 PM UTC 24 Oct 12 04:39:47 PM UTC 24 239911492 ps
T630 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.2677361870 Oct 12 04:39:46 PM UTC 24 Oct 12 04:39:49 PM UTC 24 211717671 ps
T631 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_freq_phase.602729776 Oct 12 04:36:35 PM UTC 24 Oct 12 04:39:51 PM UTC 24 102194921540 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.1499494091 Oct 12 04:38:11 PM UTC 24 Oct 12 04:39:54 PM UTC 24 20597923463 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.2070272999 Oct 12 04:37:43 PM UTC 24 Oct 12 04:39:58 PM UTC 24 3393577634 ps
T632 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.1022442916 Oct 12 04:39:40 PM UTC 24 Oct 12 04:39:58 PM UTC 24 1603474133 ps
T633 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.2846336036 Oct 12 04:39:56 PM UTC 24 Oct 12 04:39:58 PM UTC 24 161971361 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.2785254006 Oct 12 04:38:51 PM UTC 24 Oct 12 04:40:02 PM UTC 24 10806405564 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.2952441012 Oct 12 04:39:27 PM UTC 24 Oct 12 04:40:02 PM UTC 24 15233274419 ps
T634 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.139261587 Oct 12 04:40:00 PM UTC 24 Oct 12 04:40:03 PM UTC 24 168425365 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.2283065300 Oct 12 04:40:00 PM UTC 24 Oct 12 04:40:03 PM UTC 24 162689662 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2919158933 Oct 12 04:40:00 PM UTC 24 Oct 12 04:40:03 PM UTC 24 175456600 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.3808162057 Oct 12 04:39:31 PM UTC 24 Oct 12 04:40:04 PM UTC 24 10881394171 ps
T560 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.1816066719 Oct 12 04:40:02 PM UTC 24 Oct 12 04:40:05 PM UTC 24 172396455 ps
T553 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.3362332571 Oct 12 04:40:05 PM UTC 24 Oct 12 04:40:07 PM UTC 24 176045446 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.3889765309 Oct 12 04:40:05 PM UTC 24 Oct 12 04:40:07 PM UTC 24 178453254 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.2224901240 Oct 12 04:40:05 PM UTC 24 Oct 12 04:40:07 PM UTC 24 172771108 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.2136557258 Oct 12 04:40:05 PM UTC 24 Oct 12 04:40:07 PM UTC 24 202751552 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.4161536218 Oct 12 04:40:05 PM UTC 24 Oct 12 04:40:08 PM UTC 24 227453835 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.4162946237 Oct 12 04:40:07 PM UTC 24 Oct 12 04:40:09 PM UTC 24 54852756 ps
T585 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.614802308 Oct 12 04:39:18 PM UTC 24 Oct 12 04:40:11 PM UTC 24 4108579765 ps
T635 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.3301168760 Oct 12 04:40:09 PM UTC 24 Oct 12 04:40:12 PM UTC 24 187854899 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.2373974902 Oct 12 04:40:09 PM UTC 24 Oct 12 04:40:12 PM UTC 24 186659582 ps
T636 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.2700031924 Oct 12 04:40:09 PM UTC 24 Oct 12 04:40:12 PM UTC 24 210891299 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.2117166570 Oct 12 04:38:38 PM UTC 24 Oct 12 04:40:12 PM UTC 24 2336765200 ps
T637 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.4208923278 Oct 12 04:40:09 PM UTC 24 Oct 12 04:40:12 PM UTC 24 224812404 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.2988345687 Oct 12 04:40:14 PM UTC 24 Oct 12 04:40:16 PM UTC 24 157052976 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.917252514 Oct 12 04:40:14 PM UTC 24 Oct 12 04:40:17 PM UTC 24 251942835 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.2401447965 Oct 12 04:40:14 PM UTC 24 Oct 12 04:40:17 PM UTC 24 365427752 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2885621643 Oct 12 04:39:04 PM UTC 24 Oct 12 04:40:17 PM UTC 24 31915880357 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.2997973334 Oct 12 04:40:14 PM UTC 24 Oct 12 04:40:18 PM UTC 24 432973329 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.38004813 Oct 12 04:39:51 PM UTC 24 Oct 12 04:40:20 PM UTC 24 1778876960 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.1748618301 Oct 12 04:40:19 PM UTC 24 Oct 12 04:40:21 PM UTC 24 201981103 ps
T638 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.1090759649 Oct 12 04:40:19 PM UTC 24 Oct 12 04:40:21 PM UTC 24 154955470 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.3678044584 Oct 12 04:40:19 PM UTC 24 Oct 12 04:40:21 PM UTC 24 166613280 ps
T639 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.3007051237 Oct 12 04:40:19 PM UTC 24 Oct 12 04:40:22 PM UTC 24 206708953 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.267686052 Oct 12 04:39:34 PM UTC 24 Oct 12 04:40:22 PM UTC 24 4478421313 ps
T561 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.2506295789 Oct 12 04:40:21 PM UTC 24 Oct 12 04:40:24 PM UTC 24 160976821 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.1678609439 Oct 12 04:40:50 PM UTC 24 Oct 12 04:40:52 PM UTC 24 159402289 ps
T640 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.811125619 Oct 12 04:40:23 PM UTC 24 Oct 12 04:40:26 PM UTC 24 167534505 ps
T641 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.1553009820 Oct 12 04:39:53 PM UTC 24 Oct 12 04:40:27 PM UTC 24 2575928964 ps
T642 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.135733392 Oct 12 04:40:23 PM UTC 24 Oct 12 04:40:30 PM UTC 24 1187921098 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.1023627842 Oct 12 04:40:26 PM UTC 24 Oct 12 04:40:30 PM UTC 24 576692569 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.3919401627 Oct 12 04:40:50 PM UTC 24 Oct 12 04:40:54 PM UTC 24 548952184 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.1573521312 Oct 12 04:40:28 PM UTC 24 Oct 12 04:40:30 PM UTC 24 36187705 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.2589562595 Oct 12 04:40:28 PM UTC 24 Oct 12 04:40:32 PM UTC 24 786957269 ps
T643 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.3185370061 Oct 12 04:40:32 PM UTC 24 Oct 12 04:40:35 PM UTC 24 208124093 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.2226530163 Oct 12 04:40:34 PM UTC 24 Oct 12 04:40:37 PM UTC 24 154227050 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.1809117135 Oct 12 04:40:37 PM UTC 24 Oct 12 04:40:39 PM UTC 24 136752857 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.1925567393 Oct 12 04:40:19 PM UTC 24 Oct 12 04:40:41 PM UTC 24 2167956486 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.3733386204 Oct 12 04:40:39 PM UTC 24 Oct 12 04:40:41 PM UTC 24 137359857 ps
T644 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.2416864732 Oct 12 04:40:41 PM UTC 24 Oct 12 04:40:44 PM UTC 24 397891384 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.86255795 Oct 12 04:40:12 PM UTC 24 Oct 12 04:40:48 PM UTC 24 5846877866 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.1805719676 Oct 12 04:40:07 PM UTC 24 Oct 12 04:40:49 PM UTC 24 14960651083 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.1916535559 Oct 12 04:40:43 PM UTC 24 Oct 12 04:40:49 PM UTC 24 1077105524 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.1536743780 Oct 12 04:40:14 PM UTC 24 Oct 12 04:40:50 PM UTC 24 20186059456 ps
T645 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_enable.2148020016 Oct 12 04:40:52 PM UTC 24 Oct 12 04:40:54 PM UTC 24 53087991 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.3021642242 Oct 12 04:40:30 PM UTC 24 Oct 12 04:40:58 PM UTC 24 10245197914 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_levels.2953017921 Oct 12 04:40:56 PM UTC 24 Oct 12 04:40:59 PM UTC 24 245049793 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.1555185803 Oct 12 04:40:56 PM UTC 24 Oct 12 04:41:00 PM UTC 24 417863238 ps
T646 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.902966272 Oct 12 04:40:54 PM UTC 24 Oct 12 04:41:00 PM UTC 24 943252852 ps
T647 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.2332318296 Oct 12 04:39:49 PM UTC 24 Oct 12 04:41:03 PM UTC 24 2333731836 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.575037982 Oct 12 04:41:00 PM UTC 24 Oct 12 04:41:05 PM UTC 24 341166337 ps
T648 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.765314614 Oct 12 04:40:45 PM UTC 24 Oct 12 04:41:08 PM UTC 24 873637487 ps
T590 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.73712081 Oct 12 04:41:07 PM UTC 24 Oct 12 04:41:10 PM UTC 24 220982106 ps
T649 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.3915268865 Oct 12 04:41:09 PM UTC 24 Oct 12 04:41:11 PM UTC 24 140539576 ps
T650 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.2312796198 Oct 12 04:40:50 PM UTC 24 Oct 12 04:41:12 PM UTC 24 1957183812 ps
T651 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.2935856568 Oct 12 04:41:11 PM UTC 24 Oct 12 04:41:14 PM UTC 24 249015949 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.1573528936 Oct 12 04:40:30 PM UTC 24 Oct 12 04:41:16 PM UTC 24 15262869751 ps
T652 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.2318235851 Oct 12 04:41:13 PM UTC 24 Oct 12 04:41:16 PM UTC 24 205863510 ps
T653 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.714622811 Oct 12 04:40:12 PM UTC 24 Oct 12 04:41:24 PM UTC 24 5886693397 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.1448334030 Oct 12 04:41:17 PM UTC 24 Oct 12 04:41:31 PM UTC 24 4066559606 ps
T654 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.628440985 Oct 12 04:41:32 PM UTC 24 Oct 12 04:41:34 PM UTC 24 231646044 ps
T655 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.1646801627 Oct 12 04:41:32 PM UTC 24 Oct 12 04:41:35 PM UTC 24 236546026 ps
T656 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.818027192 Oct 12 04:40:23 PM UTC 24 Oct 12 04:41:36 PM UTC 24 2945785796 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.3796560325 Oct 12 04:39:25 PM UTC 24 Oct 12 04:41:36 PM UTC 24 13960226699 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.1283358320 Oct 12 04:40:32 PM UTC 24 Oct 12 04:41:38 PM UTC 24 30630028595 ps
T657 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.3455554312 Oct 12 04:41:38 PM UTC 24 Oct 12 04:41:41 PM UTC 24 246690551 ps
T658 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.1088805244 Oct 12 04:41:41 PM UTC 24 Oct 12 04:41:43 PM UTC 24 172085360 ps
T659 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_invalid_sync.1923303549 Oct 12 04:41:05 PM UTC 24 Oct 12 04:41:45 PM UTC 24 3620316582 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.3684324086 Oct 12 04:41:43 PM UTC 24 Oct 12 04:41:45 PM UTC 24 204037095 ps
T660 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.4152949367 Oct 12 04:41:45 PM UTC 24 Oct 12 04:41:47 PM UTC 24 160357109 ps
T661 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.2752937152 Oct 12 04:41:47 PM UTC 24 Oct 12 04:41:50 PM UTC 24 184146784 ps
T554 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.1167882338 Oct 12 04:41:47 PM UTC 24 Oct 12 04:41:50 PM UTC 24 181718731 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.2145137758 Oct 12 04:41:49 PM UTC 24 Oct 12 04:41:52 PM UTC 24 153687832 ps
T662 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.1515873420 Oct 12 04:41:51 PM UTC 24 Oct 12 04:41:54 PM UTC 24 218847270 ps
T663 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.3563077126 Oct 12 04:41:51 PM UTC 24 Oct 12 04:41:54 PM UTC 24 250241079 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.2243434512 Oct 12 04:41:53 PM UTC 24 Oct 12 04:41:56 PM UTC 24 146016305 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.2646368598 Oct 12 04:41:56 PM UTC 24 Oct 12 04:41:58 PM UTC 24 36402378 ps
T609 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk.1366000103 Oct 12 04:36:29 PM UTC 24 Oct 12 04:42:00 PM UTC 24 118102001283 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.2125618152 Oct 12 04:41:58 PM UTC 24 Oct 12 04:42:00 PM UTC 24 179917134 ps
T664 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.1444938252 Oct 12 04:41:38 PM UTC 24 Oct 12 04:42:01 PM UTC 24 2319033627 ps
T665 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.2319876933 Oct 12 04:42:00 PM UTC 24 Oct 12 04:42:02 PM UTC 24 188246574 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.883989809 Oct 12 04:40:24 PM UTC 24 Oct 12 04:42:03 PM UTC 24 7228670498 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.2291547135 Oct 12 04:42:03 PM UTC 24 Oct 12 04:42:05 PM UTC 24 181924988 ps
T666 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.905829793 Oct 12 04:42:03 PM UTC 24 Oct 12 04:42:05 PM UTC 24 197374814 ps
T667 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_max_usb_traffic.351251844 Oct 12 04:41:36 PM UTC 24 Oct 12 04:42:08 PM UTC 24 2122787605 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.352607422 Oct 12 04:42:07 PM UTC 24 Oct 12 04:42:10 PM UTC 24 152788759 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.2693471252 Oct 12 04:42:10 PM UTC 24 Oct 12 04:42:13 PM UTC 24 343793958 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.2354108972 Oct 12 04:42:12 PM UTC 24 Oct 12 04:42:14 PM UTC 24 186794682 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.2654831504 Oct 12 04:42:14 PM UTC 24 Oct 12 04:42:17 PM UTC 24 409713653 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.2766277336 Oct 12 04:40:43 PM UTC 24 Oct 12 04:42:19 PM UTC 24 39538740687 ps
T668 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.2004003435 Oct 12 04:42:16 PM UTC 24 Oct 12 04:42:19 PM UTC 24 228615806 ps
T669 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.1410646110 Oct 12 04:42:18 PM UTC 24 Oct 12 04:42:21 PM UTC 24 182708623 ps
T670 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.56205535 Oct 12 04:42:21 PM UTC 24 Oct 12 04:42:23 PM UTC 24 223636613 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.1266319536 Oct 12 04:42:21 PM UTC 24 Oct 12 04:42:23 PM UTC 24 195597721 ps
T671 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.2872047037 Oct 12 04:42:25 PM UTC 24 Oct 12 04:42:28 PM UTC 24 168581943 ps
T562 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.385895315 Oct 12 04:42:25 PM UTC 24 Oct 12 04:42:28 PM UTC 24 169950727 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.3707580332 Oct 12 04:41:56 PM UTC 24 Oct 12 04:42:30 PM UTC 24 11609866193 ps
T672 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.2739494250 Oct 12 04:42:29 PM UTC 24 Oct 12 04:42:32 PM UTC 24 219928003 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_resume_link_active.1706277690 Oct 12 04:42:07 PM UTC 24 Oct 12 04:42:33 PM UTC 24 20208017289 ps
T673 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.457246088 Oct 12 04:42:34 PM UTC 24 Oct 12 04:42:38 PM UTC 24 622787660 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.4002710966 Oct 12 04:42:36 PM UTC 24 Oct 12 04:42:40 PM UTC 24 413737736 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.3517819466 Oct 12 04:42:38 PM UTC 24 Oct 12 04:42:40 PM UTC 24 43213854 ps
T610 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk.2640784253 Oct 12 04:39:15 PM UTC 24 Oct 12 04:42:44 PM UTC 24 119189910381 ps
T674 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_streaming_out.2920499527 Oct 12 04:42:29 PM UTC 24 Oct 12 04:42:49 PM UTC 24 2616448203 ps
T675 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.3446517754 Oct 12 04:42:48 PM UTC 24 Oct 12 04:42:50 PM UTC 24 157416162 ps
T676 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.3659271315 Oct 12 04:41:26 PM UTC 24 Oct 12 04:42:52 PM UTC 24 2926966867 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.4222996778 Oct 12 04:42:50 PM UTC 24 Oct 12 04:42:52 PM UTC 24 163522879 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.3314879491 Oct 12 04:42:52 PM UTC 24 Oct 12 04:42:54 PM UTC 24 149893482 ps
T677 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.1878987380 Oct 12 04:41:36 PM UTC 24 Oct 12 04:42:55 PM UTC 24 2438171720 ps
T678 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.406367819 Oct 12 04:42:54 PM UTC 24 Oct 12 04:42:57 PM UTC 24 174650549 ps
T679 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_spurious_pids_ignored.3426232884 Oct 12 04:42:23 PM UTC 24 Oct 12 04:42:57 PM UTC 24 2457776409 ps
T680 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.904916674 Oct 12 04:42:54 PM UTC 24 Oct 12 04:42:57 PM UTC 24 291824662 ps
T681 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_iso_retraction.3387102035 Oct 12 04:41:13 PM UTC 24 Oct 12 04:43:01 PM UTC 24 9451858003 ps
T596 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.100369391 Oct 12 04:42:56 PM UTC 24 Oct 12 04:43:01 PM UTC 24 823715744 ps
T682 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.219334807 Oct 12 04:42:59 PM UTC 24 Oct 12 04:43:02 PM UTC 24 152923391 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.3680777435 Oct 12 04:41:15 PM UTC 24 Oct 12 04:43:02 PM UTC 24 33567397897 ps
T504 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.385622141 Oct 12 04:42:59 PM UTC 24 Oct 12 04:43:03 PM UTC 24 450263270 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.4060151859 Oct 12 04:42:41 PM UTC 24 Oct 12 04:43:03 PM UTC 24 6864908197 ps
T683 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_enable.954862257 Oct 12 04:43:03 PM UTC 24 Oct 12 04:43:06 PM UTC 24 59176472 ps
T684 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.1309941393 Oct 12 04:43:04 PM UTC 24 Oct 12 04:43:06 PM UTC 24 244591155 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.3864220562 Oct 12 04:43:04 PM UTC 24 Oct 12 04:43:07 PM UTC 24 289493543 ps
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T686 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.2555937976 Oct 12 04:43:04 PM UTC 24 Oct 12 04:43:08 PM UTC 24 301410225 ps
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T688 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_rand_suspends.376099317 Oct 12 04:42:05 PM UTC 24 Oct 12 04:43:13 PM UTC 24 8960491757 ps
T689 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.878526895 Oct 12 04:43:11 PM UTC 24 Oct 12 04:43:14 PM UTC 24 194985087 ps
T690 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.3755180912 Oct 12 04:43:13 PM UTC 24 Oct 12 04:43:16 PM UTC 24 176016532 ps
T691 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.2768407044 Oct 12 04:43:15 PM UTC 24 Oct 12 04:43:18 PM UTC 24 230720269 ps
T692 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.2900809604 Oct 12 04:42:59 PM UTC 24 Oct 12 04:43:19 PM UTC 24 1985974837 ps
T693 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_resets.2533985076 Oct 12 04:42:05 PM UTC 24 Oct 12 04:43:20 PM UTC 24 10216903804 ps
T694 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.2300188073 Oct 12 04:43:17 PM UTC 24 Oct 12 04:43:20 PM UTC 24 158468655 ps
T695 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_disconnects.2499629482 Oct 12 04:42:03 PM UTC 24 Oct 12 04:43:23 PM UTC 24 2488693242 ps
T616 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk_max.3645746886 Oct 12 04:39:15 PM UTC 24 Oct 12 04:43:26 PM UTC 24 104172777269 ps
T696 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.1489096487 Oct 12 04:43:24 PM UTC 24 Oct 12 04:43:27 PM UTC 24 243598011 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.2178581194 Oct 12 04:41:17 PM UTC 24 Oct 12 04:43:31 PM UTC 24 3832143726 ps
T697 /workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.315298307 Oct 12 04:43:29 PM UTC 24 Oct 12 04:43:32 PM UTC 24 183938241 ps
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