Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112260

1

T2

1

T3

1

T17

1

auto[1]

46266

1

T18

2

T19

8

T26

12

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30323	1			T65	1		T112	2		T81	1
max_len_m1	853	1			T40	3		T48	1		T153	1
max_len_m2	881	1			T26	2		T40	2		T4	4
max_len_m3	817	1			T66	1		T6	4		T148	4
five	1189	1			T40	2		T4	1		T5	1
four	1102	1			T40	1		T4	2		T5	1
three	765	1			T31	1		T40	2		T65	1
one	846	1			T40	2		T5	2		T406	1
zero	11574	1			T17	1		T18	2		T19	3

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24318	1			T65	1		T112	1		T81	1
max_len	auto[1]	6005	1			T112	1		T5	2		T113	1
max_len_m1	auto[0]	596	1			T40	3		T48	1		T153	1
max_len_m1	auto[1]	257	1			T155	1		T151	1		T172	1
max_len_m2	auto[0]	605	1			T26	1		T40	2		T4	2
max_len_m2	auto[1]	276	1			T26	1		T4	2		T5	3
max_len_m3	auto[0]	555	1			T66	1		T6	2		T148	2
max_len_m3	auto[1]	262	1			T6	2		T148	2		T152	1
five	auto[0]	610	1			T40	2		T4	1		T5	1
five	auto[1]	579	1			T148	2		T62	1		T171	1
four	auto[0]	567	1			T40	1		T4	1		T5	1
four	auto[1]	535	1			T4	1		T589	1		T113	1
three	auto[0]	359	1			T31	1		T40	2		T65	1
three	auto[1]	406	1			T283	15		T87	4		T590	1
one	auto[0]	380	1			T40	2		T5	2		T406	1
one	auto[1]	466	1			T283	14		T87	7		T108	1
zero	auto[0]	540	1			T17	1		T31	1		T40	3
zero	auto[1]	11034	1			T18	2		T19	3		T29	18