Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139092

1

T2

2

T3

2

T18

4

auto[1]

77701

1

T18

4

T19

14

T26

24

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	18110	1			T19	6		T26	4		T4	36
endpoints[0x1]	17252	1			T26	4		T29	24		T31	21
endpoints[0x2]	17045	1			T19	3		T26	4		T410	1
endpoints[0x3]	16680	1			T19	5		T26	4		T5	28
endpoints[0x4]	14423	1			T2	2		T26	4		T30	23
endpoints[0x5]	19722	1			T19	4		T26	4		T27	2
endpoints[0x6]	19383	1			T18	8		T26	4		T32	2
endpoints[0x7]	17143	1			T19	4		T26	4		T8	4
endpoints[0x8]	21321	1			T3	2		T19	4		T26	4
endpoints[0x9]	22238	1			T26	4		T5	28		T43	6
endpoints[0xa]	15336	1			T26	4		T5	28		T219	1
endpoints[0xb]	18140	1			T19	4		T26	4		T4	36

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1324	1			T19	3		T31	2		T65	2
ack	104729	1			T2	1		T3	1		T18	4
data1	50742	1			T18	1		T19	9		T29	5
data0	59922	1			T2	1		T3	1		T18	3

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	140	1			T111	6		T591	1		T158	12
nak	auto[0]	endpoints[0x1]	106	1			T31	2		T65	2		T66	2
nak	auto[0]	endpoints[0x2]	93	1			T164	12		T427	12		T592	1
nak	auto[0]	endpoints[0x3]	66	1			T60	4		T67	1		T363	1
nak	auto[0]	endpoints[0x4]	76	1			T164	8		T311	1		T593	13
nak	auto[0]	endpoints[0x5]	116	1			T552	1		T128	1		T164	15
nak	auto[0]	endpoints[0x6]	79	1			T118	1		T427	10		T587	3
nak	auto[0]	endpoints[0x7]	101	1			T553	1		T164	6		T594	1
nak	auto[0]	endpoints[0x8]	85	1			T111	18		T158	14		T566	5
nak	auto[0]	endpoints[0x9]	66	1			T310	1		T139	1		T140	1
nak	auto[0]	endpoints[0xa]	153	1			T554	1		T158	17		T164	19
nak	auto[0]	endpoints[0xb]	74	1			T110	7		T145	1		T376	1
nak	auto[1]	endpoints[0x0]	18	1			T19	1		T108	2		T595	1
nak	auto[1]	endpoints[0x1]	18	1			T103	1		T108	2		T596	1
nak	auto[1]	endpoints[0x2]	13	1			T103	1		T596	1		T597	1
nak	auto[1]	endpoints[0x3]	12	1			T596	1		T598	1		T599	1
nak	auto[1]	endpoints[0x4]	18	1			T600	3		T601	1		T602	1
nak	auto[1]	endpoints[0x5]	12	1			T19	1		T108	1		T599	1
nak	auto[1]	endpoints[0x6]	15	1			T108	1		T595	1		T599	1
nak	auto[1]	endpoints[0x7]	9	1			T596	1		T600	1		T603	1
nak	auto[1]	endpoints[0x8]	13	1			T19	1		T596	1		T595	1
nak	auto[1]	endpoints[0x9]	17	1			T108	1		T596	1		T604	3
nak	auto[1]	endpoints[0xa]	13	1			T600	1		T601	2		T602	1
nak	auto[1]	endpoints[0xb]	11	1			T599	2		T605	1		T606	1
ack	auto[0]	endpoints[0x0]	5566	1			T19	1		T26	1		T4	9
ack	auto[0]	endpoints[0x1]	5456	1			T26	1		T31	8		T65	8
ack	auto[0]	endpoints[0x2]	4813	1			T19	1		T26	1		T62	7
ack	auto[0]	endpoints[0x3]	4770	1			T19	2		T26	1		T5	7
ack	auto[0]	endpoints[0x4]	3592	1			T2	1		T26	1		T5	7
ack	auto[0]	endpoints[0x5]	6428	1			T26	1		T27	1		T4	9
ack	auto[0]	endpoints[0x6]	6345	1			T18	2		T26	1		T32	1
ack	auto[0]	endpoints[0x7]	5220	1			T19	1		T26	1		T8	1
ack	auto[0]	endpoints[0x8]	7115	1			T3	1		T19	1		T26	1
ack	auto[0]	endpoints[0x9]	7499	1			T26	1		T5	7		T43	2
ack	auto[0]	endpoints[0xa]	4295	1			T26	1		T5	7		T101	1
ack	auto[0]	endpoints[0xb]	5344	1			T19	2		T26	1		T4	9
ack	auto[1]	endpoints[0x0]	3134	1			T19	1		T26	1		T4	9
ack	auto[1]	endpoints[0x1]	2827	1			T26	1		T29	6		T4	9
ack	auto[1]	endpoints[0x2]	3391	1			T26	1		T62	7		T149	1
ack	auto[1]	endpoints[0x3]	3334	1			T26	1		T5	7		T60	18
ack	auto[1]	endpoints[0x4]	3323	1			T26	1		T30	7		T5	7
ack	auto[1]	endpoints[0x5]	3101	1			T19	1		T26	1		T4	9
ack	auto[1]	endpoints[0x6]	3041	1			T18	2		T26	1		T33	1
ack	auto[1]	endpoints[0x7]	3034	1			T19	1		T26	1		T8	1
ack	auto[1]	endpoints[0x8]	3289	1			T26	1		T60	13		T148	7
ack	auto[1]	endpoints[0x9]	3360	1			T26	1		T5	7		T43	1
ack	auto[1]	endpoints[0xa]	3021	1			T26	1		T5	7		T150	1
ack	auto[1]	endpoints[0xb]	3431	1			T26	1		T4	9		T60	15
data1	auto[0]	endpoints[0x0]	2495	1			T4	4		T60	8		T148	1
data1	auto[0]	endpoints[0x1]	2438	1			T31	5		T65	5		T4	4
data1	auto[0]	endpoints[0x2]	2119	1			T19	1		T62	1		T283	17
data1	auto[0]	endpoints[0x3]	2099	1			T19	2		T5	3		T60	2
data1	auto[0]	endpoints[0x4]	1426	1			T5	2		T42	1		T148	2
data1	auto[0]	endpoints[0x5]	2930	1			T4	4		T5	2		T153	1
data1	auto[0]	endpoints[0x6]	2895	1			T18	1		T60	2		T154	1
data1	auto[0]	endpoints[0x7]	2334	1			T6	11		T148	3		T283	16
data1	auto[0]	endpoints[0x8]	3244	1			T148	3		T62	2		T152	3
data1	auto[0]	endpoints[0x9]	3452	1			T5	2		T43	1		T148	3
data1	auto[0]	endpoints[0xa]	1934	1			T5	3		T150	1		T283	20
data1	auto[0]	endpoints[0xb]	2321	1			T19	1		T4	4		T60	8
data1	auto[1]	endpoints[0x0]	1709	1			T4	4		T60	8		T148	5
data1	auto[1]	endpoints[0x1]	1581	1			T29	5		T4	4		T5	3
data1	auto[1]	endpoints[0x2]	1860	1			T19	1		T62	6		T283	19
data1	auto[1]	endpoints[0x3]	1846	1			T19	1		T5	3		T60	11
data1	auto[1]	endpoints[0x4]	1898	1			T30	5		T5	4		T42	1
data1	auto[1]	endpoints[0x5]	1682	1			T19	2		T4	4		T5	5
data1	auto[1]	endpoints[0x6]	1642	1			T154	1		T148	5		T62	3
data1	auto[1]	endpoints[0x7]	1671	1			T6	28		T148	3		T283	19
data1	auto[1]	endpoints[0x8]	1801	1			T19	1		T60	10		T148	3
data1	auto[1]	endpoints[0x9]	1820	1			T5	5		T43	1		T148	4
data1	auto[1]	endpoints[0xa]	1652	1			T5	3		T150	1		T103	1
data1	auto[1]	endpoints[0xb]	1893	1			T4	4		T60	10		T44	1
data0	auto[0]	endpoints[0x0]	3532	1			T19	1		T26	1		T4	5
data0	auto[0]	endpoints[0x1]	3470	1			T26	1		T31	6		T65	6
data0	auto[0]	endpoints[0x2]	3133	1			T26	1		T410	1		T62	6
data0	auto[0]	endpoints[0x3]	2978	1			T26	1		T5	4		T60	17
data0	auto[0]	endpoints[0x4]	2561	1			T2	1		T26	1		T5	5
data0	auto[0]	endpoints[0x5]	3970	1			T26	1		T27	1		T4	5
data0	auto[0]	endpoints[0x6]	3891	1			T18	1		T26	1		T32	1
data0	auto[0]	endpoints[0x7]	3311	1			T19	1		T26	1		T8	1
data0	auto[0]	endpoints[0x8]	4240	1			T3	1		T19	1		T26	1
data0	auto[0]	endpoints[0x9]	4400	1			T26	1		T5	5		T43	1
data0	auto[0]	endpoints[0xa]	2835	1			T26	1		T5	4		T219	1
data0	auto[0]	endpoints[0xb]	3460	1			T19	1		T26	1		T4	5
data0	auto[1]	endpoints[0x0]	1505	1			T19	2		T26	1		T4	5
data0	auto[1]	endpoints[0x1]	1347	1			T26	1		T29	13		T4	5
data0	auto[1]	endpoints[0x2]	1612	1			T26	1		T62	1		T103	1
data0	auto[1]	endpoints[0x3]	1569	1			T26	1		T5	4		T60	7
data0	auto[1]	endpoints[0x4]	1522	1			T26	1		T30	11		T5	3
data0	auto[1]	endpoints[0x5]	1477	1			T26	1		T4	5		T112	1
data0	auto[1]	endpoints[0x6]	1468	1			T18	2		T26	1		T33	1
data0	auto[1]	endpoints[0x7]	1463	1			T19	1		T26	1		T8	1
data0	auto[1]	endpoints[0x8]	1529	1			T26	1		T60	3		T148	4
data0	auto[1]	endpoints[0x9]	1619	1			T26	1		T5	2		T148	3
data0	auto[1]	endpoints[0xa]	1429	1			T26	1		T5	4		T205	1
data0	auto[1]	endpoints[0xb]	1601	1			T26	1		T4	5		T60	5