Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7892 1 T21 5 T80 3 T5 3
auto[1] 54766 1 T18 2 T19 8 T21 4


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54293 1 T18 2 T19 8 T21 9
auto[1] 8365 1 T80 1 T32 1 T5 17


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56672 1 T18 2 T19 8 T21 5
auto[1] 5986 1 T21 4 T80 1 T100 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4493 1 T21 3 T80 2 T5 4
pkt_types[PidTypeInToken] 58165 1 T18 2 T19 8 T21 6


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1398 1 T21 2 T80 1 T5 2
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 692 1 T60 7 T110 18 T158 23
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 85 1 T5 1 T172 2 T224 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 9 1 T80 1 T464 1 T440 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1386 1 T5 1 T60 33 T409 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 805 1 T21 1 T60 20 T110 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 105 1 T172 5 T411 1 T412 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 13 1 T484 1 T465 1 T607 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3727 1 T21 3 T80 1 T60 71
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 1888 1 T60 31 T409 3 T110 70
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 42 1 T453 1 T503 2 T431 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 51 1 T488 1 T451 2 T608 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41927 1 T18 2 T19 8 T26 12
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2470 1 T21 3 T100 1 T60 84
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 8002 1 T32 1 T5 16 T109 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 58 1 T488 2 T536 1 T451 1

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