Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.52	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	192	1	191	99.48

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_out_enable	2	0	2	100.00	100	1	1	2
cp_out_iso	2	0	2	100.00	100	1	1	2
cp_out_stall	2	0	2	100.00	100	1	1	2
cp_pid	3	0	3	100.00	100	1	1	0
cp_rxenable_out	2	0	2	100.00	100	1	1	2
cp_rxenable_setup	2	0	2	100.00	100	1	1	2
cp_set_nak_out	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	192	1	191	99.48	100	1	1	0

Summary for Variable cp_out_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15971

1

T21

9

T40

139

T5

3

auto[1]

83375

1

T2

1

T3

1

T17

1

---

Summary for Variable cp_out_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96936

1

T2

1

T3

1

T17

1

auto[1]

2410

1

T80

2

T5

2

T82

1

---

Summary for Variable cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87531

1

T2

1

T3

1

T17

1

auto[1]

11815

1

T21

3

T60

349

T219

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	8967	1			T5	12		T60	216		T409	4
pkt_types[PidTypeSetupToken]	20175	1			T21	5		T27	1		T28	8
pkt_types[PidTypeOutToken]	70136	1			T2	1		T3	1		T17	1

---

Summary for Variable cp_rxenable_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17685

1

T80

2

T40

139

T5

3

auto[1]

81661

1

T2

1

T3

1

T17

1

---

Summary for Variable cp_rxenable_setup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_setup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67673

1

T2

1

T3

1

T17

1

auto[1]

31673

1

T21

8

T80

1

T27

1

---

Summary for Variable cp_set_nak_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_set_nak_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98690

1

T2

1

T3

1

T17

1

auto[1]

656

1

T80

1

T67

2

T410

1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	192	1	191	99.48	1

Automatically Generated Cross Bins for cr_pid_x_epconfig

Uncovered bins

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER	STATUS
[pkt_types[PidTypeOutToken]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_out_enable

cp_rxenable_setup

cp_rxenable_out

cp_set_nak_out

cp_out_iso

cp_out_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

643

1

T172

3

T224

4

T411

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

432

1

T60

31

T409

1

T111

11

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

83

1

T5

1

T411

2

T412

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T413

1

T414

1

T415

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

4

1

T416

1

T417

1

T418

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T419

1

T420

1

T421

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T422

1

T423

1

T424

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T422

1

T425

1

T426

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

444

1

T427

16

T428

2

T429

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

330

1

T110

11

T430

1

T111

23

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T431

1

T432

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T433

1

T434

2

T435

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T436

1

T437

1

T418

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T438

2

T437

1

T439

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T440

2

T424

1

T441

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T442

2

-

-

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

620

1

T5

1

T60

34

T224

3

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

512

1

T60

35

T409

2

T110

13

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

74

1

T5

1

T172

1

T411

4

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T443

1

T418

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

8

1

T444

1

T445

1

T436

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T446

1

-

-

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T433

1

T442

1

T447

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T420

1

T448

1

T449

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

483

1

T111

18

T158

36

T450

3

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

447

1

T409

1

T430

1

T158

16

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T416

2

-

-

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T451

1

T452

1

T424

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T453

1

T416

1

T454

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T455

1

T422

1

T456

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T445

1

T457

1

T458

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T459

2

T460

1

T461

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

546

1

T111

19

T158

17

T164

14

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

506

1

T60

23

T111

9

T158

17

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

8

1

T462

2

T442

1

T463

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T464

1

T465

1

T420

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

7

1

T466

1

T467

1

T468

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T469

1

T470

1

T471

2

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T472

1

T473

1

T474

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T475

1

-

-

-

-

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

731

1

T5

3

T60

20

T110

12

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

445

1

T110

26

T158

36

T476

33

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

73

1

T172

2

T224

3

T411

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T477

1

T478

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T479

1

T480

1

T481

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T433

1

T482

1

T483

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T442

1

T464

1

T438

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T109

1

T484

1

T485

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

920

1

T60

19

T110

29

T111

20

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T110

1

T164

1

T486

2

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

2

1

T416

1

T487

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T484

1

T488

1

T489

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

2

1

T490

2

-

-

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T488

1

T459

1

T491

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T492

1

-

-

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T493

1

T494

1

T495

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1351

1

T5

6

T60

53

T110

61

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T60

1

T110

4

T111

2

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

88

1

T172

5

T224

1

T411

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T496

1

T497

1

T439

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T419

1

T498

1

T499

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T438

1

T500

1

T441

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T473

1

T501

2

T502

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T503

2

T431

1

T464

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

796

1

T72

1

T504

1

T444

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

599

1

T60

40

T409

1

T430

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1

1

T505

1

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T419

2

T414

1

T459

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

11

1

T484

1

T469

1

T416

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T420

1

T421

1

T491

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T465

1

T419

1

T424

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T472

1

T422

1

T506

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

642

1

T430

1

T507

1

T503

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

501

1

T409

1

T110

20

T111

23

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

9

1

T453

1

T431

1

T508

3

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T422

1

T416

1

T420

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T446

1

T509

1

T510

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T484

2

T414

1

T469

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T508

1

T511

1

T512

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T442

1

T513

1

T514

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

831

1

T60

50

T72

1

T75

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

846

1

T60

56

T409

2

T110

21

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

3

1

T515

1

T516

1

T517

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T109

1

T416

1

T443

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

5

1

T444

1

T446

1

T518

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T519

1

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T433

1

T520

1

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T521

1

T448

1

T522

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

651

1

T21

3

T111

28

T504

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

731

1

T21

2

T409

2

T430

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T501

2

T523

1

T524

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T433

1

T456

1

T511

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T453

1

T445

1

T413

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T462

2

T473

1

T413

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T445

1

T525

2

T526

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T440

1

T418

1

-

-

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

851

1

T223

1

T404

1

T111

23

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

838

1

T60

40

T453

1

T111

22

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

5

1

T527

1

T470

1

T463

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T453

3

T445

1

T515

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

6

1

T473

1

T413

1

T455

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T488

1

T482

1

T516

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T433

1

T438

1

T528

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T479

1

T443

1

T481

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

967

1

T60

24

T72

2

T110

12

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

671

1

T110

35

T158

59

T476

62

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

7

1

T438

1

T501

1

T466

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T529

1

T530

2

T478

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T419

1

T467

1

T497

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T436

1

T467

1

T531

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T532

1

T443

1

T449

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T533

1

T534

1

T454

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1704

1

T60

31

T83

1

T47

8

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

37

1

T110

2

T164

1

T165

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

2

1

T506

1

T535

1

-

-

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T484

1

T488

1

T489

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

4

1

T431

1

T523

1

T475

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T489

1

T467

2

T534

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T536

1

T537

1

T538

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T462

1

T452

1

T470

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

8870

1

T27

1

T28

8

T5

11

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

46

1

T60

2

T101

1

T110

4

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

337

1

T155

5

T172

11

T224

4

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T489

1

T539

2

T540

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T527

1

T501

1

T541

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T419

1

T542

1

T452

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T500

1

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T485

2

T421

2

T470

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1016

1

T40

139

T72

2

T78

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

650

1

T60

53

T409

2

T111

17

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

5

1

T431

1

T532

1

T505

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T452

1

T414

1

T526

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

5

1

T433

1

T500

1

T537

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T501

1

T421

1

T543

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

10

1

T503

1

T465

1

T544

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T506

1

-

-

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

602

1

T21

1

T430

1

T504

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

517

1

T409

2

T110

30

T111

33

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T431

1

T536

1

T436

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T488

1

T465

1

T533

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

6

1

T545

1

T546

1

T466

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T433

1

T484

1

T515

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T508

1

T452

1

T414

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T515

1

T528

1

T443

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

887

1

T60

47

T72

6

T75

7

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

868

1

T60

48

T409

3

T110

22

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

3

1

T515

1

T543

1

T547

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T414

1

T526

2

T496

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

4

1

T503

1

T528

1

T492

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T422

1

T548

1

T440

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T442

1

T488

1

T534

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T420

1

T426

1

T549

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

676

1

T21

2

T111

25

T504

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

715

1

T21

1

T409

2

T430

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T506

1

T540

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T500

1

T550

1

T551

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T472

1

T462

1

T413

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T442

1

T526

1

T510

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T506

1

T418

1

T460

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

807

1

T552

1

T553

1

T554

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

829

1

T60

17

T111

27

T158

28

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

3

1

T80

1

T425

1

T555

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T556

3

T524

2

T557

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T67

1

T118

1

T453

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T542

1

T469

2

T466

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T433

1

T534

2

T491

2

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T433

1

T472

1

T558

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50857

1

T2

1

T3

1

T17

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

745

1

T219

1

T559

1

T560

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

974

1

T82

1

T155

17

T215

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T431

1

T525

1

T498

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T67

1

T118

1

T119

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

52

1

T410

1

T561

1

T562

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T563

1

T564

1

T441

2

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T416

1

T534

1

T565

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1303

1

T60

15

T110

33

T453

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T110

2

T472

1

T566

2

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T464

1

T567

1

T568

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T484

1

T506

1

T457

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

9

1

T536

1

T451

1

T490

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T532

1

T508

1

T489

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T80

1

T471

1

T415

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T558

1

T569

2

-

-

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

7872

1

T5

10

T60

82

T42

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

55

1

T60

3

T101

1

T110

11

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

326

1

T155

3

T172

10

T224

8

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T473

1

T539

1

T425

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T527

1

T419

1

T498

2

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T461

1

-

-

-

-

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T468

1

T540

1

T500

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T503

1

T445

1

T498

1