Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	172057	1			T1	3		T2	4		T3	6
all_pins[1]	172057	1			T1	3		T2	4		T3	6
all_pins[2]	172057	1			T1	3		T2	4		T3	6
all_pins[3]	172057	1			T1	3		T2	4		T3	6
all_pins[4]	172057	1			T1	3		T2	4		T3	6
all_pins[5]	172057	1			T1	3		T2	4		T3	6
all_pins[6]	172057	1			T1	3		T2	4		T3	6
all_pins[7]	172057	1			T1	3		T2	4		T3	6
all_pins[8]	172057	1			T1	3		T2	4		T3	6
all_pins[9]	172057	1			T1	3		T2	4		T3	6
all_pins[10]	172057	1			T1	3		T2	4		T3	6
all_pins[11]	172057	1			T1	3		T2	4		T3	6
all_pins[12]	172057	1			T1	3		T2	4		T3	6
all_pins[13]	172057	1			T1	3		T2	4		T3	6
all_pins[14]	172057	1			T1	3		T2	4		T3	6
all_pins[15]	172057	1			T1	3		T2	4		T3	6
all_pins[16]	172057	1			T1	3		T2	4		T3	6
all_pins[17]	172057	1			T1	3		T2	4		T3	6

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5503566	1			T1	96		T2	128		T3	191
values[0x1]	2258	1			T3	1		T16	2		T17	1
transitions[0x0=>0x1]	1982	1			T3	1		T16	2		T17	1
transitions[0x1=>0x0]	1982	1			T3	1		T16	2		T17	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	171954	1			T1	3		T2	4		T3	6
all_pins[0]	values[0x1]	103	1			T406	1		T407	1		T408	1
all_pins[0]	transitions[0x0=>0x1]	93	1			T406	1		T407	1		T408	1
all_pins[0]	transitions[0x1=>0x0]	858	1			T26	12		T8	1		T33	1
all_pins[1]	values[0x0]	171189	1			T1	3		T2	4		T3	6
all_pins[1]	values[0x1]	868	1			T26	12		T8	1		T33	1
all_pins[1]	transitions[0x0=>0x1]	856	1			T26	12		T8	1		T33	1
all_pins[1]	transitions[0x1=>0x0]	115	1			T20	1		T58	1		T59	1
all_pins[2]	values[0x0]	171930	1			T1	3		T2	4		T3	6
all_pins[2]	values[0x1]	127	1			T20	1		T58	1		T59	1
all_pins[2]	transitions[0x0=>0x1]	107	1			T20	1		T58	1		T59	1
all_pins[2]	transitions[0x1=>0x0]	57	1			T40	1		T200	2		T197	2
all_pins[3]	values[0x0]	171980	1			T1	3		T2	4		T3	6
all_pins[3]	values[0x1]	77	1			T40	1		T200	2		T197	2
all_pins[3]	transitions[0x0=>0x1]	62	1			T40	1		T200	2		T197	2
all_pins[3]	transitions[0x1=>0x0]	46	1			T41	1		T201	3		T198	1
all_pins[4]	values[0x0]	171996	1			T1	3		T2	4		T3	6
all_pins[4]	values[0x1]	61	1			T41	1		T201	3		T198	1
all_pins[4]	transitions[0x0=>0x1]	41	1			T41	1		T198	1		T299	1
all_pins[4]	transitions[0x1=>0x0]	41	1			T197	2		T297	2		T304	2
all_pins[5]	values[0x0]	171996	1			T1	3		T2	4		T3	6
all_pins[5]	values[0x1]	61	1			T201	3		T197	2		T297	2
all_pins[5]	transitions[0x0=>0x1]	49	1			T201	3		T197	2		T297	2
all_pins[5]	transitions[0x1=>0x0]	102	1			T61	1		T63	1		T64	1
all_pins[6]	values[0x0]	171943	1			T1	3		T2	4		T3	6
all_pins[6]	values[0x1]	114	1			T61	1		T63	1		T64	1
all_pins[6]	transitions[0x0=>0x1]	96	1			T61	1		T63	1		T64	1
all_pins[6]	transitions[0x1=>0x0]	54	1			T3	1		T45	1		T46	1
all_pins[7]	values[0x0]	171985	1			T1	3		T2	4		T3	5
all_pins[7]	values[0x1]	72	1			T3	1		T45	1		T46	1
all_pins[7]	transitions[0x0=>0x1]	55	1			T3	1		T45	1		T46	1
all_pins[7]	transitions[0x1=>0x0]	59	1			T47	1		T52	1		T53	1
all_pins[8]	values[0x0]	171981	1			T1	3		T2	4		T3	6
all_pins[8]	values[0x1]	76	1			T47	1		T52	1		T53	1
all_pins[8]	transitions[0x0=>0x1]	64	1			T47	1		T52	1		T53	1
all_pins[8]	transitions[0x1=>0x0]	61	1			T16	2		T56	2		T57	2
all_pins[9]	values[0x0]	171984	1			T1	3		T2	4		T3	6
all_pins[9]	values[0x1]	73	1			T16	2		T56	2		T57	2
all_pins[9]	transitions[0x0=>0x1]	46	1			T16	2		T56	2		T57	2
all_pins[9]	transitions[0x1=>0x0]	40	1			T200	1		T197	3		T300	1
all_pins[10]	values[0x0]	171990	1			T1	3		T2	4		T3	6
all_pins[10]	values[0x1]	67	1			T200	1		T197	3		T198	1
all_pins[10]	transitions[0x0=>0x1]	49	1			T200	1		T197	3		T198	1
all_pins[10]	transitions[0x1=>0x0]	116	1			T68	1		T69	1		T70	1
all_pins[11]	values[0x0]	171923	1			T1	3		T2	4		T3	6
all_pins[11]	values[0x1]	134	1			T68	1		T69	1		T70	1
all_pins[11]	transitions[0x0=>0x1]	112	1			T68	1		T69	1		T70	1
all_pins[11]	transitions[0x1=>0x0]	40	1			T71	1		T73	1		T74	1
all_pins[12]	values[0x0]	171995	1			T1	3		T2	4		T3	6
all_pins[12]	values[0x1]	62	1			T71	1		T73	1		T74	1
all_pins[12]	transitions[0x0=>0x1]	49	1			T71	1		T73	1		T74	1
all_pins[12]	transitions[0x1=>0x0]	102	1			T17	1		T77	1		T78	1
all_pins[13]	values[0x0]	171942	1			T1	3		T2	4		T3	6
all_pins[13]	values[0x1]	115	1			T17	1		T77	1		T78	1
all_pins[13]	transitions[0x0=>0x1]	99	1			T17	1		T77	1		T78	1
all_pins[13]	transitions[0x1=>0x0]	45	1			T197	1		T299	1		T304	1
all_pins[14]	values[0x0]	171996	1			T1	3		T2	4		T3	6
all_pins[14]	values[0x1]	61	1			T200	2		T197	2		T299	1
all_pins[14]	transitions[0x0=>0x1]	39	1			T200	2		T197	1		T305	1
all_pins[14]	transitions[0x1=>0x0]	42	1			T196	2		T197	2		T198	1
all_pins[15]	values[0x0]	171993	1			T1	3		T2	4		T3	6
all_pins[15]	values[0x1]	64	1			T196	2		T197	3		T198	1
all_pins[15]	transitions[0x0=>0x1]	55	1			T196	2		T198	1		T299	1
all_pins[15]	transitions[0x1=>0x0]	60	1			T31	4		T65	4		T66	4
all_pins[16]	values[0x0]	171988	1			T1	3		T2	4		T3	6
all_pins[16]	values[0x1]	69	1			T31	4		T65	4		T66	4
all_pins[16]	transitions[0x0=>0x1]	56	1			T31	4		T65	4		T66	4
all_pins[16]	transitions[0x1=>0x0]	41	1			T54	1		T55	1		T201	1
all_pins[17]	values[0x0]	172003	1			T1	3		T2	4		T3	6
all_pins[17]	values[0x1]	54	1			T54	1		T55	1		T201	2
all_pins[17]	transitions[0x0=>0x1]	54	1			T54	1		T55	1		T201	2