Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4574	1			T80	2		T4	9		T60	133
invalid_ep[0xd]	4622	1			T4	7		T60	100		T109	1
invalid_ep[0xe]	4483	1			T4	7		T60	99		T109	1
invalid_ep[0xf]	4727	1			T80	1		T4	11		T60	99
endpoints[0x0]	13117	1			T17	1		T19	3		T21	3
endpoints[0x1]	12993	1			T26	2		T80	1		T29	18
endpoints[0x2]	12993	1			T19	2		T21	4		T26	2
endpoints[0x3]	12558	1			T19	3		T21	2		T26	2
endpoints[0x4]	12426	1			T2	1		T26	2		T80	2
endpoints[0x5]	14333	1			T19	2		T26	2		T80	1
endpoints[0x6]	14015	1			T18	4		T26	2		T32	2
endpoints[0x7]	13269	1			T19	2		T26	2		T8	2
endpoints[0x8]	15156	1			T3	1		T19	2		T26	2
endpoints[0x9]	15212	1			T21	9		T26	2		T80	1
endpoints[0xa]	12490	1			T26	2		T80	1		T40	139
endpoints[0xb]	13442	1			T19	2		T26	2		T4	19

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24264	1			T21	5		T80	1		T27	1
pkt_types[PidTypeOutToken]	76340	1			T2	1		T3	1		T17	1
pkt_types[PidTypeInToken]	62180	1			T18	2		T19	8		T21	6

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1023	1			T80	1		T60	34		T110	20
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1050	1			T60	18		T110	21		T111	22
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1004	1			T60	25		T110	26		T111	18
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1012	1			T60	29		T110	29		T111	23
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1672	1			T21	2		T60	30		T148	4
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1733	1			T60	30		T83	1		T62	5
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1709	1			T60	23		T62	5		T409	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1667	1			T60	31		T148	2		T152	3
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1853	1			T5	4		T60	27		T42	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1605	1			T27	1		T5	4		T60	16
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1620	1			T60	24		T154	1		T148	3
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1623	1			T60	27		T6	22		T223	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1720	1			T28	8		T60	40		T62	5
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1589	1			T21	3		T5	3		T60	29
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1584	1			T60	24		T101	1		T150	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1800	1			T60	19		T44	1		T148	3
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1514	1			T4	9		T60	30		T72	3
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1526	1			T4	7		T60	27		T109	1
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1534	1			T4	7		T60	26		T109	1
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1630	1			T80	1		T4	11		T60	26
pkt_types[PidTypeOutToken]	endpoints[0x0]	5813	1			T17	1		T19	1		T21	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	5711	1			T26	1		T80	1		T31	11
pkt_types[PidTypeOutToken]	endpoints[0x2]	5139	1			T19	1		T21	1		T26	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5031	1			T19	2		T26	1		T5	7
pkt_types[PidTypeOutToken]	endpoints[0x4]	3741	1			T2	1		T26	1		T5	3
pkt_types[PidTypeOutToken]	endpoints[0x5]	6845	1			T26	1		T80	1		T4	9
pkt_types[PidTypeOutToken]	endpoints[0x6]	6731	1			T18	2		T26	1		T32	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	5544	1			T19	1		T26	1		T8	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	7420	1			T3	1		T19	1		T26	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	7745	1			T21	2		T26	1		T5	4
pkt_types[PidTypeOutToken]	endpoints[0xa]	4883	1			T26	1		T40	139		T5	7
pkt_types[PidTypeOutToken]	endpoints[0xb]	5533	1			T19	2		T26	1		T4	9
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1028	1			T80	1		T60	38		T110	13
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1001	1			T60	31		T110	21		T111	21
pkt_types[PidTypeInToken]	invalid_ep[0xe]	971	1			T60	30		T110	25		T111	30
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1015	1			T60	21		T110	17		T111	28
pkt_types[PidTypeInToken]	endpoints[0x0]	4486	1			T19	2		T26	1		T4	10
pkt_types[PidTypeInToken]	endpoints[0x1]	4415	1			T26	1		T29	18		T4	10
pkt_types[PidTypeInToken]	endpoints[0x2]	4934	1			T19	1		T21	2		T26	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4750	1			T19	1		T21	1		T26	1
pkt_types[PidTypeInToken]	endpoints[0x4]	5716	1			T26	1		T80	1		T30	16
pkt_types[PidTypeInToken]	endpoints[0x5]	4752	1			T19	2		T26	1		T4	10
pkt_types[PidTypeInToken]	endpoints[0x6]	4529	1			T18	2		T26	1		T32	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4987	1			T19	1		T26	1		T8	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4838	1			T19	1		T26	1		T60	28
pkt_types[PidTypeInToken]	endpoints[0x9]	4833	1			T21	3		T26	1		T80	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4943	1			T26	1		T5	8		T60	31
pkt_types[PidTypeInToken]	endpoints[0xb]	4982	1			T26	1		T4	10		T60	27