Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T201	4		T200	4		T196	4
all_values[1]	272	1			T201	4		T200	4		T196	4
all_values[2]	272	1			T201	4		T200	4		T196	4
all_values[3]	272	1			T201	4		T200	4		T196	4
all_values[4]	272	1			T201	4		T200	4		T196	4
all_values[5]	272	1			T201	4		T200	4		T196	4
all_values[6]	272	1			T201	4		T200	4		T196	4
all_values[7]	272	1			T201	4		T200	4		T196	4
all_values[8]	272	1			T201	4		T200	4		T196	4
all_values[9]	272	1			T201	4		T200	4		T196	4
all_values[10]	272	1			T201	4		T200	4		T196	4
all_values[11]	272	1			T201	4		T200	4		T196	4
all_values[12]	272	1			T201	4		T200	4		T196	4
all_values[13]	272	1			T201	4		T200	4		T196	4
all_values[14]	272	1			T201	4		T200	4		T196	4
all_values[15]	272	1			T201	4		T200	4		T196	4
all_values[16]	272	1			T201	4		T200	4		T196	4
all_values[17]	272	1			T201	4		T200	4		T196	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6489

1

T201

103

T200

98

T196

88

auto[1]

2215

1

T201

25

T200

30

T196

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6025

1

T201

88

T200

93

T196

98

auto[1]

2679

1

T201

40

T200

35

T196

30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5193

1

T201

74

T200

85

T196

78

auto[1]

3511

1

T201

54

T200

43

T196

50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	92	1			T201	3		T200	1		T196	2
all_values[0]	auto[0]	auto[1]	auto[0]	73	1			T196	2		T197	1		T198	1
all_values[0]	auto[1]	auto[0]	auto[1]	53	1			T200	2		T197	2		T297	1
all_values[0]	auto[1]	auto[1]	auto[1]	54	1			T201	1		T200	1		T198	2
all_values[1]	auto[0]	auto[0]	auto[0]	99	1			T200	2		T196	2		T197	2
all_values[1]	auto[0]	auto[1]	auto[0]	71	1			T201	2		T196	2		T297	2
all_values[1]	auto[1]	auto[0]	auto[1]	66	1			T201	1		T200	2		T197	2
all_values[1]	auto[1]	auto[1]	auto[1]	36	1			T201	1		T297	1		T298	1
all_values[2]	auto[0]	auto[0]	auto[0]	49	1			T198	1		T299	1		T298	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T201	2		T200	2		T197	3
all_values[2]	auto[0]	auto[1]	auto[0]	37	1			T201	1		T196	2		T198	1
all_values[2]	auto[0]	auto[1]	auto[1]	33	1			T200	1		T196	1		T297	1
all_values[2]	auto[1]	auto[0]	auto[1]	50	1			T201	1		T197	1		T297	1
all_values[2]	auto[1]	auto[1]	auto[1]	53	1			T200	1		T196	1		T297	1
all_values[3]	auto[0]	auto[0]	auto[0]	51	1			T197	1		T198	1		T299	1
all_values[3]	auto[0]	auto[0]	auto[1]	28	1			T201	1		T200	1		T198	1
all_values[3]	auto[0]	auto[1]	auto[0]	50	1			T196	2		T197	1		T198	1
all_values[3]	auto[0]	auto[1]	auto[1]	32	1			T197	1		T297	1		T299	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1			T201	3		T200	2		T196	1
all_values[3]	auto[1]	auto[1]	auto[1]	48	1			T200	1		T196	1		T197	1
all_values[4]	auto[0]	auto[0]	auto[0]	66	1			T201	1		T197	1		T297	1
all_values[4]	auto[0]	auto[0]	auto[1]	36	1			T196	2		T197	1		T198	1
all_values[4]	auto[0]	auto[1]	auto[0]	39	1			T200	2		T297	3		T299	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1			T201	1		T299	4		T300	2
all_values[4]	auto[1]	auto[0]	auto[1]	58	1			T200	1		T196	2		T197	2
all_values[4]	auto[1]	auto[1]	auto[1]	43	1			T201	2		T200	1		T198	2
all_values[5]	auto[0]	auto[0]	auto[0]	69	1			T201	1		T200	1		T196	4
all_values[5]	auto[0]	auto[0]	auto[1]	18	1			T301	1		T302	2		T303	1
all_values[5]	auto[0]	auto[1]	auto[0]	49	1			T200	2		T198	1		T299	2
all_values[5]	auto[0]	auto[1]	auto[1]	26	1			T201	1		T197	1		T297	1
all_values[5]	auto[1]	auto[0]	auto[1]	58	1			T200	1		T197	1		T297	3
all_values[5]	auto[1]	auto[1]	auto[1]	52	1			T201	2		T198	1		T299	4
all_values[6]	auto[0]	auto[0]	auto[0]	65	1			T201	1		T200	3		T196	3
all_values[6]	auto[0]	auto[0]	auto[1]	33	1			T201	1		T197	1		T299	1
all_values[6]	auto[0]	auto[1]	auto[0]	37	1			T200	1		T196	1		T198	1
all_values[6]	auto[0]	auto[1]	auto[1]	25	1			T197	1		T198	1		T299	2
all_values[6]	auto[1]	auto[0]	auto[1]	58	1			T201	2		T197	1		T297	2
all_values[6]	auto[1]	auto[1]	auto[1]	54	1			T197	1		T198	1		T299	1
all_values[7]	auto[0]	auto[0]	auto[0]	76	1			T201	2		T196	1		T197	2
all_values[7]	auto[0]	auto[1]	auto[0]	80	1			T200	2		T196	2		T197	1
all_values[7]	auto[1]	auto[0]	auto[1]	65	1			T201	2		T200	1		T196	1
all_values[7]	auto[1]	auto[1]	auto[1]	51	1			T200	1		T198	1		T298	1
all_values[8]	auto[0]	auto[0]	auto[0]	95	1			T201	2		T200	2		T196	2
all_values[8]	auto[0]	auto[1]	auto[0]	73	1			T200	1		T196	1		T197	1
all_values[8]	auto[1]	auto[0]	auto[1]	55	1			T201	1		T198	1		T299	1
all_values[8]	auto[1]	auto[1]	auto[1]	49	1			T201	1		T200	1		T196	1
all_values[9]	auto[0]	auto[0]	auto[0]	64	1			T201	1		T200	2		T196	2
all_values[9]	auto[0]	auto[0]	auto[1]	36	1			T201	2		T198	1		T297	1
all_values[9]	auto[0]	auto[1]	auto[0]	40	1			T197	1		T299	1		T300	2
all_values[9]	auto[0]	auto[1]	auto[1]	29	1			T299	1		T298	1		T304	1
all_values[9]	auto[1]	auto[0]	auto[1]	63	1			T201	1		T200	2		T196	1
all_values[9]	auto[1]	auto[1]	auto[1]	40	1			T196	1		T198	2		T297	1
all_values[10]	auto[0]	auto[0]	auto[0]	67	1			T201	2		T297	1		T299	5
all_values[10]	auto[0]	auto[0]	auto[1]	15	1			T198	1		T297	1		T304	1
all_values[10]	auto[0]	auto[1]	auto[0]	48	1			T200	2		T196	2		T297	1
all_values[10]	auto[0]	auto[1]	auto[1]	30	1			T200	1		T197	2		T198	1
all_values[10]	auto[1]	auto[0]	auto[1]	61	1			T201	2		T200	1		T196	1
all_values[10]	auto[1]	auto[1]	auto[1]	51	1			T196	1		T197	1		T198	1
all_values[11]	auto[0]	auto[0]	auto[0]	66	1			T201	1		T200	1		T197	3
all_values[11]	auto[0]	auto[0]	auto[1]	21	1			T200	2		T300	1		T305	2
all_values[11]	auto[0]	auto[1]	auto[0]	38	1			T201	2		T197	1		T297	1
all_values[11]	auto[0]	auto[1]	auto[1]	35	1			T196	1		T198	1		T297	1
all_values[11]	auto[1]	auto[0]	auto[1]	52	1			T201	1		T196	1		T299	2
all_values[11]	auto[1]	auto[1]	auto[1]	60	1			T200	1		T196	2		T198	2
all_values[12]	auto[0]	auto[0]	auto[0]	58	1			T201	2		T200	2		T297	1
all_values[12]	auto[0]	auto[0]	auto[1]	26	1			T196	1		T198	1		T299	2
all_values[12]	auto[0]	auto[1]	auto[0]	59	1			T201	2		T200	2		T198	1
all_values[12]	auto[0]	auto[1]	auto[1]	27	1			T197	2		T304	1		T300	1
all_values[12]	auto[1]	auto[0]	auto[1]	59	1			T196	3		T197	1		T198	1
all_values[12]	auto[1]	auto[1]	auto[1]	43	1			T197	1		T198	1		T297	1
all_values[13]	auto[0]	auto[0]	auto[0]	60	1			T200	2		T197	1		T297	1
all_values[13]	auto[0]	auto[0]	auto[1]	22	1			T201	1		T300	1		T306	1
all_values[13]	auto[0]	auto[1]	auto[0]	47	1			T201	1		T196	1		T198	2
all_values[13]	auto[0]	auto[1]	auto[1]	27	1			T200	1		T196	1		T197	2
all_values[13]	auto[1]	auto[0]	auto[1]	67	1			T201	2		T198	1		T297	1
all_values[13]	auto[1]	auto[1]	auto[1]	49	1			T200	1		T196	2		T197	1
all_values[14]	auto[0]	auto[0]	auto[0]	63	1			T201	1		T198	1		T299	3
all_values[14]	auto[0]	auto[0]	auto[1]	28	1			T197	1		T297	2		T298	1
all_values[14]	auto[0]	auto[1]	auto[0]	50	1			T201	2		T196	4		T198	1
all_values[14]	auto[0]	auto[1]	auto[1]	29	1			T200	1		T198	1		T299	1
all_values[14]	auto[1]	auto[0]	auto[1]	56	1			T201	1		T200	2		T197	1
all_values[14]	auto[1]	auto[1]	auto[1]	46	1			T200	1		T197	2		T299	2
all_values[15]	auto[0]	auto[0]	auto[0]	61	1			T201	1		T200	2		T197	1
all_values[15]	auto[0]	auto[0]	auto[1]	25	1			T198	1		T300	2		T307	1
all_values[15]	auto[0]	auto[1]	auto[0]	48	1			T201	2		T200	2		T297	2
all_values[15]	auto[0]	auto[1]	auto[1]	27	1			T196	1		T197	1		T299	1
all_values[15]	auto[1]	auto[0]	auto[1]	66	1			T201	1		T196	1		T198	3
all_values[15]	auto[1]	auto[1]	auto[1]	45	1			T196	2		T197	2		T299	1
all_values[16]	auto[0]	auto[0]	auto[0]	57	1			T201	1		T200	1		T197	1
all_values[16]	auto[0]	auto[0]	auto[1]	32	1			T297	1		T308	2		T309	1
all_values[16]	auto[0]	auto[1]	auto[0]	55	1			T200	2		T196	3		T297	1
all_values[16]	auto[0]	auto[1]	auto[1]	22	1			T201	1		T197	1		T198	1
all_values[16]	auto[1]	auto[0]	auto[1]	52	1			T201	1		T198	3		T297	1
all_values[16]	auto[1]	auto[1]	auto[1]	54	1			T201	1		T200	1		T196	1
all_values[17]	auto[0]	auto[0]	auto[0]	91	1			T200	2		T196	2		T197	2
all_values[17]	auto[0]	auto[1]	auto[0]	74	1			T201	1		T196	2		T198	1
all_values[17]	auto[1]	auto[0]	auto[1]	60	1			T201	2		T200	2		T299	1
all_values[17]	auto[1]	auto[1]	auto[1]	47	1			T201	1		T197	2		T198	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal