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 LINE       8941
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       8942
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T238,T239,T240
1	1	1	Covered	T2,T3,T17

 LINE       8945
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T21,T80
1	1	0	Covered	T226,T238,T239
1	1	1	Covered	T16,T21,T80

 LINE       8948
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T7,T18
1	1	0	Not Covered
1	1	1	Covered	T2,T18,T19

 LINE       8949
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T80,T27
1	1	0	Covered	T187,T239,T241
1	1	1	Covered	T21,T80,T27

 LINE       8974
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T226,T230,T231
1	1	1	Covered	T2,T3,T17

 LINE       8999
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T21,T80
1	1	0	Covered	T231,T239,T242
1	1	1	Covered	T21,T80,T60

 LINE       9024
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T26,T8,T29
1	1	0	Covered	T187,T231,T236
1	1	1	Covered	T26,T8,T29

 LINE       9049
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T21,T80
1	1	0	Covered	T237,T238,T239
1	1	1	Covered	T21,T80,T60

 LINE       9074
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T21,T80
1	1	0	Covered	T187,T230,T231
1	1	1	Covered	T21,T80,T100

 LINE       9099
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T26
1	1	0	Covered	T187,T231,T237
1	1	1	Covered	T19,T26,T4

 LINE       9110
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T26,T28
1	1	0	Covered	T187,T237,T243
1	1	1	Covered	T26,T29,T4

 LINE       9121
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T21
1	1	0	Covered	T187,T226,T237
1	1	1	Covered	T19,T21,T26

 LINE       9132
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T21
1	1	0	Covered	T230,T231,T236
1	1	1	Covered	T19,T21,T26

 LINE       9143
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T26,T80
1	1	0	Covered	T226,T231,T236
1	1	1	Covered	T26,T80,T30

 LINE       9154
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T19,T26,T28
1	1	0	Covered	T231,T237,T239
1	1	1	Covered	T19,T26,T4

 LINE       9165
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T18,T26
1	1	0	Covered	T187,T230,T231
1	1	1	Covered	T18,T26,T32

 LINE       9176
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T26
1	1	0	Covered	T187,T244,T237
1	1	1	Covered	T19,T26,T8

 LINE       9187
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T26
1	1	0	Covered	T226,T231,T239
1	1	1	Covered	T19,T26,T60

 LINE       9198
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T26,T80
1	1	0	Covered	T226,T230,T231
1	1	1	Covered	T21,T26,T80

 LINE       9209
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T26,T30
1	1	0	Covered	T231,T237,T239
1	1	1	Covered	T26,T5,T60

 LINE       9220
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T26,T28,T30
1	1	0	Covered	T187,T230,T237
1	1	1	Covered	T26,T4,T60

 LINE       9231
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T21,T80
1	1	0	Covered	T226,T237,T239
1	1	1	Covered	T21,T80,T4

 LINE       9256
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T80,T28
1	1	0	Covered	T237,T239,T241
1	1	1	Covered	T21,T80,T32

 LINE       9281
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T18,T19
1	1	0	Covered	T245
1	1	1	Covered	T19,T103,T108

 LINE       9282
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T18,T19
1	1	0	Covered	T187,T230,T231
1	1	1	Covered	T18,T19,T31

 LINE       9287
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T18,T19,T28
1	1	0	Not Covered
1	1	1	Covered	T19,T29,T30

 LINE       9288
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T18,T19,T28
1	1	0	Covered	T226,T230,T237
1	1	1	Covered	T18,T19,T104

 LINE       9293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T28,T30
1	1	0	Not Covered
1	1	1	Covered	T34,T25,T246

 LINE       9294
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T28,T30
1	1	0	Covered	T226,T230,T237
1	1	1	Covered	T25,T22,T23

 LINE       9313
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T187,T230,T231
1	1	1	Covered	T1,T2,T3

 LINE       9326
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T7,T28
1	1	0	Covered	T230,T247,T248
1	1	1	Covered	T1,T7,T8

 LINE       9329
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T21
1	1	0	Covered	T238,T239,T241
1	1	1	Covered	T19,T21,T80

 LINE       9336
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T28,T30
1	1	0	Not Covered
1	1	1	Covered	T234,T188,T199

 LINE       9337
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T28,T30
1	1	0	Covered	T187,T230,T231
1	1	1	Covered	T234,T188,T199

 LINE       9350
 EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T30,T61
1	1	0	Not Covered
1	1	1	Covered	T234,T188,T199

 LINE       9351
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T30,T61
1	1	0	Covered	T187,T230,T237
1	1	1	Covered	T234,T188,T199

 LINE       9362
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T28,T30
1	1	0	Not Covered
1	1	1	Covered	T234,T188,T199

 LINE       9363
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T28,T30
1	1	0	Covered	T226,T230,T237
1	1	1	Covered	T234,T188,T199

 LINE       9368
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T28,T30
1	1	0	Not Covered
1	1	1	Covered	T234,T188,T199

 LINE       9369
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T28,T30
1	1	0	Covered	T226,T230,T231
1	1	1	Covered	T234,T188,T199

 LINE       9881
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T7,T8