Unified Coverage Report :: Module :: usb_fs_nb_out_pe

Module : usb_fs_nb_out_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.10	99.21	92.54		87.50	96.23	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe	95.47	99.21	92.54		87.50	98.08	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.47	99.21	92.54		87.50	98.08	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.47	99.21	92.54		87.50	98.08	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
TOTAL		127	126	99.21
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	184	6	6	100.00
ALWAYS	196	4	4	100.00
ALWAYS	212	55	54	98.18
CONT_ASSIGN	326	1	1	100.00
ALWAYS	329	3	3	100.00
ALWAYS	337	3	3	100.00
ALWAYS	346	7	7	100.00
CONT_ASSIGN	360	1	1	100.00
ALWAYS	363	5	5	100.00
ALWAYS	373	9	9	100.00
ALWAYS	390	3	3	100.00
ALWAYS	402	6	6	100.00
CONT_ASSIGN	418	1	1	100.00
ALWAYS	421	6	6	100.00
CONT_ASSIGN	435	1	1	100.00

89                        logic                        unused_1;
90         1/1            assign unused_1 = tx_pkt_end_i;
           Tests:       T1 T2 T3 
91                      
92                        ///////////////////////////////////
93                        // out transaction state machine //
94                        ///////////////////////////////////
95                        import usb_consts_pkg::*;
96                      
97                        typedef enum logic [2:0] {
98                          StIdle,
99                          StRcvdOut,
100                         StRcvdDataStart,
101                         StRcvdDataEnd,
102                         StRcvdIsoDataEnd
103                       } state_out_e;
104                     
105                       state_out_e  out_xact_state;
106                       state_out_e  out_xact_state_next;
107                     
108                       logic out_xact_start;
109                       logic new_pkt_end;
110                       logic rollback_data;
111                     
112                       // set when the endpoint buffer is unable to receive the out transaction
113                       logic nak_out_transaction;
114                     
115                       // data toggle state
116                       logic [NumOutEps - 1:0] data_toggle_q, data_toggle_d;
117                     
118                       // Decode the rx token
119                       logic       token_received, out_token_received, setup_token_received;
120                       logic       invalid_packet_received, data_packet_received, non_data_packet_received;
121                       logic       bad_data_toggle;
122                       logic       ep_in_hw, ep_active, ep_is_control;
123                       logic [3:0] out_ep_current_d;
124                     
125                       // 1: If the current transaction is a SETUP, 0: OUT
126                       logic current_xact_setup_q;
127                     
128                       // More syntax so can compare with enum
129                       usb_pid_type_e rx_pid_type;
130                       usb_pid_e      rx_pid;
131        1/1            assign rx_pid_type = usb_pid_type_e'(rx_pid_i[1:0]);
           Tests:       T1 T2 T3 
132        1/1            assign rx_pid      = usb_pid_e'(rx_pid_i);
           Tests:       T1 T2 T3 
133                     
134        1/1            assign token_received =
           Tests:       T1 T2 T3 
135                         rx_pkt_end_i &&
136                         rx_pkt_valid_i &&
137                         rx_pid_type == UsbPidTypeToken &&
138                         rx_addr_i == dev_addr_i;
139                     
140        1/1            assign out_token_received =
           Tests:       T1 T2 T3 
141                         token_received &&
142                         rx_pid == UsbPidOut;
143                     
144        1/1            assign setup_token_received =
           Tests:       T1 T2 T3 
145                         token_received &&
146                         rx_pid == UsbPidSetup;
147                     
148        1/1            assign invalid_packet_received =
           Tests:       T1 T2 T3 
149                         rx_pkt_end_i &&
150                         !rx_pkt_valid_i;
151                     
152        1/1            assign data_packet_received =
           Tests:       T1 T2 T3 
153                         rx_pkt_end_i &&
154                         rx_pkt_valid_i &&
155                         ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1));
156                     
157        1/1            assign non_data_packet_received =
           Tests:       T1 T2 T3 
158                         rx_pkt_end_i &&
159                         rx_pkt_valid_i &&
160                         !((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1));
161                     
162                       // Is the specified endpoint actually implemented in hardware?
163        1/1            assign ep_in_hw = {1'b0, rx_endp_i} < NumOutEps;
           Tests:       T1 T2 T3 
164        1/1            assign out_ep_current_d = ep_in_hw ? rx_endp_i : '0;
           Tests:       T1 T2 T3 
165                     
166                       // Make widths work - out_ep_current_d/out_ep_current_o only hold implemented endpoint IDs.
167                       // These signals can be used to index signals of NumOutEps width.
168                       // They are only valid if ep_in_hw is set, i.e., if the specified endpoint is implemented.
169                       logic [OutEpW-1:0] out_ep_index;
170                       logic [OutEpW-1:0] out_ep_index_d;
171        1/1            assign out_ep_index   = out_ep_current_o[0 +: OutEpW];
           Tests:       T1 T2 T3 
172        1/1            assign out_ep_index_d = out_ep_current_d[0 +: OutEpW];
           Tests:       T1 T2 T3 
173                     
174                       // Is the endpoint active?
175        1/1            assign ep_active = out_ep_enabled_i[out_ep_index_d] & ep_in_hw;
           Tests:       T1 T2 T3 
176        1/1            assign ep_is_control = out_ep_control_i[out_ep_index_d];
           Tests:       T1 T2 T3 
177                     
178        1/1            assign bad_data_toggle =
           Tests:       T1 T2 T3 
179                         data_packet_received &&
180                         ep_active &&
181                         rx_pid_i[3] != data_toggle_q[out_ep_index_d];
182                     
183                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
184        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
185        1/1                out_ep_setup_o <= '0;
           Tests:       T1 T2 T3 
186                         end else begin
187        1/1                if (setup_token_received && ep_active) begin
           Tests:       T1 T2 T3 
188        1/1                  out_ep_setup_o[out_ep_index_d] <= 1'b1;
           Tests:       T2 T24 T82 
189        1/1                end else if (out_token_received && ep_active) begin
           Tests:       T1 T2 T3 
190        1/1                  out_ep_setup_o[out_ep_index_d] <= 1'b0;
           Tests:       T1 T18 T19 
191                           end
                        MISSING_ELSE
192                         end
193                       end
194                     
195                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
196        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
197        1/1                out_ep_data_o <= 0;
           Tests:       T1 T2 T3 
198                         end else begin
199        1/1                if (rx_data_put_i) begin
           Tests:       T1 T2 T3 
200        1/1                  out_ep_data_o <= rx_data_i;
           Tests:       T1 T2 T17 
201                           end
                        MISSING_ELSE
202                         end
203                       end
204                     
205                       ///////////////////////////////////
206                       // out transaction state machine //
207                       ///////////////////////////////////
208                     
209                       logic [AckTimeoutCntW-1:0] timeout_cntdown_d, timeout_cntdown_q;
210                     
211                       always_comb begin
212        1/1              out_ep_acked_o = 1'b0;
           Tests:       T1 T2 T3 
213        1/1              out_xact_start = 1'b0;
           Tests:       T1 T2 T3 
214        1/1              out_xact_state_next = out_xact_state;
           Tests:       T1 T2 T3 
215        1/1              tx_pkt_start_o = 1'b0;
           Tests:       T1 T2 T3 
216        1/1              tx_pid_o = 4'b0000;
           Tests:       T1 T2 T3 
217        1/1              new_pkt_end = 1'b0;
           Tests:       T1 T2 T3 
218        1/1              rollback_data = 1'b0;
           Tests:       T1 T2 T3 
219        1/1              timeout_cntdown_d = AckTimeoutCnt[AckTimeoutCntW-1:0];
           Tests:       T1 T2 T3 
220                     
221        1/1              unique case (out_xact_state)
           Tests:       T1 T2 T3 
222                           StIdle: begin
223                             // For unimplemented EPs, transactions are ignored.
224                             // SETUP transactions are also ignored for non-control EPs.
225        1/1                  if (ep_active && (out_token_received || (setup_token_received && ep_is_control))) begin
           Tests:       T1 T2 T3 
226        1/1                    out_xact_state_next = StRcvdOut;
           Tests:       T1 T2 T18 
227        1/1                    out_xact_start = 1'b1;
           Tests:       T1 T2 T18 
228                             end else begin
229        1/1                    out_xact_state_next = StIdle;
           Tests:       T1 T2 T3 
230                             end
231                           end
232                     
233                           StRcvdOut: begin
234                             // The spec says we have up to 18 bit times to wait for the host's
235                             // data packet. If it doesn't arrive in time, we must invalidate the
236                             // transaction.
237        1/1                  timeout_cntdown_d = timeout_cntdown_q - 1'b1;
           Tests:       T1 T2 T18 
238                     
239        1/1                  if (rx_pkt_start_i) begin
           Tests:       T1 T2 T18 
240        1/1                    out_xact_state_next = StRcvdDataStart;
           Tests:       T1 T2 T18 
241        1/1                  end else if (timeout_cntdown_q == '0) begin
           Tests:       T1 T2 T18 
242        0/1     ==>            out_xact_state_next = StIdle;
243                             end else begin
244        1/1                    out_xact_state_next = StRcvdOut;
           Tests:       T1 T2 T18 
245                             end
246                           end
247                     
248                           StRcvdDataStart: begin
249        1/1                  if (!ep_is_control && out_ep_iso_i[out_ep_index] && data_packet_received) begin
           Tests:       T1 T2 T18 
250                               // ISO EP: Don't send a handshake, ignore toggle.
251                               // But ignore iso bit for endpoints marked control. This is
252                               // a configuration error.
253        1/1                    out_xact_state_next = StRcvdIsoDataEnd;
           Tests:       T24 T81 T6 
254        1/1                  end else if (bad_data_toggle && !out_ep_stall_i[out_ep_index]) begin
           Tests:       T1 T2 T18 
255                               // The DATA toggle was wrong (skipped when this EP is stalled)
256                               // Note: bad_data_toggle is meaningless for unimplemented EPs.
257        1/1                    out_xact_state_next = StIdle;
           Tests:       T19 T30 T66 
258        1/1                    rollback_data = 1'b1;
           Tests:       T19 T30 T66 
259        1/1                    tx_pkt_start_o = 1'b1;
           Tests:       T19 T30 T66 
260        1/1                    tx_pid_o = {UsbPidAck}; // ACK by spec because this is most likely previous ACK was lost
           Tests:       T19 T30 T66 
261        1/1                  end else if (invalid_packet_received || non_data_packet_received) begin
           Tests:       T1 T2 T18 
262                               // in these cases eg bad CRC, send no response (not a NAK)
263        1/1                    out_xact_state_next = StIdle;
           Tests:       T30 T66 T67 
264        1/1                    rollback_data = 1'b1;
           Tests:       T30 T66 T67 
265        1/1                  end else if (data_packet_received) begin
           Tests:       T1 T2 T18 
266        1/1                    out_xact_state_next = StRcvdDataEnd;
           Tests:       T1 T2 T18 
267                             end else begin
268        1/1                    out_xact_state_next = StRcvdDataStart;
           Tests:       T1 T2 T18 
269                             end
270                           end
271                     
272                           StRcvdDataEnd: begin
273        1/1                  out_xact_state_next = StIdle;
           Tests:       T1 T2 T18 
274        1/1                  tx_pkt_start_o = 1'b1;
           Tests:       T1 T2 T18 
275                     
276        1/1                  if (current_xact_setup_q) begin
           Tests:       T1 T2 T18 
277                               // SETUP transactions end here
278        1/1                    if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
           Tests:       T2 T24 T82 
279                                 // SETUP transactions that fail to be received are dropped without a response.
280        1/1                      tx_pkt_start_o = 1'b0;
           Tests:       T178 T179 T180 
281        1/1                      rollback_data = 1'b1;
           Tests:       T178 T179 T180 
282                               end else begin
283        1/1                      tx_pid_o = {UsbPidAck};
           Tests:       T2 T24 T82 
284        1/1                      new_pkt_end = 1'b1;
           Tests:       T2 T24 T82 
285        1/1                      out_ep_acked_o = 1'b1;
           Tests:       T2 T24 T82 
286                               end
287                             end else begin
288                               // Non-isochronous OUT transactions end here
289        1/1                    if (out_ep_stall_i[out_ep_index]) begin
           Tests:       T1 T18 T19 
290        1/1                      tx_pid_o = {UsbPidStall}; // STALL
           Tests:       T155 T103 T181 
291        1/1                      rollback_data = 1'b1; // Packet not accepted
           Tests:       T155 T103 T181 
292        1/1                    end else if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
           Tests:       T1 T18 T19 
293        1/1                      tx_pid_o = {UsbPidNak}; // NAK -- the endpoint could not accept the data at the moment
           Tests:       T30 T66 T68 
294        1/1                      rollback_data = 1'b1;
           Tests:       T30 T66 T68 
295                               end else begin
296        1/1                      tx_pid_o = {UsbPidAck}; // ACK
           Tests:       T1 T18 T19 
297        1/1                      new_pkt_end = 1'b1;
           Tests:       T1 T18 T19 
298        1/1                      out_ep_acked_o = 1'b1;
           Tests:       T1 T18 T19 
299                               end
300                             end
301                           end
302                     
303                           StRcvdIsoDataEnd: begin
304                             // Isochronous OUT transactions end here
305        1/1                  out_xact_state_next = StIdle;
           Tests:       T24 T81 T6 
306                     
307        1/1                  if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
           Tests:       T24 T81 T6 
308                               // We got a valid packet, but can't store it (error that the software must resolve)
309        1/1                    rollback_data = 1'b1;
           Tests:       T24 T51 T182 
310                             end else begin
311                               // We got a valid packet, but we don't send an ACK on the bus
312        1/1                    new_pkt_end    = 1'b1;
           Tests:       T81 T6 T183 
313        1/1                    out_ep_acked_o = 1'b1;
           Tests:       T81 T6 T183 
314                             end
315                           end
316                     
317                           default: out_xact_state_next = StIdle;
318                         endcase
319                       end
320                     
321                       `ASSERT(OutXactStateValid_A,
322                         out_xact_state inside {StIdle, StRcvdOut, StRcvdDataStart, StRcvdDataEnd, StRcvdIsoDataEnd},
323                         clk_48mhz_i)
324                     
325                       // could flop this if needed
326        1/1            assign out_ep_rollback_o = rollback_data;
           Tests:       T1 T2 T3 
327                     
328                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
329        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
330        1/1                timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
           Tests:       T1 T2 T3 
331                         end else begin
332        1/1                timeout_cntdown_q <= timeout_cntdown_d;
           Tests:       T1 T2 T3 
333                         end
334                       end
335                     
336                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
337        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
338        1/1                out_xact_state <= StIdle;
           Tests:       T1 T2 T3 
339                         end else begin
340        1/1                out_xact_state <= link_reset_i ? StIdle : out_xact_state_next;
           Tests:       T1 T2 T3 
341                         end
342                       end
343                     
344                       // Updating of data toggles
345                       always_comb begin : proc_data_toggle_d
346        1/1              data_toggle_d = data_toggle_q;
           Tests:       T1 T2 T3 
347                     
348        1/1              if (setup_token_received && ep_active) begin
           Tests:       T1 T2 T3 
349        1/1                data_toggle_d[out_ep_index_d] = 1'b0;
           Tests:       T2 T24 T82 
350        1/1              end else if (new_pkt_end) begin
           Tests:       T1 T2 T3 
351        1/1                data_toggle_d[out_ep_index] = ~data_toggle_q[out_ep_index];
           Tests:       T1 T2 T18 
352                         end
                        MISSING_ELSE
353                         // Selective modification by software
354        1/1              if (out_datatog_we_i) begin
           Tests:       T1 T2 T3 
355        1/1                data_toggle_d = (data_toggle_d & ~out_datatog_mask_i) |
           Tests:       T18 T19 T30 
356                                           (out_datatog_status_i & out_datatog_mask_i);
357                         end
                        MISSING_ELSE
358                       end
359                       // Supply current data toggles to register interface
360        1/1            assign out_data_toggle_o = data_toggle_q;
           Tests:       T1 T2 T3 
361                     
362                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
363        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
364        1/1                data_toggle_q <= '0; // Clear for all endpoints
           Tests:       T1 T2 T3 
365        1/1              end else if (link_reset_i) begin
           Tests:       T1 T2 T3 
366        1/1                data_toggle_q <= '0; // Clear for all endpoints
           Tests:       T1 T2 T3 
367                         end else begin
368        1/1                data_toggle_q <= data_toggle_d;
           Tests:       T1 T2 T3 
369                         end
370                       end
371                     
372                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
373        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
374        1/1                out_ep_newpkt_o       <= 1'b0;
           Tests:       T1 T2 T3 
375        1/1                out_ep_current_o      <= '0;
           Tests:       T1 T2 T3 
376        1/1                current_xact_setup_q  <= 1'b0;
           Tests:       T1 T2 T3 
377                         end else begin
378        1/1                if (out_xact_start) begin
           Tests:       T1 T2 T3 
379        1/1                  out_ep_newpkt_o      <= 1'b1;
           Tests:       T1 T2 T18 
380        1/1                  out_ep_current_o     <= out_ep_current_d;
           Tests:       T1 T2 T18 
381        1/1                  current_xact_setup_q <= setup_token_received;
           Tests:       T1 T2 T18 
382                           end else begin
383        1/1                  out_ep_newpkt_o <= 1'b0;
           Tests:       T1 T2 T3 
384                           end
385                         end
386                       end
387                     
388                       // put data strobe follows the rx strobe (which will latch the data)
389                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
390        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
391        1/1                out_ep_data_put_o <= 1'b0;
           Tests:       T1 T2 T3 
392                         end else begin
393        1/1                out_ep_data_put_o <= ((out_xact_state == StRcvdDataStart) && rx_data_put_i);
           Tests:       T1 T2 T3 
394                         end
395                       end
396                     
397                       // nak an OUT if any data comes in with the endpoint full
398                       // Note that if there is a full size packet buffer this will only be all or nothing
399                       // but in the case there was a FIFO with less than a max packet size free you
400                       // could get lucky and the packet received be small and fit with no need to NAK
401                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
402        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
403        1/1                nak_out_transaction <= 1'b0;
           Tests:       T1 T2 T3 
404                         end else begin
405        1/1                if ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut)) begin
           Tests:       T1 T2 T3 
406        1/1                  nak_out_transaction <= 1'b0;
           Tests:       T1 T2 T3 
407        1/1                end else if (out_ep_data_put_o && out_ep_full_i[out_ep_index]) begin
           Tests:       T1 T2 T18 
408        1/1                  nak_out_transaction <= 1'b1;
           Tests:       T24 T30 T66 
409                           end
                        MISSING_ELSE
410                         end
411                       end
412                     
413                       // address increment whenever there is a data put unless
414                       // -- already going to NAK transaction and replay things
415                       // -- the address is at max packet size
416                       // NOTE if more than max packet size received then data is lost
417                       logic increment_addr;
418        1/1            assign increment_addr = !nak_out_transaction && (~&out_ep_put_addr_o) && out_ep_data_put_o;
           Tests:       T1 T2 T3 
419                     
420                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
421        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
422        1/1                out_ep_put_addr_o <= '0;
           Tests:       T1 T2 T3 
423                         end else begin
424        1/1                if (out_xact_state == StRcvdOut) begin
           Tests:       T1 T2 T3 
425        1/1                  out_ep_put_addr_o <= '0;
           Tests:       T1 T2 T18 
426        1/1                end else if ((out_xact_state == StRcvdDataStart) && increment_addr) begin
           Tests:       T1 T2 T3 
427        1/1                  out_ep_put_addr_o <= out_ep_put_addr_o + 1;
           Tests:       T1 T2 T18 
428                           end
                        MISSING_ELSE
429                         end
430                       end
431                     
432                       ///////////////////////////////////////////////////////////////////////////////////////////////
433                       // Count OUT transactions that have been ACKed and dropped because of unexpected Data Toggles.
434                       ///////////////////////////////////////////////////////////////////////////////////////////////
435        1/1            assign event_datatog_out_o = (out_xact_state == StRcvdDataStart) &&
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : usb_fs_nb_out_pe

	Total	Covered	Percent
Conditions	134	124	92.54
Logical	134	124	92.54
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T18
1	0	1	1	Covered	T69,T107,T73
1	1	0	1	Covered	T1,T2,T18
1	1	1	0	Covered	T20,T21,T23
1	1	1	1	Covered	T1,T2,T18

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T2,T18,T19
1	1	Covered	T1,T18,T19

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Covered	T1,T18,T19
1	1	Covered	T2,T20,T24

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T17,T20,T23

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T30,T66,T67
1	1	0	Covered	T1,T2,T18
1	1	1	Covered	T1,T2,T17

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T18,T19
1	0	Covered	T1,T2,T17

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T18,T19

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T17,T20,T23
1	1	0	Covered	T1,T2,T17
1	1	1	Covered	T1,T2,T18

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T18,T19
1	0	Covered	T1,T2,T17

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T18,T19

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---

-1-	Status	Tests
0	Covered	T21,T8,T112
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T113,T74,T140
1	1	Covered	T1,T2,T18

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T74,T115,T76
1	1	0	Covered	T1,T2,T18
1	1	1	Covered	T19,T30,T66

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T20,T74,T114
1	1	Covered	T2,T24,T82

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T41,T4,T74
1	1	Covered	T1,T18,T19

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T41,T4
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T24
1	0	Covered	T1,T18,T19

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Covered	T184,T185,T114
1	1	Covered	T2,T20,T24

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Not Covered

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T186,T187,T188
1	0	1	Covered	T1,T18,T19
1	1	0	Covered	T24,T81,T6
1	1	1	Covered	T24,T81,T6

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Not Covered
1	1	Covered	T19,T30,T66

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T74,T76,T77
1	0	Covered	T30,T66,T67

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T24,T82
0	1	Not Covered
1	0	Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T19
0	1	Not Covered
1	0	Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T81,T6,T183
0	1	Not Covered
1	0	Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T20,T74,T114
1	1	Covered	T2,T24,T82

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T20,T23
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T66
1	0	Covered	T1,T2,T18
1	1	Covered	T24,T30,T66

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T30,T66
1	0	1	Covered	T117,T80,T67
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T18

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T114,T115,T76
1	0	1	1	Covered	T6,T174,T186
1	1	0	1	Not Covered
1	1	1	0	Covered	T1,T2,T18
1	1	1	1	Covered	T19,T30,T66

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T81,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T174,T189

---

FSM Coverage for Module : usb_fs_nb_out_pe

Summary for FSM :: out_xact_state

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	7	87.50
Sequences	0	0

State, Transition and Sequence Details for FSM :: out_xact_state

---

states	Line No.	Covered	Tests
StIdle	340	Covered	T1,T2,T3
StRcvdDataEnd	266	Covered	T1,T2,T18
StRcvdDataStart	240	Covered	T1,T2,T18
StRcvdIsoDataEnd	253	Covered	T24,T81,T6
StRcvdOut	226	Covered	T1,T2,T18

transitions	Line No.	Covered	Tests
StIdle->StRcvdOut	226	Covered	T1,T2,T18
StRcvdDataEnd->StIdle	340	Covered	T1,T2,T18
StRcvdDataStart->StIdle	340	Covered	T19,T30,T66
StRcvdDataStart->StRcvdDataEnd	266	Covered	T1,T2,T18
StRcvdDataStart->StRcvdIsoDataEnd	253	Covered	T24,T81,T6
StRcvdIsoDataEnd->StIdle	340	Covered	T24,T81,T6
StRcvdOut->StIdle	340	Not Covered
StRcvdOut->StRcvdDataStart	240	Covered	T1,T2,T18

---

Branch Coverage for Module : usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
Branches		53	51	96.23
TERNARY	164	2	2	100.00
IF	184	4	4	100.00
IF	196	3	3	100.00
CASE	221	18	16	88.89
IF	329	2	2	100.00
IF	337	3	3	100.00
IF	348	3	3	100.00
IF	354	2	2	100.00
IF	363	3	3	100.00
IF	373	3	3	100.00
IF	390	2	2	100.00
IF	402	4	4	100.00
IF	421	4	4	100.00

164          assign out_ep_current_d = ep_in_hw ? rx_endp_i : '0;
                                                -1-  
                                                ==>  
                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T8,T112

184            if (!rst_ni) begin
               -1-  
185              out_ep_setup_o <= '0;
                 ==>
186            end else begin
187              if (setup_token_received && ep_active) begin
                 -2-  
188                out_ep_setup_o[out_ep_index_d] <= 1'b1;
                   ==>
189              end else if (out_token_received && ep_active) begin
                          -3-  
190                out_ep_setup_o[out_ep_index_d] <= 1'b0;
                   ==>
191              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T24,T82
0	0	1	Covered	T1,T18,T19
0	0	0	Covered	T1,T2,T3

196            if (!rst_ni) begin
               -1-  
197              out_ep_data_o <= 0;
                 ==>
198            end else begin
199              if (rx_data_put_i) begin
                 -2-  
200                out_ep_data_o <= rx_data_i;
                   ==>
201              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

221            unique case (out_xact_state)
                      -1-  
222              StIdle: begin
223                // For unimplemented EPs, transactions are ignored.
224                // SETUP transactions are also ignored for non-control EPs.
225                if (ep_active && (out_token_received || (setup_token_received && ep_is_control))) begin
                   -2-  
226                  out_xact_state_next = StRcvdOut;
                     ==>
227                  out_xact_start = 1'b1;
228                end else begin
229                  out_xact_state_next = StIdle;
                     ==>
230                end
231              end
232        
233              StRcvdOut: begin
234                // The spec says we have up to 18 bit times to wait for the host's
235                // data packet. If it doesn't arrive in time, we must invalidate the
236                // transaction.
237                timeout_cntdown_d = timeout_cntdown_q - 1'b1;
238        
239                if (rx_pkt_start_i) begin
                   -3-  
240                  out_xact_state_next = StRcvdDataStart;
                     ==>
241                end else if (timeout_cntdown_q == '0) begin
                            -4-  
242                  out_xact_state_next = StIdle;
                     ==>
243                end else begin
244                  out_xact_state_next = StRcvdOut;
                     ==>
245                end
246              end
247        
248              StRcvdDataStart: begin
249                if (!ep_is_control && out_ep_iso_i[out_ep_index] && data_packet_received) begin
                   -5-  
250                  // ISO EP: Don't send a handshake, ignore toggle.
251                  // But ignore iso bit for endpoints marked control. This is
252                  // a configuration error.
253                  out_xact_state_next = StRcvdIsoDataEnd;
                     ==>
254                end else if (bad_data_toggle && !out_ep_stall_i[out_ep_index]) begin
                            -6-  
255                  // The DATA toggle was wrong (skipped when this EP is stalled)
256                  // Note: bad_data_toggle is meaningless for unimplemented EPs.
257                  out_xact_state_next = StIdle;
                     ==>
258                  rollback_data = 1'b1;
259                  tx_pkt_start_o = 1'b1;
260                  tx_pid_o = {UsbPidAck}; // ACK by spec because this is most likely previous ACK was lost
261                end else if (invalid_packet_received || non_data_packet_received) begin
                            -7-  
262                  // in these cases eg bad CRC, send no response (not a NAK)
263                  out_xact_state_next = StIdle;
                     ==>
264                  rollback_data = 1'b1;
265                end else if (data_packet_received) begin
                            -8-  
266                  out_xact_state_next = StRcvdDataEnd;
                     ==>
267                end else begin
268                  out_xact_state_next = StRcvdDataStart;
                     ==>
269                end
270              end
271        
272              StRcvdDataEnd: begin
273                out_xact_state_next = StIdle;
274                tx_pkt_start_o = 1'b1;
275        
276                if (current_xact_setup_q) begin
                   -9-  
277                  // SETUP transactions end here
278                  if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
                     -10-  
279                    // SETUP transactions that fail to be received are dropped without a response.
280                    tx_pkt_start_o = 1'b0;
                       ==>
281                    rollback_data = 1'b1;
282                  end else begin
283                    tx_pid_o = {UsbPidAck};
                       ==>
284                    new_pkt_end = 1'b1;
285                    out_ep_acked_o = 1'b1;
286                  end
287                end else begin
288                  // Non-isochronous OUT transactions end here
289                  if (out_ep_stall_i[out_ep_index]) begin
                     -11-  
290                    tx_pid_o = {UsbPidStall}; // STALL
                       ==>
291                    rollback_data = 1'b1; // Packet not accepted
292                  end else if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
                              -12-  
293                    tx_pid_o = {UsbPidNak}; // NAK -- the endpoint could not accept the data at the moment
                       ==>
294                    rollback_data = 1'b1;
295                  end else begin
296                    tx_pid_o = {UsbPidAck}; // ACK
                       ==>
297                    new_pkt_end = 1'b1;
298                    out_ep_acked_o = 1'b1;
299                  end
300                end
301              end
302        
303              StRcvdIsoDataEnd: begin
304                // Isochronous OUT transactions end here
305                out_xact_state_next = StIdle;
306        
307                if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
                   -13-  
308                  // We got a valid packet, but can't store it (error that the software must resolve)
309                  rollback_data = 1'b1;
                     ==>
310                end else begin
311                  // We got a valid packet, but we don't send an ACK on the bus
312                  new_pkt_end    = 1'b1;
                     ==>
313                  out_ep_acked_o = 1'b1;
314                end
315              end
316        
317              default: out_xact_state_next = StIdle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRcvdOut	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
StRcvdOut	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdOut	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
StRcvdDataStart	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T81,T6
StRcvdDataStart	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T19,T30,T66
StRcvdDataStart	-	-	-	0	0	1	-	-	-	-	-	-	Covered	T30,T66,T67
StRcvdDataStart	-	-	-	0	0	0	1	-	-	-	-	-	Covered	T1,T2,T18
StRcvdDataStart	-	-	-	0	0	0	0	-	-	-	-	-	Covered	T1,T2,T18
StRcvdDataEnd	-	-	-	-	-	-	-	1	1	-	-	-	Covered	T178,T179,T180
StRcvdDataEnd	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T2,T24,T82
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	1	-	-	Covered	T155,T103,T181
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	1	-	Covered	T30,T66,T68
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	0	-	Covered	T1,T18,T19
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T24,T51,T182
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T81,T6,T183
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

329            if (!rst_ni) begin
               -1-  
330              timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
                 ==>
331            end else begin
332              timeout_cntdown_q <= timeout_cntdown_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

337            if (!rst_ni) begin
               -1-  
338              out_xact_state <= StIdle;
                 ==>
339            end else begin
340              out_xact_state <= link_reset_i ? StIdle : out_xact_state_next;
                                                -2-  
                                                ==>  
                                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

348            if (setup_token_received && ep_active) begin
               -1-  
349              data_toggle_d[out_ep_index_d] = 1'b0;
                 ==>
350            end else if (new_pkt_end) begin
                        -2-  
351              data_toggle_d[out_ep_index] = ~data_toggle_q[out_ep_index];
                 ==>
352            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T24,T82
0	1	Covered	T1,T2,T18
0	0	Covered	T1,T2,T3

354            if (out_datatog_we_i) begin
               -1-  
355              data_toggle_d = (data_toggle_d & ~out_datatog_mask_i) |
                 ==>
356                              (out_datatog_status_i & out_datatog_mask_i);
357            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T30
0	Covered	T1,T2,T3

363            if (!rst_ni) begin
               -1-  
364              data_toggle_q <= '0; // Clear for all endpoints
                 ==>
365            end else if (link_reset_i) begin
                        -2-  
366              data_toggle_q <= '0; // Clear for all endpoints
                 ==>
367            end else begin
368              data_toggle_q <= data_toggle_d;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

373            if (!rst_ni) begin
               -1-  
374              out_ep_newpkt_o       <= 1'b0;
                 ==>
375              out_ep_current_o      <= '0;
376              current_xact_setup_q  <= 1'b0;
377            end else begin
378              if (out_xact_start) begin
                 -2-  
379                out_ep_newpkt_o      <= 1'b1;
                   ==>
380                out_ep_current_o     <= out_ep_current_d;
381                current_xact_setup_q <= setup_token_received;
382              end else begin
383                out_ep_newpkt_o <= 1'b0;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T18
0	0	Covered	T1,T2,T3

390            if (!rst_ni) begin
               -1-  
391              out_ep_data_put_o <= 1'b0;
                 ==>
392            end else begin
393              out_ep_data_put_o <= ((out_xact_state == StRcvdDataStart) && rx_data_put_i);
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

402            if (!rst_ni) begin
               -1-  
403              nak_out_transaction <= 1'b0;
                 ==>
404            end else begin
405              if ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut)) begin
                 -2-  
406                nak_out_transaction <= 1'b0;
                   ==>
407              end else if (out_ep_data_put_o && out_ep_full_i[out_ep_index]) begin
                          -3-  
408                nak_out_transaction <= 1'b1;
                   ==>
409              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T24,T30,T66
0	0	0	Covered	T1,T2,T18

421            if (!rst_ni) begin
               -1-  
422              out_ep_put_addr_o <= '0;
                 ==>
423            end else begin
424              if (out_xact_state == StRcvdOut) begin
                 -2-  
425                out_ep_put_addr_o <= '0;
                   ==>
426              end else if ((out_xact_state == StRcvdDataStart) && increment_addr) begin
                          -3-  
427                out_ep_put_addr_o <= out_ep_put_addr_o + 1;
                   ==>
428              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T18
0	0	1	Covered	T1,T2,T18
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usb_fs_nb_out_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutXactStateValid_A	578377389	578088936	0	0

OutXactStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578377389	578088936	0	0
T1	9647	9557	0	0
T2	8147	8076	0	0
T3	7219	7156	0	0
T7	279126	279033	0	0
T17	9642	9576	0	0
T18	23955	23883	0	0
T19	44812	44731	0	0
T20	27564	27485	0	0
T21	10864	10805	0	0
T22	1813	1750	0	0

Line Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
TOTAL		127	126	99.21
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	184	6	6	100.00
ALWAYS	196	4	4	100.00
ALWAYS	212	55	54	98.18
CONT_ASSIGN	326	1	1	100.00
ALWAYS	329	3	3	100.00
ALWAYS	337	3	3	100.00
ALWAYS	346	7	7	100.00
CONT_ASSIGN	360	1	1	100.00
ALWAYS	363	5	5	100.00
ALWAYS	373	9	9	100.00
ALWAYS	390	3	3	100.00
ALWAYS	402	6	6	100.00
CONT_ASSIGN	418	1	1	100.00
ALWAYS	421	6	6	100.00
CONT_ASSIGN	435	1	1	100.00

89                        logic                        unused_1;
90         1/1            assign unused_1 = tx_pkt_end_i;
           Tests:       T1 T2 T3 
91                      
92                        ///////////////////////////////////
93                        // out transaction state machine //
94                        ///////////////////////////////////
95                        import usb_consts_pkg::*;
96                      
97                        typedef enum logic [2:0] {
98                          StIdle,
99                          StRcvdOut,
100                         StRcvdDataStart,
101                         StRcvdDataEnd,
102                         StRcvdIsoDataEnd
103                       } state_out_e;
104                     
105                       state_out_e  out_xact_state;
106                       state_out_e  out_xact_state_next;
107                     
108                       logic out_xact_start;
109                       logic new_pkt_end;
110                       logic rollback_data;
111                     
112                       // set when the endpoint buffer is unable to receive the out transaction
113                       logic nak_out_transaction;
114                     
115                       // data toggle state
116                       logic [NumOutEps - 1:0] data_toggle_q, data_toggle_d;
117                     
118                       // Decode the rx token
119                       logic       token_received, out_token_received, setup_token_received;
120                       logic       invalid_packet_received, data_packet_received, non_data_packet_received;
121                       logic       bad_data_toggle;
122                       logic       ep_in_hw, ep_active, ep_is_control;
123                       logic [3:0] out_ep_current_d;
124                     
125                       // 1: If the current transaction is a SETUP, 0: OUT
126                       logic current_xact_setup_q;
127                     
128                       // More syntax so can compare with enum
129                       usb_pid_type_e rx_pid_type;
130                       usb_pid_e      rx_pid;
131        1/1            assign rx_pid_type = usb_pid_type_e'(rx_pid_i[1:0]);
           Tests:       T1 T2 T3 
132        1/1            assign rx_pid      = usb_pid_e'(rx_pid_i);
           Tests:       T1 T2 T3 
133                     
134        1/1            assign token_received =
           Tests:       T1 T2 T3 
135                         rx_pkt_end_i &&
136                         rx_pkt_valid_i &&
137                         rx_pid_type == UsbPidTypeToken &&
138                         rx_addr_i == dev_addr_i;
139                     
140        1/1            assign out_token_received =
           Tests:       T1 T2 T3 
141                         token_received &&
142                         rx_pid == UsbPidOut;
143                     
144        1/1            assign setup_token_received =
           Tests:       T1 T2 T3 
145                         token_received &&
146                         rx_pid == UsbPidSetup;
147                     
148        1/1            assign invalid_packet_received =
           Tests:       T1 T2 T3 
149                         rx_pkt_end_i &&
150                         !rx_pkt_valid_i;
151                     
152        1/1            assign data_packet_received =
           Tests:       T1 T2 T3 
153                         rx_pkt_end_i &&
154                         rx_pkt_valid_i &&
155                         ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1));
156                     
157        1/1            assign non_data_packet_received =
           Tests:       T1 T2 T3 
158                         rx_pkt_end_i &&
159                         rx_pkt_valid_i &&
160                         !((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1));
161                     
162                       // Is the specified endpoint actually implemented in hardware?
163        1/1            assign ep_in_hw = {1'b0, rx_endp_i} < NumOutEps;
           Tests:       T1 T2 T3 
164        1/1            assign out_ep_current_d = ep_in_hw ? rx_endp_i : '0;
           Tests:       T1 T2 T3 
165                     
166                       // Make widths work - out_ep_current_d/out_ep_current_o only hold implemented endpoint IDs.
167                       // These signals can be used to index signals of NumOutEps width.
168                       // They are only valid if ep_in_hw is set, i.e., if the specified endpoint is implemented.
169                       logic [OutEpW-1:0] out_ep_index;
170                       logic [OutEpW-1:0] out_ep_index_d;
171        1/1            assign out_ep_index   = out_ep_current_o[0 +: OutEpW];
           Tests:       T1 T2 T3 
172        1/1            assign out_ep_index_d = out_ep_current_d[0 +: OutEpW];
           Tests:       T1 T2 T3 
173                     
174                       // Is the endpoint active?
175        1/1            assign ep_active = out_ep_enabled_i[out_ep_index_d] & ep_in_hw;
           Tests:       T1 T2 T3 
176        1/1            assign ep_is_control = out_ep_control_i[out_ep_index_d];
           Tests:       T1 T2 T3 
177                     
178        1/1            assign bad_data_toggle =
           Tests:       T1 T2 T3 
179                         data_packet_received &&
180                         ep_active &&
181                         rx_pid_i[3] != data_toggle_q[out_ep_index_d];
182                     
183                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
184        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
185        1/1                out_ep_setup_o <= '0;
           Tests:       T1 T2 T3 
186                         end else begin
187        1/1                if (setup_token_received && ep_active) begin
           Tests:       T1 T2 T3 
188        1/1                  out_ep_setup_o[out_ep_index_d] <= 1'b1;
           Tests:       T2 T24 T82 
189        1/1                end else if (out_token_received && ep_active) begin
           Tests:       T1 T2 T3 
190        1/1                  out_ep_setup_o[out_ep_index_d] <= 1'b0;
           Tests:       T1 T18 T19 
191                           end
                        MISSING_ELSE
192                         end
193                       end
194                     
195                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
196        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
197        1/1                out_ep_data_o <= 0;
           Tests:       T1 T2 T3 
198                         end else begin
199        1/1                if (rx_data_put_i) begin
           Tests:       T1 T2 T3 
200        1/1                  out_ep_data_o <= rx_data_i;
           Tests:       T1 T2 T17 
201                           end
                        MISSING_ELSE
202                         end
203                       end
204                     
205                       ///////////////////////////////////
206                       // out transaction state machine //
207                       ///////////////////////////////////
208                     
209                       logic [AckTimeoutCntW-1:0] timeout_cntdown_d, timeout_cntdown_q;
210                     
211                       always_comb begin
212        1/1              out_ep_acked_o = 1'b0;
           Tests:       T1 T2 T3 
213        1/1              out_xact_start = 1'b0;
           Tests:       T1 T2 T3 
214        1/1              out_xact_state_next = out_xact_state;
           Tests:       T1 T2 T3 
215        1/1              tx_pkt_start_o = 1'b0;
           Tests:       T1 T2 T3 
216        1/1              tx_pid_o = 4'b0000;
           Tests:       T1 T2 T3 
217        1/1              new_pkt_end = 1'b0;
           Tests:       T1 T2 T3 
218        1/1              rollback_data = 1'b0;
           Tests:       T1 T2 T3 
219        1/1              timeout_cntdown_d = AckTimeoutCnt[AckTimeoutCntW-1:0];
           Tests:       T1 T2 T3 
220                     
221        1/1              unique case (out_xact_state)
           Tests:       T1 T2 T3 
222                           StIdle: begin
223                             // For unimplemented EPs, transactions are ignored.
224                             // SETUP transactions are also ignored for non-control EPs.
225        1/1                  if (ep_active && (out_token_received || (setup_token_received && ep_is_control))) begin
           Tests:       T1 T2 T3 
226        1/1                    out_xact_state_next = StRcvdOut;
           Tests:       T1 T2 T18 
227        1/1                    out_xact_start = 1'b1;
           Tests:       T1 T2 T18 
228                             end else begin
229        1/1                    out_xact_state_next = StIdle;
           Tests:       T1 T2 T3 
230                             end
231                           end
232                     
233                           StRcvdOut: begin
234                             // The spec says we have up to 18 bit times to wait for the host's
235                             // data packet. If it doesn't arrive in time, we must invalidate the
236                             // transaction.
237        1/1                  timeout_cntdown_d = timeout_cntdown_q - 1'b1;
           Tests:       T1 T2 T18 
238                     
239        1/1                  if (rx_pkt_start_i) begin
           Tests:       T1 T2 T18 
240        1/1                    out_xact_state_next = StRcvdDataStart;
           Tests:       T1 T2 T18 
241        1/1                  end else if (timeout_cntdown_q == '0) begin
           Tests:       T1 T2 T18 
242        0/1     ==>            out_xact_state_next = StIdle;
243                             end else begin
244        1/1                    out_xact_state_next = StRcvdOut;
           Tests:       T1 T2 T18 
245                             end
246                           end
247                     
248                           StRcvdDataStart: begin
249        1/1                  if (!ep_is_control && out_ep_iso_i[out_ep_index] && data_packet_received) begin
           Tests:       T1 T2 T18 
250                               // ISO EP: Don't send a handshake, ignore toggle.
251                               // But ignore iso bit for endpoints marked control. This is
252                               // a configuration error.
253        1/1                    out_xact_state_next = StRcvdIsoDataEnd;
           Tests:       T24 T81 T6 
254        1/1                  end else if (bad_data_toggle && !out_ep_stall_i[out_ep_index]) begin
           Tests:       T1 T2 T18 
255                               // The DATA toggle was wrong (skipped when this EP is stalled)
256                               // Note: bad_data_toggle is meaningless for unimplemented EPs.
257        1/1                    out_xact_state_next = StIdle;
           Tests:       T19 T30 T66 
258        1/1                    rollback_data = 1'b1;
           Tests:       T19 T30 T66 
259        1/1                    tx_pkt_start_o = 1'b1;
           Tests:       T19 T30 T66 
260        1/1                    tx_pid_o = {UsbPidAck}; // ACK by spec because this is most likely previous ACK was lost
           Tests:       T19 T30 T66 
261        1/1                  end else if (invalid_packet_received || non_data_packet_received) begin
           Tests:       T1 T2 T18 
262                               // in these cases eg bad CRC, send no response (not a NAK)
263        1/1                    out_xact_state_next = StIdle;
           Tests:       T30 T66 T67 
264        1/1                    rollback_data = 1'b1;
           Tests:       T30 T66 T67 
265        1/1                  end else if (data_packet_received) begin
           Tests:       T1 T2 T18 
266        1/1                    out_xact_state_next = StRcvdDataEnd;
           Tests:       T1 T2 T18 
267                             end else begin
268        1/1                    out_xact_state_next = StRcvdDataStart;
           Tests:       T1 T2 T18 
269                             end
270                           end
271                     
272                           StRcvdDataEnd: begin
273        1/1                  out_xact_state_next = StIdle;
           Tests:       T1 T2 T18 
274        1/1                  tx_pkt_start_o = 1'b1;
           Tests:       T1 T2 T18 
275                     
276        1/1                  if (current_xact_setup_q) begin
           Tests:       T1 T2 T18 
277                               // SETUP transactions end here
278        1/1                    if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
           Tests:       T2 T24 T82 
279                                 // SETUP transactions that fail to be received are dropped without a response.
280        1/1                      tx_pkt_start_o = 1'b0;
           Tests:       T178 T179 T180 
281        1/1                      rollback_data = 1'b1;
           Tests:       T178 T179 T180 
282                               end else begin
283        1/1                      tx_pid_o = {UsbPidAck};
           Tests:       T2 T24 T82 
284        1/1                      new_pkt_end = 1'b1;
           Tests:       T2 T24 T82 
285        1/1                      out_ep_acked_o = 1'b1;
           Tests:       T2 T24 T82 
286                               end
287                             end else begin
288                               // Non-isochronous OUT transactions end here
289        1/1                    if (out_ep_stall_i[out_ep_index]) begin
           Tests:       T1 T18 T19 
290        1/1                      tx_pid_o = {UsbPidStall}; // STALL
           Tests:       T155 T103 T181 
291        1/1                      rollback_data = 1'b1; // Packet not accepted
           Tests:       T155 T103 T181 
292        1/1                    end else if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
           Tests:       T1 T18 T19 
293        1/1                      tx_pid_o = {UsbPidNak}; // NAK -- the endpoint could not accept the data at the moment
           Tests:       T30 T66 T68 
294        1/1                      rollback_data = 1'b1;
           Tests:       T30 T66 T68 
295                               end else begin
296        1/1                      tx_pid_o = {UsbPidAck}; // ACK
           Tests:       T1 T18 T19 
297        1/1                      new_pkt_end = 1'b1;
           Tests:       T1 T18 T19 
298        1/1                      out_ep_acked_o = 1'b1;
           Tests:       T1 T18 T19 
299                               end
300                             end
301                           end
302                     
303                           StRcvdIsoDataEnd: begin
304                             // Isochronous OUT transactions end here
305        1/1                  out_xact_state_next = StIdle;
           Tests:       T24 T81 T6 
306                     
307        1/1                  if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
           Tests:       T24 T81 T6 
308                               // We got a valid packet, but can't store it (error that the software must resolve)
309        1/1                    rollback_data = 1'b1;
           Tests:       T24 T51 T182 
310                             end else begin
311                               // We got a valid packet, but we don't send an ACK on the bus
312        1/1                    new_pkt_end    = 1'b1;
           Tests:       T81 T6 T183 
313        1/1                    out_ep_acked_o = 1'b1;
           Tests:       T81 T6 T183 
314                             end
315                           end
316                     
317                           default: out_xact_state_next = StIdle;
Exclude Annotation: VC_COV_UNR
318                         endcase
319                       end
320                     
321                       `ASSERT(OutXactStateValid_A,
322                         out_xact_state inside {StIdle, StRcvdOut, StRcvdDataStart, StRcvdDataEnd, StRcvdIsoDataEnd},
323                         clk_48mhz_i)
324                     
325                       // could flop this if needed
326        1/1            assign out_ep_rollback_o = rollback_data;
           Tests:       T1 T2 T3 
327                     
328                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
329        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
330        1/1                timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
           Tests:       T1 T2 T3 
331                         end else begin
332        1/1                timeout_cntdown_q <= timeout_cntdown_d;
           Tests:       T1 T2 T3 
333                         end
334                       end
335                     
336                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
337        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
338        1/1                out_xact_state <= StIdle;
           Tests:       T1 T2 T3 
339                         end else begin
340        1/1                out_xact_state <= link_reset_i ? StIdle : out_xact_state_next;
           Tests:       T1 T2 T3 
341                         end
342                       end
343                     
344                       // Updating of data toggles
345                       always_comb begin : proc_data_toggle_d
346        1/1              data_toggle_d = data_toggle_q;
           Tests:       T1 T2 T3 
347                     
348        1/1              if (setup_token_received && ep_active) begin
           Tests:       T1 T2 T3 
349        1/1                data_toggle_d[out_ep_index_d] = 1'b0;
           Tests:       T2 T24 T82 
350        1/1              end else if (new_pkt_end) begin
           Tests:       T1 T2 T3 
351        1/1                data_toggle_d[out_ep_index] = ~data_toggle_q[out_ep_index];
           Tests:       T1 T2 T18 
352                         end
                        MISSING_ELSE
353                         // Selective modification by software
354        1/1              if (out_datatog_we_i) begin
           Tests:       T1 T2 T3 
355        1/1                data_toggle_d = (data_toggle_d & ~out_datatog_mask_i) |
           Tests:       T18 T19 T30 
356                                           (out_datatog_status_i & out_datatog_mask_i);
357                         end
                        MISSING_ELSE
358                       end
359                       // Supply current data toggles to register interface
360        1/1            assign out_data_toggle_o = data_toggle_q;
           Tests:       T1 T2 T3 
361                     
362                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
363        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
364        1/1                data_toggle_q <= '0; // Clear for all endpoints
           Tests:       T1 T2 T3 
365        1/1              end else if (link_reset_i) begin
           Tests:       T1 T2 T3 
366        1/1                data_toggle_q <= '0; // Clear for all endpoints
           Tests:       T1 T2 T3 
367                         end else begin
368        1/1                data_toggle_q <= data_toggle_d;
           Tests:       T1 T2 T3 
369                         end
370                       end
371                     
372                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
373        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
374        1/1                out_ep_newpkt_o       <= 1'b0;
           Tests:       T1 T2 T3 
375        1/1                out_ep_current_o      <= '0;
           Tests:       T1 T2 T3 
376        1/1                current_xact_setup_q  <= 1'b0;
           Tests:       T1 T2 T3 
377                         end else begin
378        1/1                if (out_xact_start) begin
           Tests:       T1 T2 T3 
379        1/1                  out_ep_newpkt_o      <= 1'b1;
           Tests:       T1 T2 T18 
380        1/1                  out_ep_current_o     <= out_ep_current_d;
           Tests:       T1 T2 T18 
381        1/1                  current_xact_setup_q <= setup_token_received;
           Tests:       T1 T2 T18 
382                           end else begin
383        1/1                  out_ep_newpkt_o <= 1'b0;
           Tests:       T1 T2 T3 
384                           end
385                         end
386                       end
387                     
388                       // put data strobe follows the rx strobe (which will latch the data)
389                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
390        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
391        1/1                out_ep_data_put_o <= 1'b0;
           Tests:       T1 T2 T3 
392                         end else begin
393        1/1                out_ep_data_put_o <= ((out_xact_state == StRcvdDataStart) && rx_data_put_i);
           Tests:       T1 T2 T3 
394                         end
395                       end
396                     
397                       // nak an OUT if any data comes in with the endpoint full
398                       // Note that if there is a full size packet buffer this will only be all or nothing
399                       // but in the case there was a FIFO with less than a max packet size free you
400                       // could get lucky and the packet received be small and fit with no need to NAK
401                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
402        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
403        1/1                nak_out_transaction <= 1'b0;
           Tests:       T1 T2 T3 
404                         end else begin
405        1/1                if ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut)) begin
           Tests:       T1 T2 T3 
406        1/1                  nak_out_transaction <= 1'b0;
           Tests:       T1 T2 T3 
407        1/1                end else if (out_ep_data_put_o && out_ep_full_i[out_ep_index]) begin
           Tests:       T1 T2 T18 
408        1/1                  nak_out_transaction <= 1'b1;
           Tests:       T24 T30 T66 
409                           end
                        MISSING_ELSE
410                         end
411                       end
412                     
413                       // address increment whenever there is a data put unless
414                       // -- already going to NAK transaction and replay things
415                       // -- the address is at max packet size
416                       // NOTE if more than max packet size received then data is lost
417                       logic increment_addr;
418        1/1            assign increment_addr = !nak_out_transaction && (~&out_ep_put_addr_o) && out_ep_data_put_o;
           Tests:       T1 T2 T3 
419                     
420                       always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
421        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
422        1/1                out_ep_put_addr_o <= '0;
           Tests:       T1 T2 T3 
423                         end else begin
424        1/1                if (out_xact_state == StRcvdOut) begin
           Tests:       T1 T2 T3 
425        1/1                  out_ep_put_addr_o <= '0;
           Tests:       T1 T2 T18 
426        1/1                end else if ((out_xact_state == StRcvdDataStart) && increment_addr) begin
           Tests:       T1 T2 T3 
427        1/1                  out_ep_put_addr_o <= out_ep_put_addr_o + 1;
           Tests:       T1 T2 T18 
428                           end
                        MISSING_ELSE
429                         end
430                       end
431                     
432                       ///////////////////////////////////////////////////////////////////////////////////////////////
433                       // Count OUT transactions that have been ACKed and dropped because of unexpected Data Toggles.
434                       ///////////////////////////////////////////////////////////////////////////////////////////////
435        1/1            assign event_datatog_out_o = (out_xact_state == StRcvdDataStart) &&
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

	Total	Covered	Percent
Conditions	134	124	92.54
Logical	134	124	92.54
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T18
1	0	1	1	Covered	T69,T107,T73
1	1	0	1	Covered	T1,T2,T18
1	1	1	0	Covered	T20,T21,T23
1	1	1	1	Covered	T1,T2,T18

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T2,T18,T19
1	1	Covered	T1,T18,T19

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Covered	T1,T18,T19
1	1	Covered	T2,T20,T24

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T17,T20,T23

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T30,T66,T67
1	1	0	Covered	T1,T2,T18
1	1	1	Covered	T1,T2,T17

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T18,T19
1	0	Covered	T1,T2,T17

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T18,T19

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T17,T20,T23
1	1	0	Covered	T1,T2,T17
1	1	1	Covered	T1,T2,T18

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T18,T19
1	0	Covered	T1,T2,T17

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T18,T19

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---

-1-	Status	Tests
0	Covered	T21,T8,T112
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T113,T74,T140
1	1	Covered	T1,T2,T18

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T74,T115,T76
1	1	0	Covered	T1,T2,T18
1	1	1	Covered	T19,T30,T66

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T20,T74,T114
1	1	Covered	T2,T24,T82

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T41,T4,T74
1	1	Covered	T1,T18,T19

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T41,T4
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T24
1	0	Covered	T1,T18,T19

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Covered	T184,T185,T114
1	1	Covered	T2,T20,T24

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Not Covered

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T186,T187,T188
1	0	1	Covered	T1,T18,T19
1	1	0	Covered	T24,T81,T6
1	1	1	Covered	T24,T81,T6

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Not Covered
1	1	Covered	T19,T30,T66

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T74,T76,T77
1	0	Covered	T30,T66,T67

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T24,T82
0	1	Not Covered
1	0	Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T19
0	1	Not Covered
1	0	Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T81,T6,T183
0	1	Not Covered
1	0	Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T20,T74,T114
1	1	Covered	T2,T24,T82

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T20,T23
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T66
1	0	Covered	T1,T2,T18
1	1	Covered	T24,T30,T66

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T30,T66
1	0	1	Covered	T117,T80,T67
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T18

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T18

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T114,T115,T76
1	0	1	1	Covered	T6,T174,T186
1	1	0	1	Not Covered
1	1	1	0	Covered	T1,T2,T18
1	1	1	1	Covered	T19,T30,T66

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T81,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T174,T189

---

FSM Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Summary for FSM :: out_xact_state

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	7	87.50
Sequences	0	0

State, Transition and Sequence Details for FSM :: out_xact_state

---

states	Line No.	Covered	Tests
StIdle	340	Covered	T1,T2,T3
StRcvdDataEnd	266	Covered	T1,T2,T18
StRcvdDataStart	240	Covered	T1,T2,T18
StRcvdIsoDataEnd	253	Covered	T24,T81,T6
StRcvdOut	226	Covered	T1,T2,T18

transitions	Line No.	Covered	Tests
StIdle->StRcvdOut	226	Covered	T1,T2,T18
StRcvdDataEnd->StIdle	340	Covered	T1,T2,T18
StRcvdDataStart->StIdle	340	Covered	T19,T30,T66
StRcvdDataStart->StRcvdDataEnd	266	Covered	T1,T2,T18
StRcvdDataStart->StRcvdIsoDataEnd	253	Covered	T24,T81,T6
StRcvdIsoDataEnd->StIdle	340	Covered	T24,T81,T6
StRcvdOut->StIdle	340	Not Covered
StRcvdOut->StRcvdDataStart	240	Covered	T1,T2,T18

---

Branch Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
Branches		52	51	98.08
TERNARY	164	2	2	100.00
IF	184	4	4	100.00
IF	196	3	3	100.00
CASE	221	17	16	94.12
IF	329	2	2	100.00
IF	337	3	3	100.00
IF	348	3	3	100.00
IF	354	2	2	100.00
IF	363	3	3	100.00
IF	373	3	3	100.00
IF	390	2	2	100.00
IF	402	4	4	100.00
IF	421	4	4	100.00

164          assign out_ep_current_d = ep_in_hw ? rx_endp_i : '0;
                                                -1-  
                                                ==>  
                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T8,T112

184            if (!rst_ni) begin
               -1-  
185              out_ep_setup_o <= '0;
                 ==>
186            end else begin
187              if (setup_token_received && ep_active) begin
                 -2-  
188                out_ep_setup_o[out_ep_index_d] <= 1'b1;
                   ==>
189              end else if (out_token_received && ep_active) begin
                          -3-  
190                out_ep_setup_o[out_ep_index_d] <= 1'b0;
                   ==>
191              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T24,T82
0	0	1	Covered	T1,T18,T19
0	0	0	Covered	T1,T2,T3

196            if (!rst_ni) begin
               -1-  
197              out_ep_data_o <= 0;
                 ==>
198            end else begin
199              if (rx_data_put_i) begin
                 -2-  
200                out_ep_data_o <= rx_data_i;
                   ==>
201              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

221            unique case (out_xact_state)
                      -1-  
222              StIdle: begin
223                // For unimplemented EPs, transactions are ignored.
224                // SETUP transactions are also ignored for non-control EPs.
225                if (ep_active && (out_token_received || (setup_token_received && ep_is_control))) begin
                   -2-  
226                  out_xact_state_next = StRcvdOut;
                     ==>
227                  out_xact_start = 1'b1;
228                end else begin
229                  out_xact_state_next = StIdle;
                     ==>
230                end
231              end
232        
233              StRcvdOut: begin
234                // The spec says we have up to 18 bit times to wait for the host's
235                // data packet. If it doesn't arrive in time, we must invalidate the
236                // transaction.
237                timeout_cntdown_d = timeout_cntdown_q - 1'b1;
238        
239                if (rx_pkt_start_i) begin
                   -3-  
240                  out_xact_state_next = StRcvdDataStart;
                     ==>
241                end else if (timeout_cntdown_q == '0) begin
                            -4-  
242                  out_xact_state_next = StIdle;
                     ==>
243                end else begin
244                  out_xact_state_next = StRcvdOut;
                     ==>
245                end
246              end
247        
248              StRcvdDataStart: begin
249                if (!ep_is_control && out_ep_iso_i[out_ep_index] && data_packet_received) begin
                   -5-  
250                  // ISO EP: Don't send a handshake, ignore toggle.
251                  // But ignore iso bit for endpoints marked control. This is
252                  // a configuration error.
253                  out_xact_state_next = StRcvdIsoDataEnd;
                     ==>
254                end else if (bad_data_toggle && !out_ep_stall_i[out_ep_index]) begin
                            -6-  
255                  // The DATA toggle was wrong (skipped when this EP is stalled)
256                  // Note: bad_data_toggle is meaningless for unimplemented EPs.
257                  out_xact_state_next = StIdle;
                     ==>
258                  rollback_data = 1'b1;
259                  tx_pkt_start_o = 1'b1;
260                  tx_pid_o = {UsbPidAck}; // ACK by spec because this is most likely previous ACK was lost
261                end else if (invalid_packet_received || non_data_packet_received) begin
                            -7-  
262                  // in these cases eg bad CRC, send no response (not a NAK)
263                  out_xact_state_next = StIdle;
                     ==>
264                  rollback_data = 1'b1;
265                end else if (data_packet_received) begin
                            -8-  
266                  out_xact_state_next = StRcvdDataEnd;
                     ==>
267                end else begin
268                  out_xact_state_next = StRcvdDataStart;
                     ==>
269                end
270              end
271        
272              StRcvdDataEnd: begin
273                out_xact_state_next = StIdle;
274                tx_pkt_start_o = 1'b1;
275        
276                if (current_xact_setup_q) begin
                   -9-  
277                  // SETUP transactions end here
278                  if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
                     -10-  
279                    // SETUP transactions that fail to be received are dropped without a response.
280                    tx_pkt_start_o = 1'b0;
                       ==>
281                    rollback_data = 1'b1;
282                  end else begin
283                    tx_pid_o = {UsbPidAck};
                       ==>
284                    new_pkt_end = 1'b1;
285                    out_ep_acked_o = 1'b1;
286                  end
287                end else begin
288                  // Non-isochronous OUT transactions end here
289                  if (out_ep_stall_i[out_ep_index]) begin
                     -11-  
290                    tx_pid_o = {UsbPidStall}; // STALL
                       ==>
291                    rollback_data = 1'b1; // Packet not accepted
292                  end else if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
                              -12-  
293                    tx_pid_o = {UsbPidNak}; // NAK -- the endpoint could not accept the data at the moment
                       ==>
294                    rollback_data = 1'b1;
295                  end else begin
296                    tx_pid_o = {UsbPidAck}; // ACK
                       ==>
297                    new_pkt_end = 1'b1;
298                    out_ep_acked_o = 1'b1;
299                  end
300                end
301              end
302        
303              StRcvdIsoDataEnd: begin
304                // Isochronous OUT transactions end here
305                out_xact_state_next = StIdle;
306        
307                if (nak_out_transaction | out_ep_full_i[out_ep_index]) begin
                   -13-  
308                  // We got a valid packet, but can't store it (error that the software must resolve)
309                  rollback_data = 1'b1;
                     ==>
310                end else begin
311                  // We got a valid packet, but we don't send an ACK on the bus
312                  new_pkt_end    = 1'b1;
                     ==>
313                  out_ep_acked_o = 1'b1;
314                end
315              end
316        
317              default: out_xact_state_next = StIdle;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests	Exclude Annotation
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRcvdOut	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
StRcvdOut	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdOut	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
StRcvdDataStart	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T81,T6
StRcvdDataStart	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T19,T30,T66
StRcvdDataStart	-	-	-	0	0	1	-	-	-	-	-	-	Covered	T30,T66,T67
StRcvdDataStart	-	-	-	0	0	0	1	-	-	-	-	-	Covered	T1,T2,T18
StRcvdDataStart	-	-	-	0	0	0	0	-	-	-	-	-	Covered	T1,T2,T18
StRcvdDataEnd	-	-	-	-	-	-	-	1	1	-	-	-	Covered	T178,T179,T180
StRcvdDataEnd	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T2,T24,T82
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	1	-	-	Covered	T155,T103,T181
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	1	-	Covered	T30,T66,T68
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	0	-	Covered	T1,T18,T19
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T24,T51,T182
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T81,T6,T183
default	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

329            if (!rst_ni) begin
               -1-  
330              timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
                 ==>
331            end else begin
332              timeout_cntdown_q <= timeout_cntdown_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

337            if (!rst_ni) begin
               -1-  
338              out_xact_state <= StIdle;
                 ==>
339            end else begin
340              out_xact_state <= link_reset_i ? StIdle : out_xact_state_next;
                                                -2-  
                                                ==>  
                                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

348            if (setup_token_received && ep_active) begin
               -1-  
349              data_toggle_d[out_ep_index_d] = 1'b0;
                 ==>
350            end else if (new_pkt_end) begin
                        -2-  
351              data_toggle_d[out_ep_index] = ~data_toggle_q[out_ep_index];
                 ==>
352            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T24,T82
0	1	Covered	T1,T2,T18
0	0	Covered	T1,T2,T3

354            if (out_datatog_we_i) begin
               -1-  
355              data_toggle_d = (data_toggle_d & ~out_datatog_mask_i) |
                 ==>
356                              (out_datatog_status_i & out_datatog_mask_i);
357            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T30
0	Covered	T1,T2,T3

363            if (!rst_ni) begin
               -1-  
364              data_toggle_q <= '0; // Clear for all endpoints
                 ==>
365            end else if (link_reset_i) begin
                        -2-  
366              data_toggle_q <= '0; // Clear for all endpoints
                 ==>
367            end else begin
368              data_toggle_q <= data_toggle_d;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

373            if (!rst_ni) begin
               -1-  
374              out_ep_newpkt_o       <= 1'b0;
                 ==>
375              out_ep_current_o      <= '0;
376              current_xact_setup_q  <= 1'b0;
377            end else begin
378              if (out_xact_start) begin
                 -2-  
379                out_ep_newpkt_o      <= 1'b1;
                   ==>
380                out_ep_current_o     <= out_ep_current_d;
381                current_xact_setup_q <= setup_token_received;
382              end else begin
383                out_ep_newpkt_o <= 1'b0;
                   ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T18
0	0	Covered	T1,T2,T3

390            if (!rst_ni) begin
               -1-  
391              out_ep_data_put_o <= 1'b0;
                 ==>
392            end else begin
393              out_ep_data_put_o <= ((out_xact_state == StRcvdDataStart) && rx_data_put_i);
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

402            if (!rst_ni) begin
               -1-  
403              nak_out_transaction <= 1'b0;
                 ==>
404            end else begin
405              if ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut)) begin
                 -2-  
406                nak_out_transaction <= 1'b0;
                   ==>
407              end else if (out_ep_data_put_o && out_ep_full_i[out_ep_index]) begin
                          -3-  
408                nak_out_transaction <= 1'b1;
                   ==>
409              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T24,T30,T66
0	0	0	Covered	T1,T2,T18

421            if (!rst_ni) begin
               -1-  
422              out_ep_put_addr_o <= '0;
                 ==>
423            end else begin
424              if (out_xact_state == StRcvdOut) begin
                 -2-  
425                out_ep_put_addr_o <= '0;
                   ==>
426              end else if ((out_xact_state == StRcvdDataStart) && increment_addr) begin
                          -3-  
427                out_ep_put_addr_o <= out_ep_put_addr_o + 1;
                   ==>
428              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T18
0	0	1	Covered	T1,T2,T18
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutXactStateValid_A	578377389	578088936	0	0

OutXactStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	578377389	578088936	0	0
T1	9647	9557	0	0
T2	8147	8076	0	0
T3	7219	7156	0	0
T7	279126	279033	0	0
T17	9642	9576	0	0
T18	23955	23883	0	0
T19	44812	44731	0	0
T20	27564	27485	0	0
T21	10864	10805	0	0
T22	1813	1750	0	0