Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	117162	1		T2	4		T3	2		T4	2
all_values[1]	117162	1		T2	4		T3	2		T4	2
all_values[2]	117162	1		T2	4		T3	2		T4	2
all_values[3]	117162	1		T2	4		T3	2		T4	2
all_values[4]	117162	1		T2	4		T3	2		T4	2
all_values[5]	117162	1		T2	4		T3	2		T4	2
all_values[6]	117162	1		T2	4		T3	2		T4	2
all_values[7]	117162	1		T2	4		T3	2		T4	2
all_values[8]	117162	1		T2	4		T3	2		T4	2
all_values[9]	117162	1		T2	4		T3	2		T4	2
all_values[10]	117162	1		T2	4		T3	2		T4	2
all_values[11]	117162	1		T2	4		T3	2		T4	2
all_values[12]	117162	1		T2	4		T3	2		T4	2
all_values[13]	117162	1		T2	4		T3	2		T4	2
all_values[14]	117162	1		T2	4		T3	2		T4	2
all_values[15]	117162	1		T2	4		T3	2		T4	2
all_values[16]	117162	1		T2	4		T3	2		T4	2
all_values[17]	117162	1		T2	4		T3	2		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2104056	1		T2	72		T3	36		T4	36
auto[1]	4860	1		T5	4		T19	3		T34	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2104130	1		T2	72		T3	36		T4	36
auto[1]	4786	1		T82	72		T79	134		T81	64

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	116169	1		T2	4		T3	2		T4	2
all_values[0]	auto[0]	auto[1]	119	1		T79	2		T81	2		T83	4
all_values[0]	auto[1]	auto[0]	718	1		T19	3		T75	4		T76	4
all_values[0]	auto[1]	auto[1]	156	1		T82	3		T79	6		T81	3
all_values[1]	auto[0]	auto[0]	115820	1		T2	4		T3	2		T4	2
all_values[1]	auto[0]	auto[1]	147	1		T82	4		T79	6		T84	2
all_values[1]	auto[1]	auto[0]	1081	1		T5	4		T77	3		T78	3
all_values[1]	auto[1]	auto[1]	114	1		T82	1		T79	2		T84	3
all_values[2]	auto[0]	auto[0]	116767	1		T2	4		T3	2		T4	2
all_values[2]	auto[0]	auto[1]	125	1		T82	1		T79	4		T81	3
all_values[2]	auto[1]	auto[0]	136	1		T8	2		T9	2		T11	2
all_values[2]	auto[1]	auto[1]	134	1		T82	4		T79	4		T83	5
all_values[3]	auto[0]	auto[0]	116858	1		T2	4		T3	2		T4	2
all_values[3]	auto[0]	auto[1]	150	1		T82	1		T79	1		T81	3
all_values[3]	auto[1]	auto[0]	17	1		T79	2		T81	1		T83	1
all_values[3]	auto[1]	auto[1]	137	1		T82	4		T79	4		T83	2
all_values[4]	auto[0]	auto[0]	116880	1		T2	4		T3	2		T4	2
all_values[4]	auto[0]	auto[1]	126	1		T82	4		T79	5		T81	1
all_values[4]	auto[1]	auto[0]	31	1		T84	4		T280	1		T281	5
all_values[4]	auto[1]	auto[1]	125	1		T82	1		T79	3		T81	3
all_values[5]	auto[0]	auto[0]	116869	1		T2	4		T3	2		T4	2
all_values[5]	auto[0]	auto[1]	135	1		T79	5		T81	3		T84	4
all_values[5]	auto[1]	auto[0]	25	1		T84	1		T83	2		T282	4
all_values[5]	auto[1]	auto[1]	133	1		T82	5		T79	2		T81	1
all_values[6]	auto[0]	auto[0]	116871	1		T2	4		T3	2		T4	2
all_values[6]	auto[0]	auto[1]	103	1		T82	3		T79	2		T81	3
all_values[6]	auto[1]	auto[0]	37	1		T79	1		T81	1		T83	3
all_values[6]	auto[1]	auto[1]	151	1		T82	1		T79	5		T84	1
all_values[7]	auto[0]	auto[0]	116866	1		T2	4		T3	2		T4	2
all_values[7]	auto[0]	auto[1]	138	1		T82	4		T79	2		T83	2
all_values[7]	auto[1]	auto[0]	15	1		T82	1		T84	5		T281	1
all_values[7]	auto[1]	auto[1]	143	1		T79	6		T81	3		T83	5
all_values[8]	auto[0]	auto[0]	116868	1		T2	4		T3	2		T4	2
all_values[8]	auto[0]	auto[1]	126	1		T79	6		T81	3		T84	4
all_values[8]	auto[1]	auto[0]	26	1		T82	1		T84	1		T281	1
all_values[8]	auto[1]	auto[1]	142	1		T79	2		T81	2		T83	2
all_values[9]	auto[0]	auto[0]	116863	1		T2	4		T3	2		T4	2
all_values[9]	auto[0]	auto[1]	142	1		T79	5		T84	3		T83	3
all_values[9]	auto[1]	auto[0]	29	1		T81	1		T84	1		T83	1
all_values[9]	auto[1]	auto[1]	128	1		T82	4		T79	3		T81	4
all_values[10]	auto[0]	auto[0]	116869	1		T2	4		T3	2		T4	2
all_values[10]	auto[0]	auto[1]	143	1		T82	5		T79	5		T81	3
all_values[10]	auto[1]	auto[0]	18	1		T79	1		T284	2		T285	1
all_values[10]	auto[1]	auto[1]	132	1		T79	1		T81	2		T84	4
all_values[11]	auto[0]	auto[0]	116775	1		T2	4		T3	2		T4	2
all_values[11]	auto[0]	auto[1]	147	1		T79	3		T84	4		T83	6
all_values[11]	auto[1]	auto[0]	124	1		T34	2		T35	2		T36	2
all_values[11]	auto[1]	auto[1]	116	1		T82	3		T79	5		T84	1
all_values[12]	auto[0]	auto[0]	116873	1		T2	4		T3	2		T4	2
all_values[12]	auto[0]	auto[1]	117	1		T79	4		T81	3		T83	5
all_values[12]	auto[1]	auto[0]	27	1		T82	3		T79	1		T84	1
all_values[12]	auto[1]	auto[1]	145	1		T79	3		T81	1		T84	4
all_values[13]	auto[0]	auto[0]	116877	1		T2	4		T3	2		T4	2
all_values[13]	auto[0]	auto[1]	113	1		T82	1		T79	4		T81	4
all_values[13]	auto[1]	auto[0]	34	1		T79	1		T84	1		T83	1
all_values[13]	auto[1]	auto[1]	138	1		T82	4		T79	3		T81	1
all_values[14]	auto[0]	auto[0]	116860	1		T2	4		T3	2		T4	2
all_values[14]	auto[0]	auto[1]	159	1		T82	1		T79	3		T81	4
all_values[14]	auto[1]	auto[0]	20	1		T84	1		T83	2		T282	1
all_values[14]	auto[1]	auto[1]	123	1		T82	4		T79	5		T84	4
all_values[15]	auto[0]	auto[0]	116871	1		T2	4		T3	2		T4	2
all_values[15]	auto[0]	auto[1]	119	1		T82	5		T79	3		T84	1
all_values[15]	auto[1]	auto[0]	35	1		T81	1		T280	1		T286	1
all_values[15]	auto[1]	auto[1]	137	1		T79	4		T81	3		T84	4
all_values[16]	auto[0]	auto[0]	116872	1		T2	4		T3	2		T4	2
all_values[16]	auto[0]	auto[1]	118	1		T82	1		T79	6		T81	1
all_values[16]	auto[1]	auto[0]	36	1		T82	1		T84	5		T281	1
all_values[16]	auto[1]	auto[1]	136	1		T82	3		T79	2		T81	3
all_values[17]	auto[0]	auto[0]	116868	1		T2	4		T3	2		T4	2
all_values[17]	auto[0]	auto[1]	133	1		T82	5		T79	3		T81	1
all_values[17]	auto[1]	auto[0]	25	1		T83	1		T280	1		T287	1
all_values[17]	auto[1]	auto[1]	136	1		T79	5		T81	4		T83	6