Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	172056	1			T1	7		T2	4		T3	5
all_values[1]	172056	1			T1	7		T2	4		T3	5
all_values[2]	172056	1			T1	7		T2	4		T3	5
all_values[3]	172056	1			T1	7		T2	4		T3	5
all_values[4]	172056	1			T1	7		T2	4		T3	5
all_values[5]	172056	1			T1	7		T2	4		T3	5
all_values[6]	172056	1			T1	7		T2	4		T3	5
all_values[7]	172056	1			T1	7		T2	4		T3	5
all_values[8]	172056	1			T1	7		T2	4		T3	5
all_values[9]	172056	1			T1	7		T2	4		T3	5
all_values[10]	172056	1			T1	7		T2	4		T3	5
all_values[11]	172056	1			T1	7		T2	4		T3	5
all_values[12]	172056	1			T1	7		T2	4		T3	5
all_values[13]	172056	1			T1	7		T2	4		T3	5
all_values[14]	172056	1			T1	7		T2	4		T3	5
all_values[15]	172056	1			T1	7		T2	4		T3	5
all_values[16]	172056	1			T1	7		T2	4		T3	5
all_values[17]	172056	1			T1	7		T2	4		T3	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5495874

1

T1

219

T2

128

T3

158

auto[1]

9918

1

T1

5

T3

2

T34

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4717470

1

T1

210

T2

110

T3

146

auto[1]

788322

1

T1

14

T2

18

T3

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	143266	1			T1	7		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	25488	1			T2	1		T3	2		T20	1
all_values[0]	auto[1]	auto[0]	3194	1			T46	3		T47	3		T48	3
all_values[0]	auto[1]	auto[1]	108	1			T85	1		T337	1		T338	1
all_values[1]	auto[0]	auto[0]	167618	1			T1	7		T2	4		T3	5
all_values[1]	auto[0]	auto[1]	3044	1			T28	2		T30	2		T21	1
all_values[1]	auto[1]	auto[0]	526	1			T17	2		T23	2		T49	1
all_values[1]	auto[1]	auto[1]	868	1			T17	12		T23	1		T49	1
all_values[2]	auto[0]	auto[0]	4236	1			T1	6		T2	1		T3	4
all_values[2]	auto[0]	auto[1]	167575	1			T1	1		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	124	1			T35	1		T63	1		T64	1
all_values[2]	auto[1]	auto[1]	121	1			T35	1		T63	1		T64	1
all_values[3]	auto[0]	auto[0]	170120	1			T1	7		T2	4		T3	5
all_values[3]	auto[0]	auto[1]	286	1			T45	1		T65	1		T66	1
all_values[3]	auto[1]	auto[0]	1589	1			T45	1484		T228	4		T226	1
all_values[3]	auto[1]	auto[1]	61	1			T45	1		T226	2		T227	1
all_values[4]	auto[0]	auto[0]	4204	1			T1	6		T2	1		T3	4
all_values[4]	auto[0]	auto[1]	167679	1			T1	1		T2	3		T3	1
all_values[4]	auto[1]	auto[0]	106	1			T44	1		T228	4		T226	2
all_values[4]	auto[1]	auto[1]	67	1			T44	1		T226	2		T227	1
all_values[5]	auto[0]	auto[0]	171522	1			T1	7		T2	4		T3	5
all_values[5]	auto[0]	auto[1]	351	1			T7	1		T8	1		T49	1
all_values[5]	auto[1]	auto[0]	100	1			T228	1		T226	2		T227	3
all_values[5]	auto[1]	auto[1]	83	1			T226	4		T227	1		T321	5
all_values[6]	auto[0]	auto[0]	171605	1			T1	7		T2	4		T3	5
all_values[6]	auto[0]	auto[1]	218	1			T49	1		T9	1		T66	1
all_values[6]	auto[1]	auto[0]	98	1			T226	1		T227	1		T321	4
all_values[6]	auto[1]	auto[1]	135	1			T67	1		T68	1		T69	1
all_values[7]	auto[0]	auto[0]	115072	1			T1	5		T34	3		T35	2
all_values[7]	auto[0]	auto[1]	56788	1			T1	2		T2	4		T3	3
all_values[7]	auto[1]	auto[0]	131	1			T3	1		T50	1		T51	1
all_values[7]	auto[1]	auto[1]	65	1			T3	1		T50	1		T51	1
all_values[8]	auto[0]	auto[0]	171316	1			T1	7		T2	4		T3	5
all_values[8]	auto[0]	auto[1]	54	1			T226	1		T227	1		T321	2
all_values[8]	auto[1]	auto[0]	611	1			T55	10		T56	10		T57	10
all_values[8]	auto[1]	auto[1]	75	1			T58	1		T59	1		T60	1
all_values[9]	auto[0]	auto[0]	171789	1			T1	2		T2	4		T3	5
all_values[9]	auto[0]	auto[1]	76	1			T228	1		T226	3		T321	4
all_values[9]	auto[1]	auto[0]	104	1			T1	3		T61	3		T62	3
all_values[9]	auto[1]	auto[1]	87	1			T1	2		T61	2		T62	2
all_values[10]	auto[0]	auto[0]	171502	1			T1	7		T2	4		T3	5
all_values[10]	auto[0]	auto[1]	373	1			T30	1		T24	2		T31	1
all_values[10]	auto[1]	auto[0]	112	1			T226	2		T227	2		T321	1
all_values[10]	auto[1]	auto[1]	69	1			T227	2		T321	4		T322	1
all_values[11]	auto[0]	auto[0]	171066	1			T1	7		T2	4		T3	5
all_values[11]	auto[0]	auto[1]	729	1			T34	1		T20	4		T32	4
all_values[11]	auto[1]	auto[0]	147	1			T73	1		T74	1		T75	1
all_values[11]	auto[1]	auto[1]	114	1			T73	1		T74	1		T75	1
all_values[12]	auto[0]	auto[0]	171602	1			T1	7		T2	4		T3	5
all_values[12]	auto[0]	auto[1]	242	1			T79	3		T80	1		T81	1
all_values[12]	auto[1]	auto[0]	138	1			T76	2		T77	2		T78	2
all_values[12]	auto[1]	auto[1]	74	1			T76	1		T77	1		T78	1
all_values[13]	auto[0]	auto[0]	171704	1			T1	7		T2	4		T3	5
all_values[13]	auto[0]	auto[1]	55	1			T80	1		T81	1		T84	1
all_values[13]	auto[1]	auto[0]	173	1			T34	1		T82	1		T83	1
all_values[13]	auto[1]	auto[1]	124	1			T34	1		T82	1		T83	1
all_values[14]	auto[0]	auto[0]	35364	1			T1	7		T2	4		T3	5
all_values[14]	auto[0]	auto[1]	136522	1			T35	1		T7	2		T8	2
all_values[14]	auto[1]	auto[0]	112	1			T228	1		T226	3		T227	1
all_values[14]	auto[1]	auto[1]	58	1			T226	3		T322	1		T325	1
all_values[15]	auto[0]	auto[0]	4261	1			T1	6		T2	1		T3	4
all_values[15]	auto[0]	auto[1]	167621	1			T1	1		T2	3		T3	1
all_values[15]	auto[1]	auto[0]	107	1			T228	1		T226	4		T227	3
all_values[15]	auto[1]	auto[1]	67	1			T226	3		T227	2		T321	1
all_values[16]	auto[0]	auto[0]	171097	1			T1	7		T2	4		T3	5
all_values[16]	auto[0]	auto[1]	778	1			T30	1		T71	1		T72	1
all_values[16]	auto[1]	auto[0]	97	1			T20	4		T32	4		T70	4
all_values[16]	auto[1]	auto[1]	84	1			T20	4		T32	4		T70	4
all_values[17]	auto[0]	auto[0]	113751	1			T36	2		T7	2		T18	2
all_values[17]	auto[0]	auto[1]	58116	1			T1	7		T2	4		T3	5
all_values[17]	auto[1]	auto[0]	122	1			T228	4		T226	5		T227	3
all_values[17]	auto[1]	auto[1]	67	1			T228	1		T226	1		T227	1