Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	171553	1			T1	4		T2	6		T3	7
all_values[1]	171553	1			T1	4		T2	6		T3	7
all_values[2]	171553	1			T1	4		T2	6		T3	7
all_values[3]	171553	1			T1	4		T2	6		T3	7
all_values[4]	171553	1			T1	4		T2	6		T3	7
all_values[5]	171553	1			T1	4		T2	6		T3	7
all_values[6]	171553	1			T1	4		T2	6		T3	7
all_values[7]	171553	1			T1	4		T2	6		T3	7
all_values[8]	171553	1			T1	4		T2	6		T3	7
all_values[9]	171553	1			T1	4		T2	6		T3	7
all_values[10]	171553	1			T1	4		T2	6		T3	7
all_values[11]	171553	1			T1	4		T2	6		T3	7
all_values[12]	171553	1			T1	4		T2	6		T3	7
all_values[13]	171553	1			T1	4		T2	6		T3	7
all_values[14]	171553	1			T1	4		T2	6		T3	7
all_values[15]	171553	1			T1	4		T2	6		T3	7
all_values[16]	171553	1			T1	4		T2	6		T3	7
all_values[17]	171553	1			T1	4		T2	6		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5480219

1

T1

128

T2

189

T3

219

auto[1]

9477

1

T2

3

T3

5

T17

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4704955

1

T1

110

T2

177

T3

210

auto[1]

784741

1

T1

18

T2

15

T3

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142967	1			T1	3		T2	3		T3	7
all_values[0]	auto[0]	auto[1]	25598	1			T1	1		T2	3		T24	2
all_values[0]	auto[1]	auto[0]	2873	1			T43	3		T44	3		T45	3
all_values[0]	auto[1]	auto[1]	115	1			T233	1		T367	1		T368	1
all_values[1]	auto[0]	auto[0]	167300	1			T1	4		T2	6		T3	7
all_values[1]	auto[0]	auto[1]	2836	1			T18	2		T19	2		T31	1
all_values[1]	auto[1]	auto[0]	534	1			T29	2		T33	2		T8	1
all_values[1]	auto[1]	auto[1]	883	1			T29	12		T33	1		T8	1
all_values[2]	auto[0]	auto[0]	4297	1			T1	1		T2	5		T3	6
all_values[2]	auto[0]	auto[1]	166974	1			T1	3		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	160	1			T21	1		T60	1		T61	1
all_values[2]	auto[1]	auto[1]	122	1			T21	1		T60	1		T61	1
all_values[3]	auto[0]	auto[0]	169667	1			T1	4		T2	6		T3	7
all_values[3]	auto[0]	auto[1]	293	1			T41	1		T62	1		T63	1
all_values[3]	auto[1]	auto[0]	1531	1			T41	1428		T207	4		T210	2
all_values[3]	auto[1]	auto[1]	62	1			T41	1		T209	1		T210	2
all_values[4]	auto[0]	auto[0]	4282	1			T1	1		T2	5		T3	6
all_values[4]	auto[0]	auto[1]	167103	1			T1	3		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	98	1			T42	1		T207	3		T358	2
all_values[4]	auto[1]	auto[1]	70	1			T42	1		T207	2		T210	1
all_values[5]	auto[0]	auto[0]	171036	1			T1	4		T2	6		T3	7
all_values[5]	auto[0]	auto[1]	354	1			T7	1		T8	1		T57	1
all_values[5]	auto[1]	auto[0]	86	1			T207	3		T209	1		T358	4
all_values[5]	auto[1]	auto[1]	77	1			T207	1		T209	3		T210	2
all_values[6]	auto[0]	auto[0]	171136	1			T1	4		T2	6		T3	7
all_values[6]	auto[0]	auto[1]	203	1			T7	1		T8	1		T93	1
all_values[6]	auto[1]	auto[0]	101	1			T207	1		T210	3		T358	3
all_values[6]	auto[1]	auto[1]	113	1			T57	1		T64	1		T65	1
all_values[7]	auto[0]	auto[0]	115310	1			T7	2		T17	3		T20	2
all_values[7]	auto[0]	auto[1]	56058	1			T1	4		T2	6		T3	7
all_values[7]	auto[1]	auto[0]	117	1			T46	2		T47	2		T48	2
all_values[7]	auto[1]	auto[1]	68	1			T46	1		T47	1		T48	1
all_values[8]	auto[0]	auto[0]	170600	1			T1	4		T2	6		T3	7
all_values[8]	auto[0]	auto[1]	249	1			T51	2		T272	2		T327	2
all_values[8]	auto[1]	auto[0]	608	1			T49	10		T52	10		T53	10
all_values[8]	auto[1]	auto[1]	96	1			T49	1		T52	1		T55	1
all_values[9]	auto[0]	auto[0]	171300	1			T1	4		T2	6		T3	2
all_values[9]	auto[0]	auto[1]	70	1			T207	2		T209	2		T359	2
all_values[9]	auto[1]	auto[0]	106	1			T3	3		T58	3		T59	3
all_values[9]	auto[1]	auto[1]	77	1			T3	2		T58	2		T59	2
all_values[10]	auto[0]	auto[0]	170997	1			T1	4		T2	6		T3	7
all_values[10]	auto[0]	auto[1]	394	1			T19	1		T34	2		T35	1
all_values[10]	auto[1]	auto[0]	102	1			T207	3		T209	3		T210	4
all_values[10]	auto[1]	auto[1]	60	1			T207	3		T209	1		T359	1
all_values[11]	auto[0]	auto[0]	170579	1			T1	4		T2	6		T3	7
all_values[11]	auto[0]	auto[1]	716	1			T17	1		T30	4		T66	4
all_values[11]	auto[1]	auto[0]	143	1			T69	1		T70	1		T71	1
all_values[11]	auto[1]	auto[1]	115	1			T69	1		T70	1		T71	1
all_values[12]	auto[0]	auto[0]	171153	1			T1	4		T2	6		T3	7
all_values[12]	auto[0]	auto[1]	207	1			T74	1		T76	1		T77	1
all_values[12]	auto[1]	auto[0]	94	1			T72	2		T73	2		T75	2
all_values[12]	auto[1]	auto[1]	99	1			T72	1		T73	1		T75	1
all_values[13]	auto[0]	auto[0]	171206	1			T1	4		T2	6		T3	7
all_values[13]	auto[0]	auto[1]	80	1			T74	1		T76	1		T77	1
all_values[13]	auto[1]	auto[0]	149	1			T17	1		T78	1		T79	1
all_values[13]	auto[1]	auto[1]	118	1			T17	1		T78	1		T79	1
all_values[14]	auto[0]	auto[0]	35375	1			T1	4		T2	6		T3	7
all_values[14]	auto[0]	auto[1]	135999	1			T21	1		T41	1430		T8	2
all_values[14]	auto[1]	auto[0]	107	1			T207	2		T209	1		T210	4
all_values[14]	auto[1]	auto[1]	72	1			T207	6		T359	4		T360	3
all_values[15]	auto[0]	auto[0]	4339	1			T1	1		T2	5		T3	6
all_values[15]	auto[0]	auto[1]	167045	1			T1	3		T2	1		T3	1
all_values[15]	auto[1]	auto[0]	98	1			T207	3		T209	1		T210	1
all_values[15]	auto[1]	auto[1]	71	1			T207	2		T209	1		T359	2
all_values[16]	auto[0]	auto[0]	170501	1			T1	4		T2	6		T3	7
all_values[16]	auto[0]	auto[1]	864	1			T19	1		T24	1		T68	1
all_values[16]	auto[1]	auto[0]	98	1			T30	4		T66	4		T67	4
all_values[16]	auto[1]	auto[1]	90	1			T30	4		T66	4		T67	4
all_values[17]	auto[0]	auto[0]	114054	1			T2	1		T3	5		T7	2
all_values[17]	auto[0]	auto[1]	57335	1			T1	4		T2	2		T3	2
all_values[17]	auto[1]	auto[0]	109	1			T2	2		T56	2		T207	5
all_values[17]	auto[1]	auto[1]	55	1			T2	1		T56	1		T209	1