Name |
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/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3787479936 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.166568733 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.1497614138 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.4291965030 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1040658439 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.176662429 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.463785245 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3591266318 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.336958293 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4078369607 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.1148682342 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.465898332 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3615141846 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.3260534545 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1637311078 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.1606647175 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.4096009077 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.346956478 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.2426131285 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3953275806 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.2941989002 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.2075056910 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1487282058 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.917854650 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.992295719 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2809455958 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.1165073262 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.2808705041 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3162356612 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.1736399782 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.264111088 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3059810727 |
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/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.435789131 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3287070679 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3191339385 |
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/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.234566952 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.1600694146 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1265581276 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.2367873666 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.37671734 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.281342352 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.3071722347 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.2902550327 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3740271094 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.1941985042 |
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.107060588 |
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/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.3255614264 |
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