Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.44	98.11	95.91	97.44	87.30	98.22	98.17	92.94

Total tests in report: 3732

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
69.16	69.16	84.48	84.48	69.41	69.41	83.37	83.37	46.03	46.03	79.86	79.86	90.85	90.85	30.14	30.14	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.2818809002
75.03	5.87	88.78	4.30	81.10	11.69	85.29	1.92	47.62	1.59	91.01	11.15	91.26	0.41	40.18	10.05	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.257630083
78.92	3.89	91.44	2.65	85.52	4.42	87.63	2.35	57.14	9.52	94.45	3.44	93.29	2.03	42.99	2.81	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.2758131656
81.21	2.29	92.14	0.70	85.57	0.05	89.77	2.13	57.14	0.00	94.45	0.00	93.29	0.00	56.11	13.12	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.3185197149
82.72	1.51	92.52	0.38	86.90	1.33	90.72	0.96	63.49	6.35	95.07	0.62	93.29	0.00	57.01	0.90	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.1947079809
83.93	1.21	92.74	0.23	88.31	1.40	90.72	0.00	68.25	4.76	95.36	0.29	93.29	0.00	58.82	1.81	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.3749661985
85.05	1.12	92.78	0.04	88.64	0.33	92.22	1.49	68.25	0.00	95.44	0.08	95.93	2.64	62.08	3.26	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.1575047992
85.85	0.80	95.60	2.82	89.33	0.69	92.54	0.32	68.25	0.00	96.19	0.75	95.93	0.00	63.08	1.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1174051453
86.39	0.54	95.60	0.00	89.37	0.05	95.52	2.99	68.25	0.00	96.19	0.00	96.14	0.20	63.62	0.54	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2802779323
86.91	0.52	95.74	0.13	89.42	0.05	95.74	0.21	71.43	3.17	96.27	0.08	96.14	0.00	63.62	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.3125583547
87.42	0.52	95.91	0.17	89.52	0.10	95.74	0.00	74.60	3.17	96.44	0.17	96.14	0.00	63.62	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2359966731
87.91	0.49	95.91	0.00	89.76	0.24	95.74	0.00	74.60	0.00	96.48	0.04	96.54	0.41	66.33	2.71	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.1837131019
88.38	0.47	96.67	0.76	90.80	1.05	95.74	0.00	74.60	0.00	96.52	0.04	96.75	0.20	67.60	1.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.3726641202
88.81	0.43	97.40	0.74	91.92	1.12	95.74	0.00	74.60	0.00	97.68	1.16	96.75	0.00	67.60	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.259743068
89.15	0.34	97.40	0.00	91.99	0.07	95.95	0.21	74.60	0.00	97.68	0.00	96.75	0.00	69.68	2.08	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.2661976910
89.48	0.32	97.42	0.02	92.04	0.05	96.16	0.21	76.19	1.59	97.72	0.04	96.75	0.00	70.05	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.2044287354
89.77	0.29	97.46	0.04	92.16	0.12	96.16	0.00	77.78	1.59	97.76	0.04	96.75	0.00	70.32	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.2923822212
90.03	0.26	97.46	0.00	92.32	0.17	96.16	0.00	77.78	0.00	97.76	0.00	96.75	0.00	71.95	1.63	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2692520497
90.28	0.25	97.48	0.02	92.35	0.02	96.16	0.00	79.37	1.59	97.80	0.04	96.75	0.00	72.04	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.608841137
90.53	0.25	97.82	0.34	92.54	0.19	96.16	0.00	79.37	0.00	97.80	0.00	97.97	1.22	72.04	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.1019805777
90.77	0.24	97.84	0.02	92.58	0.05	96.16	0.00	80.95	1.59	97.85	0.04	97.97	0.00	72.04	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.1083752022
91.01	0.24	97.84	0.00	92.58	0.00	96.27	0.11	82.54	1.59	97.85	0.00	97.97	0.00	72.04	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_tx_rx_disruption.1296782864
91.25	0.24	97.88	0.04	92.58	0.00	96.27	0.00	84.13	1.59	97.89	0.04	97.97	0.00	72.04	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_link_resume.3114899975
91.48	0.23	97.88	0.00	92.63	0.05	96.27	0.00	85.71	1.59	97.89	0.00	97.97	0.00	72.04	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_tx_rx_disruption.2294398374
91.71	0.23	97.88	0.00	92.63	0.00	96.27	0.00	87.30	1.59	97.89	0.00	97.97	0.00	72.04	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/345.usbdev_tx_rx_disruption.3649423302
91.87	0.16	97.88	0.00	92.63	0.00	96.27	0.00	87.30	0.00	97.89	0.00	97.97	0.00	73.12	1.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.3746978887
92.02	0.15	97.88	0.00	92.80	0.17	96.48	0.21	87.30	0.00	97.93	0.04	97.97	0.00	73.76	0.63	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rx_full.3585104044
92.16	0.14	97.88	0.00	92.80	0.00	96.48	0.00	87.30	0.00	97.93	0.00	97.97	0.00	74.75	1.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.875076897
92.29	0.13	97.92	0.04	93.56	0.76	96.48	0.00	87.30	0.00	97.97	0.04	97.97	0.00	74.84	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.1490272924
92.41	0.12	97.92	0.00	93.56	0.00	96.48	0.00	87.30	0.00	97.97	0.00	97.97	0.00	75.66	0.81	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_endpoint_types.3862307008
92.52	0.12	97.92	0.00	93.56	0.00	96.48	0.00	87.30	0.00	97.97	0.00	97.97	0.00	76.47	0.81	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/68.usbdev_endpoint_types.1818795189
92.64	0.11	97.92	0.00	93.61	0.05	96.70	0.21	87.30	0.00	97.97	0.00	97.97	0.00	77.01	0.54	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_disconnected.3297285492
92.75	0.11	97.92	0.00	93.75	0.14	96.70	0.00	87.30	0.00	97.97	0.00	97.97	0.00	77.65	0.63	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.93927464
92.86	0.11	97.92	0.00	93.89	0.14	96.70	0.00	87.30	0.00	97.97	0.00	97.97	0.00	78.28	0.63	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_device_address.1444281508
92.97	0.11	97.92	0.00	94.03	0.14	96.91	0.21	87.30	0.00	98.01	0.04	97.97	0.00	78.64	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.1798186594
93.07	0.10	97.92	0.00	94.03	0.00	96.91	0.00	87.30	0.00	98.01	0.00	97.97	0.00	79.37	0.72	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_endpoint_types.905300507
93.17	0.10	97.92	0.00	94.08	0.05	97.12	0.21	87.30	0.00	98.01	0.00	97.97	0.00	79.82	0.45	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3166368807
93.26	0.09	97.92	0.00	94.08	0.00	97.12	0.00	87.30	0.00	98.01	0.00	97.97	0.00	80.45	0.63	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_types.2272145578
93.35	0.09	97.92	0.00	94.08	0.00	97.12	0.00	87.30	0.00	98.01	0.00	97.97	0.00	81.09	0.63	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.1693215736
93.43	0.08	97.92	0.00	94.08	0.00	97.12	0.00	87.30	0.00	98.01	0.00	97.97	0.00	81.63	0.54	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/157.usbdev_endpoint_types.4047072840
93.51	0.08	97.92	0.00	94.08	0.00	97.12	0.00	87.30	0.00	98.01	0.00	97.97	0.00	82.17	0.54	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/179.usbdev_endpoint_types.1233156379
93.59	0.08	97.92	0.00	94.08	0.00	97.12	0.00	87.30	0.00	98.01	0.00	97.97	0.00	82.71	0.54	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_types.3143196142
93.65	0.07	97.93	0.02	94.13	0.05	97.12	0.00	87.30	0.00	98.05	0.04	97.97	0.00	83.08	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.304852660
93.72	0.06	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	83.53	0.45	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.3056637024
93.78	0.06	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	83.98	0.45	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/60.usbdev_endpoint_types.1317879409
93.84	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	84.34	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.1376990434
93.89	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	84.71	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_endpoint_types.3534642946
93.94	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	85.07	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_types.2984705854
93.99	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	85.43	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_data_toggle_restore.3381703723
94.04	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	85.79	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/189.usbdev_endpoint_types.657696821
94.09	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	86.15	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_endpoint_types.1407398724
94.15	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	86.52	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/65.usbdev_endpoint_types.2847067904
94.20	0.05	97.93	0.00	94.13	0.00	97.12	0.00	87.30	0.00	98.05	0.00	97.97	0.00	86.88	0.36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.1701945614
94.25	0.05	97.99	0.06	94.20	0.07	97.33	0.21	87.30	0.00	98.05	0.00	97.97	0.00	86.88	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3239744532
94.29	0.05	98.01	0.02	94.30	0.10	97.33	0.00	87.30	0.00	98.09	0.04	97.97	0.00	87.06	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2764134435
94.33	0.04	98.03	0.02	94.32	0.02	97.44	0.11	87.30	0.00	98.14	0.04	97.97	0.00	87.15	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_tx_rx_disruption.3937544595
94.37	0.04	98.03	0.00	94.41	0.10	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	87.33	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.722614925
94.41	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	87.60	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/113.usbdev_endpoint_types.2274331545
94.45	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	87.87	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/167.usbdev_endpoint_types.3752402826
94.49	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	88.14	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_buffer.566678156
94.53	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	88.42	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/196.usbdev_endpoint_types.409292186
94.57	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	88.69	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_data_toggle_restore.1420142218
94.61	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	88.96	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_endpoint_types.3883149342
94.65	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	89.23	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_endpoint_types.4057021407
94.68	0.04	98.03	0.00	94.41	0.00	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	89.50	0.27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/82.usbdev_endpoint_types.1718578091
94.72	0.03	98.03	0.00	94.56	0.14	97.44	0.00	87.30	0.00	98.14	0.00	97.97	0.00	89.59	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rand_bus_resets.1733772172
94.75	0.03	98.03	0.00	94.58	0.02	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.20	89.59	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2275093178
94.78	0.03	98.03	0.00	94.77	0.19	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	89.59	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.4234507602
94.80	0.03	98.03	0.00	94.77	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	89.77	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.1532395286
94.83	0.03	98.03	0.00	94.77	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	89.95	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2159980619
94.85	0.03	98.03	0.00	94.77	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.14	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/137.usbdev_endpoint_types.214660862
94.88	0.03	98.03	0.00	94.77	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.32	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_types.20883019
94.91	0.03	98.03	0.00	94.77	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.50	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_endpoint_types.3174582278
94.93	0.03	98.03	0.00	94.77	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.68	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/85.usbdev_endpoint_types.244875350
94.96	0.03	98.03	0.00	94.77	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.86	0.18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.3831092124
94.98	0.02	98.09	0.06	94.79	0.02	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.95	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.433511458
95.00	0.01	98.09	0.00	94.89	0.10	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.95	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.2959798979
95.01	0.01	98.09	0.00	94.98	0.10	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	90.95	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_phy_pins_sense.1678142228
95.02	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.04	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.344103972
95.04	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.13	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.3047041438
95.05	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.22	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk.1155929631
95.06	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.31	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.1015086371
95.07	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.40	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_endpoint_types.704060587
95.09	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.49	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_low_speed_traffic.1800412989
95.10	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.58	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/124.usbdev_endpoint_types.503277157
95.11	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.67	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/139.usbdev_endpoint_types.2290781487
95.13	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.76	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/142.usbdev_endpoint_types.2495602769
95.14	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.86	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/147.usbdev_endpoint_types.2859565368
95.15	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	91.95	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_rx_full.549363513
95.17	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.04	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/154.usbdev_endpoint_types.1179672307
95.18	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.13	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/163.usbdev_endpoint_types.2380863494
95.19	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.22	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/197.usbdev_endpoint_types.2436335196
95.20	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.31	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/198.usbdev_endpoint_types.1170488565
95.22	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.40	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_rx_full.3790290356
95.23	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.49	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_rx_full.824470732
95.24	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.58	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_low_speed_traffic.3286229645
95.26	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.67	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.295802165
95.27	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.76	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_endpoint_types.1431669329
95.28	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.85	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_endpoint_types.3482240939
95.29	0.01	98.09	0.00	94.98	0.00	97.44	0.00	87.30	0.00	98.14	0.00	98.17	0.00	92.94	0.09	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_types.2646409715
95.31	0.01	98.09	0.00	95.03	0.05	97.44	0.00	87.30	0.00	98.18	0.04	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.2114824253
95.32	0.01	98.11	0.02	95.06	0.02	97.44	0.00	87.30	0.00	98.22	0.04	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_link_suspend.3633626190
95.33	0.01	98.11	0.00	95.13	0.07	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.3988819149
95.34	0.01	98.11	0.00	95.20	0.07	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.385633198
95.35	0.01	98.11	0.00	95.25	0.05	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.3142873407
95.35	0.01	98.11	0.00	95.29	0.05	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.3514672021
95.36	0.01	98.11	0.00	95.34	0.05	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.3877437147
95.37	0.01	98.11	0.00	95.39	0.05	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2907121763
95.37	0.01	98.11	0.00	95.44	0.05	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.1506379278
95.38	0.01	98.11	0.00	95.46	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2218618900
95.38	0.01	98.11	0.00	95.48	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.2693364540
95.38	0.01	98.11	0.00	95.51	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2327249029
95.39	0.01	98.11	0.00	95.53	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.2658072664
95.39	0.01	98.11	0.00	95.56	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.3218028088
95.39	0.01	98.11	0.00	95.58	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.3515621379
95.40	0.01	98.11	0.00	95.60	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/103.usbdev_tx_rx_disruption.870671293
95.40	0.01	98.11	0.00	95.63	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_nak_trans.1988143299
95.40	0.01	98.11	0.00	95.65	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_pending_in_trans.2430799071
95.41	0.01	98.11	0.00	95.67	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/113.usbdev_tx_rx_disruption.510507496
95.41	0.01	98.11	0.00	95.70	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/118.usbdev_tx_rx_disruption.3736832467
95.41	0.01	98.11	0.00	95.72	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_nak_trans.2379499925
95.42	0.01	98.11	0.00	95.75	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_nak_trans.3117458108
95.42	0.01	98.11	0.00	95.77	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_nak_trans.3225930888
95.42	0.01	98.11	0.00	95.79	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_nak_trans.3669703657
95.43	0.01	98.11	0.00	95.82	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_nak_trans.4289458759
95.43	0.01	98.11	0.00	95.84	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_nak_trans.104291121
95.43	0.01	98.11	0.00	95.86	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_nak_trans.369545325
95.44	0.01	98.11	0.00	95.89	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_nak_trans.327215339
95.44	0.01	98.11	0.00	95.91	0.02	97.44	0.00	87.30	0.00	98.22	0.00	98.17	0.00	92.94	0.00	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/474.usbdev_tx_rx_disruption.3920673074

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.2056509400
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2124771712
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.3497340366
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.4042355459
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.1131587440
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1787144167
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3667783884
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.788314571
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1822887638
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1026027944
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.2703456733
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.2625283659
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.1992555542
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4041775834
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.1121628745
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.3840308925
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.860360541
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.751894663
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3408388194
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.2925025455
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.904073344
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4020956269
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.3620492484
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.2464085301
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3149174973
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.2018562786
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.188686593
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.3149545353
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.1505800200
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1010733527
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.695855183
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.1718799479
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2545369570
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.2566860261
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4048948182
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3068169381
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.1152692224
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3488367244
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.4051279188
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.2166532681
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4079848909
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/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_tx_rx_disruption.1169004028
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.570872689
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/80.usbdev_tx_rx_disruption.3078706348
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/81.usbdev_endpoint_types.3934758961
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/81.usbdev_tx_rx_disruption.3883527186
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/82.usbdev_tx_rx_disruption.2299703635
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.3160685491
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/83.usbdev_tx_rx_disruption.1435831419
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/84.usbdev_endpoint_types.1295335490
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/84.usbdev_tx_rx_disruption.3004621153
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/85.usbdev_tx_rx_disruption.2614778097
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/86.usbdev_endpoint_types.2747437596
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/86.usbdev_tx_rx_disruption.1597223902
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/87.usbdev_endpoint_types.3123000325
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/87.usbdev_tx_rx_disruption.4044743922
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/88.usbdev_endpoint_types.1665430250
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/88.usbdev_tx_rx_disruption.4285449842
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/89.usbdev_endpoint_types.2398027763
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/89.usbdev_tx_rx_disruption.4181831180
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_alert_test.2159344700
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_disconnect.2683388934
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_reset.734634013
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_resume.1000257541
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_av_buffer.3611221594
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_bitstuff_err.3021696292
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_data_toggle_clear.2749169299
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_data_toggle_restore.1238255791
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_device_address.2482375318
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_device_timeout.155268108
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_disable_endpoint.495559605
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_disconnected.3636468349
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_enable.3929375574
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_endpoint_access.1622374140
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_endpoint_types.1776214855
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_fifo_rst.1709799274
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_in_iso.3896606968
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_in_stall.50987283
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_in_trans.4046942139
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_invalid_sync.53117584
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_iso_retraction.2588748572
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_link_in_err.2669680204
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_link_resume.249458087
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_link_suspend.1676114716
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_low_speed_traffic.4041182304
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_inter_pkt_delay.3140543160
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_in_transaction.1549916993
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_out_transaction.872633251
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_non_iso_usb_traffic.1097190015
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_usb_traffic.2219449539
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_min_inter_pkt_delay.3464883021
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_in_transaction.3298705482
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_out_transaction.857147171
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_nak_trans.2153117384
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_out_iso.1395374970
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_out_stall.3663915013
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_out_trans_nak.2660255721
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pending_in_trans.3037376832
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_pinflip.469012667
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_usb_ref_disable.2613157543
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_phy_pins_sense.2015080801
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_buffer.1399612147
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_received.4285387335
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_sent.3060886860
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_disconnects.1780032681
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_resets.887691612
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rand_suspends.1530472955
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_in_transaction.3862863464
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_out_transaction.1731277206
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_resume_link_active.816277948
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rx_crc_err.3679283282
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rx_full.871670658
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_setup_stage.2701730273
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_setup_trans_ignored.574523089
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_smoke.900659118
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_spurious_pids_ignored.1633195160
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_stall_priority_over_nak.751190459
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_stall_trans.3040675315
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_stream_len_max.3582461873
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_streaming_out.1632185546
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_timeout_missing_host_handshake.3271410817
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_tx_rx_disruption.3589399812
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.719764717
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.595392784
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.1022707106
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.272233429
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.2469276833
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.2235970770
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.3352363174
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.1332593042
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.3696117994
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.3891664340
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.3112356549
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.3269293418
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.1774756111
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.2338804235
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.237686959
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.3815226517
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.2973572370

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Total test records in report: 3732

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.4234507602			Feb 08 05:51:36 PM UTC 25	Feb 08 05:51:38 PM UTC 25	138801730 ps
T2	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.4067640243			Feb 08 05:51:36 PM UTC 25	Feb 08 05:51:38 PM UTC 25	152494249 ps
T3	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.3142873407			Feb 08 05:51:36 PM UTC 25	Feb 08 05:51:39 PM UTC 25	219067270 ps
T34	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1174051453			Feb 08 05:51:39 PM UTC 25	Feb 08 05:51:42 PM UTC 25	149799444 ps
T28	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3557771990			Feb 08 05:51:39 PM UTC 25	Feb 08 05:51:42 PM UTC 25	277449255 ps
T29	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.3247550875			Feb 08 05:51:42 PM UTC 25	Feb 08 05:51:45 PM UTC 25	141591561 ps
T30	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.2818809002			Feb 08 05:51:39 PM UTC 25	Feb 08 05:51:46 PM UTC 25	1164454536 ps
T35	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.1792538558			Feb 08 05:51:47 PM UTC 25	Feb 08 05:51:50 PM UTC 25	182554296 ps
T36	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.1179161427			Feb 08 05:51:45 PM UTC 25	Feb 08 05:51:50 PM UTC 25	714557254 ps
T37	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_enable.2015895142			Feb 08 05:51:51 PM UTC 25	Feb 08 05:51:53 PM UTC 25	44065157 ps
T7	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.3515888105			Feb 08 05:51:34 PM UTC 25	Feb 08 05:51:54 PM UTC 25	6165788413 ps
T17	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.546927163			Feb 08 05:51:51 PM UTC 25	Feb 08 05:51:56 PM UTC 25	841157579 ps
T18	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.3047041438			Feb 08 05:51:54 PM UTC 25	Feb 08 05:51:57 PM UTC 25	216516851 ps
T19	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2327249029			Feb 08 05:51:55 PM UTC 25	Feb 08 05:51:59 PM UTC 25	249094355 ps
T20	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2764134435			Feb 08 05:52:06 PM UTC 25	Feb 08 05:52:09 PM UTC 25	528700341 ps
T21	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.2168246772			Feb 08 05:52:09 PM UTC 25	Feb 08 05:52:12 PM UTC 25	235864726 ps
T22	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.1162325195			Feb 08 05:52:10 PM UTC 25	Feb 08 05:52:12 PM UTC 25	134887142 ps
T8	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.2758131656			Feb 08 05:51:34 PM UTC 25	Feb 08 05:52:13 PM UTC 25	13808703688 ps
T23	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.783393976			Feb 08 05:52:13 PM UTC 25	Feb 08 05:52:16 PM UTC 25	224972221 ps
T24	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.3145137132			Feb 08 05:52:14 PM UTC 25	Feb 08 05:52:17 PM UTC 25	249825435 ps
T31	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.2923822212			Feb 08 05:51:42 PM UTC 25	Feb 08 05:52:19 PM UTC 25	1300089413 ps
T32	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.2782209781			Feb 08 05:52:16 PM UTC 25	Feb 08 05:52:20 PM UTC 25	537374664 ps
T44	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.3877437147			Feb 08 05:52:18 PM UTC 25	Feb 08 05:52:20 PM UTC 25	168200129 ps
T45	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.3514672021			Feb 08 05:52:03 PM UTC 25	Feb 08 05:52:21 PM UTC 25	4179899514 ps
T33	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.3751833417			Feb 08 05:52:22 PM UTC 25	Feb 08 05:52:25 PM UTC 25	244081824 ps
T87	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.4177159403			Feb 08 05:52:26 PM UTC 25	Feb 08 05:52:29 PM UTC 25	195597302 ps
T49	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.2357751056			Feb 08 05:52:21 PM UTC 25	Feb 08 05:52:40 PM UTC 25	8431375223 ps
T9	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.1947079809			Feb 08 05:51:34 PM UTC 25	Feb 08 05:52:42 PM UTC 25	31060478583 ps
T4	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.1970259934			Feb 08 05:52:21 PM UTC 25	Feb 08 05:52:44 PM UTC 25	2216269618 ps
T513	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.2862617799			Feb 08 05:52:45 PM UTC 25	Feb 08 05:52:47 PM UTC 25	236812609 ps
T320	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.896589692			Feb 08 05:52:48 PM UTC 25	Feb 08 05:52:50 PM UTC 25	145885223 ps
T70	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2127657786			Feb 08 05:52:51 PM UTC 25	Feb 08 05:52:54 PM UTC 25	503662302 ps
T71	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.433511458			Feb 08 05:52:55 PM UTC 25	Feb 08 05:52:57 PM UTC 25	215570219 ps
T5	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.2940746596			Feb 08 05:52:29 PM UTC 25	Feb 08 05:52:59 PM UTC 25	2001145425 ps
T88	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.3437933996			Feb 08 05:52:58 PM UTC 25	Feb 08 05:53:00 PM UTC 25	184207924 ps
T72	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.4206423946			Feb 08 05:53:00 PM UTC 25	Feb 08 05:53:03 PM UTC 25	199636800 ps
T307	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.1496977591			Feb 08 05:53:01 PM UTC 25	Feb 08 05:53:04 PM UTC 25	150764662 ps
T90	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.1399323827			Feb 08 05:53:01 PM UTC 25	Feb 08 05:53:04 PM UTC 25	160291379 ps
T89	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2762168836			Feb 08 05:53:03 PM UTC 25	Feb 08 05:53:06 PM UTC 25	217138472 ps
T65	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.257630083			Feb 08 05:51:40 PM UTC 25	Feb 08 05:53:07 PM UTC 25	30318728653 ps
T46	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.1786937245			Feb 08 05:53:05 PM UTC 25	Feb 08 05:53:08 PM UTC 25	205397518 ps
T47	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.2226818826			Feb 08 05:53:05 PM UTC 25	Feb 08 05:53:08 PM UTC 25	291196669 ps
T48	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.3515108387			Feb 08 05:53:08 PM UTC 25	Feb 08 05:53:10 PM UTC 25	237397323 ps
T151	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2907121763			Feb 08 05:53:09 PM UTC 25	Feb 08 05:53:12 PM UTC 25	221563672 ps
T213	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.2114824253			Feb 08 05:53:09 PM UTC 25	Feb 08 05:53:12 PM UTC 25	139681651 ps
T121	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2359966731			Feb 08 05:53:09 PM UTC 25	Feb 08 05:53:12 PM UTC 25	301865343 ps
T25	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.210652851			Feb 08 05:53:11 PM UTC 25	Feb 08 05:53:14 PM UTC 25	39014757 ps
T85	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.1798186594			Feb 08 05:53:13 PM UTC 25	Feb 08 05:53:15 PM UTC 25	170527757 ps
T116	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.36926015			Feb 08 05:53:13 PM UTC 25	Feb 08 05:53:16 PM UTC 25	237460248 ps
T514	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.331857581			Feb 08 05:53:15 PM UTC 25	Feb 08 05:53:18 PM UTC 25	194082182 ps
T86	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.845633136			Feb 08 05:53:16 PM UTC 25	Feb 08 05:53:18 PM UTC 25	173935131 ps
T67	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.150049393			Feb 08 05:52:20 PM UTC 25	Feb 08 05:53:27 PM UTC 25	24939934482 ps
T6	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.871008777			Feb 08 05:52:22 PM UTC 25	Feb 08 05:53:41 PM UTC 25	2212620821 ps
T73	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3166368807			Feb 08 05:53:42 PM UTC 25	Feb 08 05:53:45 PM UTC 25	148369055 ps
T55	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.2355392614			Feb 08 05:53:45 PM UTC 25	Feb 08 05:53:48 PM UTC 25	351505853 ps
T66	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.722614925			Feb 08 05:53:17 PM UTC 25	Feb 08 05:53:49 PM UTC 25	6217815438 ps
T76	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.1506379278			Feb 08 05:53:50 PM UTC 25	Feb 08 05:53:52 PM UTC 25	153040048 ps
T52	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.304852660			Feb 08 05:53:50 PM UTC 25	Feb 08 05:53:53 PM UTC 25	404312323 ps
T166	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.2726560370			Feb 08 05:53:53 PM UTC 25	Feb 08 05:53:56 PM UTC 25	321928988 ps
T515	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.550247134			Feb 08 05:53:54 PM UTC 25	Feb 08 05:53:56 PM UTC 25	149292404 ps
T107	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.3749661985			Feb 08 05:52:40 PM UTC 25	Feb 08 05:53:56 PM UTC 25	2597946332 ps
T235	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.801724924			Feb 08 05:53:57 PM UTC 25	Feb 08 05:53:59 PM UTC 25	172337164 ps
T516	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.419593955			Feb 08 05:53:57 PM UTC 25	Feb 08 05:54:00 PM UTC 25	266238569 ps
T111	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.3195664445			Feb 08 05:54:22 PM UTC 25	Feb 08 05:54:25 PM UTC 25	241186700 ps
T339	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.564226457			Feb 08 05:54:01 PM UTC 25	Feb 08 05:54:03 PM UTC 25	165544663 ps
T484	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.660899876			Feb 08 05:54:01 PM UTC 25	Feb 08 05:54:04 PM UTC 25	207596779 ps
T517	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.3362724133			Feb 08 05:54:01 PM UTC 25	Feb 08 05:54:06 PM UTC 25	980263373 ps
T161	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.3724437841			Feb 08 05:54:04 PM UTC 25	Feb 08 05:54:08 PM UTC 25	568419036 ps
T210	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3239744532			Feb 08 05:54:07 PM UTC 25	Feb 08 05:54:09 PM UTC 25	33483517 ps
T216	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2802779323			Feb 08 05:54:07 PM UTC 25	Feb 08 05:54:11 PM UTC 25	482177699 ps
T93	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.2658072664			Feb 08 05:52:13 PM UTC 25	Feb 08 05:54:15 PM UTC 25	8603748304 ps
T96	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.1083752022			Feb 08 05:53:28 PM UTC 25	Feb 08 05:54:18 PM UTC 25	20164616681 ps
T233	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.4013263825			Feb 08 05:54:16 PM UTC 25	Feb 08 05:54:19 PM UTC 25	166945846 ps
T152	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.1117395836			Feb 08 05:53:57 PM UTC 25	Feb 08 05:54:21 PM UTC 25	3098010320 ps
T50	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.4162493219			Feb 08 05:54:19 PM UTC 25	Feb 08 05:54:21 PM UTC 25	170733530 ps
T61	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.975873373			Feb 08 05:54:20 PM UTC 25	Feb 08 05:54:22 PM UTC 25	192823142 ps
T82	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.2044311366			Feb 08 05:54:22 PM UTC 25	Feb 08 05:54:25 PM UTC 25	145488617 ps
T10	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.2779186426			Feb 08 05:54:09 PM UTC 25	Feb 08 05:54:27 PM UTC 25	4850280764 ps
T109	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.2131118520			Feb 08 05:54:23 PM UTC 25	Feb 08 05:54:28 PM UTC 25	759724449 ps
T105	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.1837131019			Feb 08 05:53:13 PM UTC 25	Feb 08 05:54:31 PM UTC 25	19226866210 ps
T63	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.2458765736			Feb 08 05:54:29 PM UTC 25	Feb 08 05:54:31 PM UTC 25	141625797 ps
T265	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.3182963467			Feb 08 05:54:28 PM UTC 25	Feb 08 05:54:32 PM UTC 25	640421733 ps
T153	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.2551039935			Feb 08 05:52:08 PM UTC 25	Feb 08 05:54:34 PM UTC 25	4961787999 ps
T260	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_enable.4151062235			Feb 08 05:54:32 PM UTC 25	Feb 08 05:54:34 PM UTC 25	47925515 ps
T113	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.1376990434			Feb 08 05:54:33 PM UTC 25	Feb 08 05:54:36 PM UTC 25	313659832 ps
T154	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.680864159			Feb 08 05:54:32 PM UTC 25	Feb 08 05:54:38 PM UTC 25	1073683993 ps
T208	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.2067424792			Feb 08 05:54:36 PM UTC 25	Feb 08 05:54:41 PM UTC 25	198115183 ps
T266	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2159980619			Feb 08 05:51:50 PM UTC 25	Feb 08 05:54:42 PM UTC 25	5105828203 ps
T11	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.3053429191			Feb 08 05:54:10 PM UTC 25	Feb 08 05:54:44 PM UTC 25	20365001940 ps
T199	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.1555843061			Feb 08 05:54:01 PM UTC 25	Feb 08 05:54:45 PM UTC 25	3588536179 ps
T110	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.1647268525			Feb 08 05:54:26 PM UTC 25	Feb 08 05:54:47 PM UTC 25	881793381 ps
T518	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.269111963			Feb 08 05:54:46 PM UTC 25	Feb 08 05:54:49 PM UTC 25	162907960 ps
T108	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.3815642244			Feb 08 05:54:48 PM UTC 25	Feb 08 05:54:51 PM UTC 25	148430418 ps
T519	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.1878321726			Feb 08 05:54:49 PM UTC 25	Feb 08 05:54:52 PM UTC 25	219025262 ps
T520	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.4189258213			Feb 08 05:54:53 PM UTC 25	Feb 08 05:54:55 PM UTC 25	216760444 ps
T187	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.1446195274			Feb 08 05:54:26 PM UTC 25	Feb 08 05:55:03 PM UTC 25	1125258765 ps
T157	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.4083423932			Feb 08 05:53:19 PM UTC 25	Feb 08 05:55:13 PM UTC 25	7416605473 ps
T521	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.1730168360			Feb 08 05:52:42 PM UTC 25	Feb 08 05:55:15 PM UTC 25	3795952463 ps
T12	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.1067118286			Feb 08 05:54:11 PM UTC 25	Feb 08 05:55:17 PM UTC 25	30722815571 ps
T522	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.519598863			Feb 08 05:55:16 PM UTC 25	Feb 08 05:55:19 PM UTC 25	252995704 ps
T523	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.3921006528			Feb 08 05:55:17 PM UTC 25	Feb 08 05:55:20 PM UTC 25	243007313 ps
T102	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.448780656			Feb 08 05:54:57 PM UTC 25	Feb 08 05:55:25 PM UTC 25	9777317175 ps
T524	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.3262831090			Feb 08 05:55:27 PM UTC 25	Feb 08 05:55:30 PM UTC 25	172005373 ps
T68	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.2044287354			Feb 08 05:54:57 PM UTC 25	Feb 08 05:55:32 PM UTC 25	13580325259 ps
T525	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.3432312171			Feb 08 05:55:30 PM UTC 25	Feb 08 05:55:32 PM UTC 25	156809438 ps
T509	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk.1155929631			Feb 08 05:51:57 PM UTC 25	Feb 08 05:55:34 PM UTC 25	83180622463 ps
T125	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.3218028088			Feb 08 05:55:32 PM UTC 25	Feb 08 05:55:35 PM UTC 25	222433915 ps
T485	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.283100471			Feb 08 05:55:34 PM UTC 25	Feb 08 05:55:36 PM UTC 25	158635685 ps
T234	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.4248306842			Feb 08 05:55:34 PM UTC 25	Feb 08 05:55:36 PM UTC 25	196243083 ps
T167	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.3966930982			Feb 08 05:55:36 PM UTC 25	Feb 08 05:55:39 PM UTC 25	153561968 ps
T480	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.1326974051			Feb 08 05:55:36 PM UTC 25	Feb 08 05:55:39 PM UTC 25	178729973 ps
T526	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.1688958147			Feb 08 05:55:37 PM UTC 25	Feb 08 05:55:40 PM UTC 25	260427148 ps
T162	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.894186899			Feb 08 05:55:37 PM UTC 25	Feb 08 05:55:40 PM UTC 25	253876288 ps
T26	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.259743068			Feb 08 05:55:39 PM UTC 25	Feb 08 05:55:42 PM UTC 25	40135708 ps
T214	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.4189306791			Feb 08 05:55:39 PM UTC 25	Feb 08 05:55:42 PM UTC 25	145907901 ps
T155	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.3310052249			Feb 08 05:55:14 PM UTC 25	Feb 08 05:55:43 PM UTC 25	2531049864 ps
T337	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.2311073575			Feb 08 05:55:42 PM UTC 25	Feb 08 05:55:44 PM UTC 25	171384509 ps
T527	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.4165775198			Feb 08 05:55:43 PM UTC 25	Feb 08 05:55:45 PM UTC 25	165815716 ps
T528	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.810754296			Feb 08 05:55:43 PM UTC 25	Feb 08 05:55:46 PM UTC 25	212101549 ps
T529	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.2021048008			Feb 08 05:55:43 PM UTC 25	Feb 08 05:55:46 PM UTC 25	217349690 ps
T74	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.656624707			Feb 08 05:55:47 PM UTC 25	Feb 08 05:55:49 PM UTC 25	184673620 ps
T56	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.1015086371			Feb 08 05:55:50 PM UTC 25	Feb 08 05:55:53 PM UTC 25	364294831 ps
T530	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.3451467727			Feb 08 05:55:26 PM UTC 25	Feb 08 05:55:53 PM UTC 25	2334536008 ps
T506	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk_max.3519258581			Feb 08 05:52:00 PM UTC 25	Feb 08 05:55:55 PM UTC 25	99171377616 ps
T77	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.2296063071			Feb 08 05:55:54 PM UTC 25	Feb 08 05:55:57 PM UTC 25	220884132 ps
T53	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.3014505314			Feb 08 05:55:54 PM UTC 25	Feb 08 05:55:57 PM UTC 25	388406981 ps
T194	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.3110789719			Feb 08 05:55:56 PM UTC 25	Feb 08 05:56:00 PM UTC 25	328250505 ps
T114	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2692520497			Feb 08 05:54:25 PM UTC 25	Feb 08 05:56:00 PM UTC 25	36877399394 ps
T531	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.3120116476			Feb 08 05:55:58 PM UTC 25	Feb 08 05:56:00 PM UTC 25	184596556 ps
T305	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.2624698222			Feb 08 05:55:59 PM UTC 25	Feb 08 05:56:01 PM UTC 25	153327699 ps
T532	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.2391004105			Feb 08 05:56:01 PM UTC 25	Feb 08 05:56:04 PM UTC 25	231694611 ps
T487	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.234420323			Feb 08 05:56:01 PM UTC 25	Feb 08 05:56:04 PM UTC 25	167395452 ps
T533	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.1562778810			Feb 08 05:56:01 PM UTC 25	Feb 08 05:56:04 PM UTC 25	232671446 ps
T180	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.3429815762			Feb 08 05:55:21 PM UTC 25	Feb 08 05:56:05 PM UTC 25	3353724459 ps
T184	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.1304260178			Feb 08 05:55:21 PM UTC 25	Feb 08 05:56:06 PM UTC 25	4280285531 ps
T437	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.3595814047			Feb 08 05:56:25 PM UTC 25	Feb 08 05:56:27 PM UTC 25	347637793 ps
T534	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.1254491237			Feb 08 05:56:05 PM UTC 25	Feb 08 05:56:10 PM UTC 25	1055664062 ps
T181	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.1268474412			Feb 08 05:55:03 PM UTC 25	Feb 08 05:56:10 PM UTC 25	5692327112 ps
T505	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.3491957669			Feb 08 05:56:06 PM UTC 25	Feb 08 05:56:10 PM UTC 25	607336365 ps
T163	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.2974750128			Feb 08 05:55:45 PM UTC 25	Feb 08 05:56:11 PM UTC 25	5323611196 ps
T217	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.1739075876			Feb 08 05:56:08 PM UTC 25	Feb 08 05:56:11 PM UTC 25	686291281 ps
T211	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.175842026			Feb 08 05:56:10 PM UTC 25	Feb 08 05:56:12 PM UTC 25	40763905 ps
T535	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.3067056108			Feb 08 05:56:12 PM UTC 25	Feb 08 05:56:14 PM UTC 25	168744136 ps
T209	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.2062503807			Feb 08 05:56:25 PM UTC 25	Feb 08 05:56:28 PM UTC 25	167559759 ps
T536	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk_max.1898169471			Feb 08 05:51:57 PM UTC 25	Feb 08 05:56:15 PM UTC 25	115206148126 ps
T51	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.2003377890			Feb 08 05:56:13 PM UTC 25	Feb 08 05:56:15 PM UTC 25	176889032 ps
T62	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.385633198			Feb 08 05:56:13 PM UTC 25	Feb 08 05:56:16 PM UTC 25	207502970 ps
T83	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.2816982579			Feb 08 05:56:16 PM UTC 25	Feb 08 05:56:18 PM UTC 25	158803440 ps
T537	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.1477401714			Feb 08 05:56:16 PM UTC 25	Feb 08 05:56:19 PM UTC 25	288060219 ps
T160	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.2959798979			Feb 08 05:54:45 PM UTC 25	Feb 08 05:56:19 PM UTC 25	2668344982 ps
T112	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.1754906907			Feb 08 05:56:17 PM UTC 25	Feb 08 05:56:20 PM UTC 25	775867418 ps
T262	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.691637941			Feb 08 05:55:40 PM UTC 25	Feb 08 05:56:20 PM UTC 25	11060499429 ps
T538	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.1347460866			Feb 08 05:56:05 PM UTC 25	Feb 08 05:56:22 PM UTC 25	1991767264 ps
T377	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.411843786			Feb 08 05:56:20 PM UTC 25	Feb 08 05:56:23 PM UTC 25	1046509968 ps
T539	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_enable.2395747462			Feb 08 05:56:21 PM UTC 25	Feb 08 05:56:23 PM UTC 25	42526201 ps
T64	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.1823469566			Feb 08 05:56:21 PM UTC 25	Feb 08 05:56:24 PM UTC 25	149963006 ps
T97	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.3328748335			Feb 08 05:55:46 PM UTC 25	Feb 08 05:56:26 PM UTC 25	20176953694 ps
T540	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.2998443745			Feb 08 05:56:23 PM UTC 25	Feb 08 05:56:27 PM UTC 25	818399297 ps
T13	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.2500878483			Feb 08 05:56:12 PM UTC 25	Feb 08 05:56:28 PM UTC 25	6289222860 ps
T541	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.2509647727			Feb 08 05:56:29 PM UTC 25	Feb 08 05:56:33 PM UTC 25	238843827 ps
T542	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.2118417429			Feb 08 05:56:33 PM UTC 25	Feb 08 05:56:36 PM UTC 25	150812219 ps
T510	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk.3693462455			Feb 08 05:51:58 PM UTC 25	Feb 08 05:56:37 PM UTC 25	99116697239 ps
T14	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.2049867765			Feb 08 05:56:12 PM UTC 25	Feb 08 05:56:37 PM UTC 25	15015178386 ps
T174	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.1939982358			Feb 08 05:53:18 PM UTC 25	Feb 08 05:56:38 PM UTC 25	7580582812 ps
T543	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.1752011967			Feb 08 05:56:37 PM UTC 25	Feb 08 05:56:39 PM UTC 25	217190929 ps
T544	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.3660554967			Feb 08 05:56:38 PM UTC 25	Feb 08 05:56:41 PM UTC 25	174913292 ps
T545	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.4057064730			Feb 08 05:56:19 PM UTC 25	Feb 08 05:56:42 PM UTC 25	2045891925 ps
T546	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.3976526668			Feb 08 05:56:43 PM UTC 25	Feb 08 05:56:46 PM UTC 25	243731306 ps
T547	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.572698680			Feb 08 05:56:43 PM UTC 25	Feb 08 05:56:46 PM UTC 25	270749896 ps
T94	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.2805030219			Feb 08 05:54:51 PM UTC 25	Feb 08 05:56:47 PM UTC 25	13259348693 ps
T548	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.3153796782			Feb 08 05:56:20 PM UTC 25	Feb 08 05:56:47 PM UTC 25	2922036639 ps
T549	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.3642664762			Feb 08 05:56:49 PM UTC 25	Feb 08 05:56:51 PM UTC 25	190136651 ps
T550	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.456257790			Feb 08 05:56:52 PM UTC 25	Feb 08 05:56:55 PM UTC 25	174620228 ps
T142	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.154359969			Feb 08 05:56:55 PM UTC 25	Feb 08 05:56:58 PM UTC 25	220975542 ps
T551	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.608841137			Feb 08 05:56:41 PM UTC 25	Feb 08 05:56:58 PM UTC 25	8990387892 ps
T552	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.1865695340			Feb 08 05:56:59 PM UTC 25	Feb 08 05:57:02 PM UTC 25	200443363 ps
T553	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.1411027050			Feb 08 05:56:59 PM UTC 25	Feb 08 05:57:02 PM UTC 25	184968022 ps
T115	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.358559846			Feb 08 05:56:17 PM UTC 25	Feb 08 05:57:03 PM UTC 25	13633545458 ps
T195	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.2647925834			Feb 08 05:57:02 PM UTC 25	Feb 08 05:57:05 PM UTC 25	151391918 ps
T554	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.4228414946			Feb 08 05:57:02 PM UTC 25	Feb 08 05:57:05 PM UTC 25	159245217 ps
T555	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_phase.1857719907			Feb 08 05:52:03 PM UTC 25	Feb 08 05:57:05 PM UTC 25	112152490092 ps
T556	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.2393526984			Feb 08 05:57:04 PM UTC 25	Feb 08 05:57:07 PM UTC 25	284653075 ps
T557	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_invalid_sync.2720609980			Feb 08 05:56:28 PM UTC 25	Feb 08 05:57:08 PM UTC 25	4610095548 ps
T69	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.839340452			Feb 08 05:56:39 PM UTC 25	Feb 08 05:57:08 PM UTC 25	9162169350 ps
T27	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.1962154343			Feb 08 05:57:07 PM UTC 25	Feb 08 05:57:09 PM UTC 25	33000321 ps
T215	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.3692146393			Feb 08 05:57:07 PM UTC 25	Feb 08 05:57:09 PM UTC 25	153664332 ps
T558	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.3372920009			Feb 08 05:57:07 PM UTC 25	Feb 08 05:57:09 PM UTC 25	235856083 ps
T175	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_disconnects.865369763			Feb 08 05:55:44 PM UTC 25	Feb 08 05:57:10 PM UTC 25	13329140661 ps
T338	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.2219071802			Feb 08 05:57:09 PM UTC 25	Feb 08 05:57:12 PM UTC 25	185661113 ps
T559	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.1482668024			Feb 08 05:57:09 PM UTC 25	Feb 08 05:57:12 PM UTC 25	171981636 ps
T560	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.856470798			Feb 08 05:57:10 PM UTC 25	Feb 08 05:57:13 PM UTC 25	184607952 ps
T561	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.960970420			Feb 08 05:57:10 PM UTC 25	Feb 08 05:57:13 PM UTC 25	234582388 ps
T15	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.4158584560			Feb 08 05:56:12 PM UTC 25	Feb 08 05:57:14 PM UTC 25	23515391732 ps
T95	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_iso_retraction.1161851330			Feb 08 05:56:38 PM UTC 25	Feb 08 05:57:16 PM UTC 25	3288119974 ps
T164	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.93927464			Feb 08 05:56:42 PM UTC 25	Feb 08 05:57:16 PM UTC 25	3343746172 ps
T75	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.2052938912			Feb 08 05:57:14 PM UTC 25	Feb 08 05:57:16 PM UTC 25	174399968 ps
T57	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.1229274263			Feb 08 05:57:14 PM UTC 25	Feb 08 05:57:17 PM UTC 25	317208721 ps
T78	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.516250462			Feb 08 05:57:15 PM UTC 25	Feb 08 05:57:18 PM UTC 25	158683616 ps
T156	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_usb_traffic.1059005144			Feb 08 05:56:47 PM UTC 25	Feb 08 05:57:18 PM UTC 25	3127300290 ps
T562	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.2128037715			Feb 08 05:57:17 PM UTC 25	Feb 08 05:57:20 PM UTC 25	148240958 ps
T178	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.1487721355			Feb 08 05:57:17 PM UTC 25	Feb 08 05:57:20 PM UTC 25	174972896 ps
T54	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.3085960423			Feb 08 05:57:17 PM UTC 25	Feb 08 05:57:21 PM UTC 25	417638040 ps
T306	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.1364179915			Feb 08 05:57:19 PM UTC 25	Feb 08 05:57:21 PM UTC 25	142016655 ps
T165	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.1424779478			Feb 08 05:55:46 PM UTC 25	Feb 08 05:57:21 PM UTC 25	10803928550 ps
T563	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.296834752			Feb 08 05:57:19 PM UTC 25	Feb 08 05:57:22 PM UTC 25	206272616 ps
T564	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.3822771577			Feb 08 05:56:46 PM UTC 25	Feb 08 05:57:22 PM UTC 25	3020786106 ps
T565	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.811033114			Feb 08 05:57:21 PM UTC 25	Feb 08 05:57:24 PM UTC 25	188641674 ps
T488	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.1054452167			Feb 08 05:57:21 PM UTC 25	Feb 08 05:57:24 PM UTC 25	229693745 ps
T16	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_resume.3022008859			Feb 08 05:57:28 PM UTC 25	Feb 08 05:58:08 PM UTC 25	23356733221 ps
T218	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.2938869513			Feb 08 05:57:25 PM UTC 25	Feb 08 05:57:28 PM UTC 25	281520018 ps
T79	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.3665345447			Feb 08 05:57:24 PM UTC 25	Feb 08 05:57:28 PM UTC 25	574341997 ps
T212	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.3465044613			Feb 08 05:57:26 PM UTC 25	Feb 08 05:57:28 PM UTC 25	42060063 ps
T566	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.387864103			Feb 08 05:57:22 PM UTC 25	Feb 08 05:57:29 PM UTC 25	1220898813 ps
T567	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.1699819395			Feb 08 05:57:30 PM UTC 25	Feb 08 05:57:32 PM UTC 25	159411613 ps
T499	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.1786001037			Feb 08 05:57:30 PM UTC 25	Feb 08 05:57:32 PM UTC 25	183834915 ps
T568	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.3006181078			Feb 08 05:57:33 PM UTC 25	Feb 08 05:57:35 PM UTC 25	164510659 ps
T91	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.1895132931			Feb 08 05:57:33 PM UTC 25	Feb 08 05:57:35 PM UTC 25	152082063 ps
T569	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.3631112805			Feb 08 05:57:36 PM UTC 25	Feb 08 05:57:40 PM UTC 25	439439986 ps
T313	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.295802165			Feb 08 05:57:36 PM UTC 25	Feb 08 05:57:41 PM UTC 25	801402030 ps
T99	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.3125583547			Feb 08 05:57:28 PM UTC 25	Feb 08 05:57:41 PM UTC 25	6335968635 ps
T353	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.4108543536			Feb 08 05:57:43 PM UTC 25	Feb 08 05:57:48 PM UTC 25	655446434 ps
T570	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.3152205880			Feb 08 05:56:42 PM UTC 25	Feb 08 05:57:48 PM UTC 25	2079840072 ps
T571	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.1499284640			Feb 08 05:57:47 PM UTC 25	Feb 08 05:57:50 PM UTC 25	141928136 ps
T572	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_enable.810738133			Feb 08 05:57:48 PM UTC 25	Feb 08 05:57:50 PM UTC 25	28272517 ps
T573	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_spurious_pids_ignored.1865483908			Feb 08 05:57:19 PM UTC 25	Feb 08 05:57:52 PM UTC 25	3057262477 ps
T574	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.1949408592			Feb 08 05:57:43 PM UTC 25	Feb 08 05:57:53 PM UTC 25	1055422895 ps
T374	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.3746978887			Feb 08 05:57:50 PM UTC 25	Feb 08 05:57:54 PM UTC 25	575310821 ps
T575	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.3535691165			Feb 08 05:57:52 PM UTC 25	Feb 08 05:57:55 PM UTC 25	187229332 ps
T576	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_resets.4082017388			Feb 08 05:57:12 PM UTC 25	Feb 08 05:57:56 PM UTC 25	6115387502 ps
T577	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.4290538496			Feb 08 05:57:49 PM UTC 25	Feb 08 05:57:56 PM UTC 25	1191963693 ps
T511	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk.4068223738			Feb 08 05:54:36 PM UTC 25	Feb 08 05:57:57 PM UTC 25	99209057382 ps
T293	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.1438580005			Feb 08 05:57:08 PM UTC 25	Feb 08 05:57:59 PM UTC 25	12961616185 ps
T578	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.2279020697			Feb 08 05:57:58 PM UTC 25	Feb 08 05:58:01 PM UTC 25	179126969 ps
T579	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_streaming_out.3767894376			Feb 08 05:57:22 PM UTC 25	Feb 08 05:58:02 PM UTC 25	3100150287 ps
T580	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.2802065887			Feb 08 05:58:00 PM UTC 25	Feb 08 05:58:03 PM UTC 25	145225346 ps
T581	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.153739989			Feb 08 05:56:01 PM UTC 25	Feb 08 05:58:04 PM UTC 25	2859480304 ps
T582	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.4104390078			Feb 08 05:58:02 PM UTC 25	Feb 08 05:58:05 PM UTC 25	199672396 ps
T583	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.2039577270			Feb 08 05:58:04 PM UTC 25	Feb 08 05:58:07 PM UTC 25	230568927 ps
T584	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rand_suspends.2080285578			Feb 08 05:57:13 PM UTC 25	Feb 08 05:58:07 PM UTC 25	9894170065 ps
T80	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.1490272924			Feb 08 05:54:04 PM UTC 25	Feb 08 05:58:08 PM UTC 25	11058913795 ps
T585	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.346971478			Feb 08 05:56:49 PM UTC 25	Feb 08 05:58:09 PM UTC 25	2556214598 ps
T81	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.3515621379			Feb 08 05:56:06 PM UTC 25	Feb 08 05:58:10 PM UTC 25	8086585703 ps
T586	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.3222989996			Feb 08 05:58:09 PM UTC 25	Feb 08 05:58:11 PM UTC 25	250032958 ps
T587	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.1944475103			Feb 08 05:58:09 PM UTC 25	Feb 08 05:58:12 PM UTC 25	203108989 ps
T158	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_disconnects.2053965879			Feb 08 05:57:10 PM UTC 25	Feb 08 05:58:13 PM UTC 25	5625062765 ps
T98	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_resume_link_active.3062069622			Feb 08 05:57:13 PM UTC 25	Feb 08 05:58:14 PM UTC 25	20196426609 ps
T588	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.247962898			Feb 08 05:58:12 PM UTC 25	Feb 08 05:58:15 PM UTC 25	151047562 ps
T589	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.1368233444			Feb 08 05:58:12 PM UTC 25	Feb 08 05:58:15 PM UTC 25	198044924 ps
T148	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.1758425539			Feb 08 05:58:14 PM UTC 25	Feb 08 05:58:16 PM UTC 25	259299897 ps
T590	/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.910556304			Feb 08 05:57:43 PM UTC 25	Feb 08 05:58:17 PM UTC 25	4299869460 ps