Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1449	1			T65	5		T114	4		T112	18
range_16_to_126	153814	1			T2	1		T34	1		T29	1
fifteen	588	1			T65	1		T187	12		T114	4
range_2_to_14	17470	1			T3	1		T28	7		T18	2
seven	553	1			T31	18		T65	5		T86	1
one	1541	1			T17	24		T65	4		T114	5
zero	2622	1			T65	3		T82	1		T266	5

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

12943

1

T30

5

T36

4

T17

2

three

13295

1

T30

2

T36

3

T17

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	132	1			T114	1		T112	2		T496	13
range_127	three	114	1			T197	1		T411	1		T497	2
range_16_to_126	seven	11286	1			T30	5		T36	4		T23	2
range_16_to_126	three	11895	1			T30	2		T36	3		T33	2
fifteen	seven	20	1			T164	1		T197	1		T498	1
fifteen	three	49	1			T114	1		T186	1		T197	1
range_2_to_14	seven	1301	1			T65	4		T161	3		T113	1
range_2_to_14	three	1057	1			T65	2		T66	17		T265	2
seven	seven	38	1			T499	1		T172	1		T405	1
seven	three	116	1			T65	1		T265	1		T114	1
one	seven	45	1			T17	2		T65	1		T377	2
one	three	40	1			T17	2		T114	1		T365	1
zero	seven	159	1			T114	1		T500	2		T197	1
zero	three	140	1			T65	1		T500	2		T501	1