Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	3022	1			T322	1		T114	10		T268	582
range_16_to_126	148648	1			T1	1		T2	1		T18	18
fifteen	974	1			T114	4		T115	3		T116	2
range_2_to_14	22874	1			T23	2		T67	11		T83	1
seven	1266	1			T322	1		T113	1		T169	79
one	438	1			T114	8		T115	3		T177	1
zero	557	1			T17	1		T245	1		T90	101

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

13337

1

T19

2

T23

1

T29

2

three

12656

1

T19

1

T29

2

T8

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	90	1			T114	1		T268	49		T177	1
range_127	three	106	1			T114	2		T268	46		T177	2
range_16_to_126	seven	11728	1			T19	2		T23	1		T29	2
range_16_to_126	three	10749	1			T19	1		T29	2		T8	2
fifteen	seven	48	1			T114	1		T165	2		T515	1
fifteen	three	129	1			T418	1		T516	9		T433	1
range_2_to_14	seven	1428	1			T517	1		T518	2		T114	72
range_2_to_14	three	1637	1			T518	2		T114	63		T115	39
seven	seven	55	1			T115	1		T177	1		T173	33
seven	three	58	1			T116	1		T519	1		T166	1
one	seven	18	1			T418	1		T173	1		T515	1
one	three	18	1			T114	1		T166	1		T520	7
zero	seven	25	1			T245	1		T114	1		T115	1
zero	three	17	1			T114	1		T115	1		T418	1