Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109747

1

T2

1

T3

1

T34

1

auto[1]

46319

1

T28

2

T29

1

T30

18

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30100	1			T33	2		T87	1		T72	1
max_len_m1	849	1			T28	1		T45	1		T5	2
max_len_m2	813	1			T20	1		T45	3		T5	2
max_len_m3	749	1			T30	1		T45	3		T70	2
five	1122	1			T45	3		T4	2		T6	2
four	1179	1			T45	2		T70	1		T66	8
three	873	1			T28	1		T17	2		T45	2
one	880	1			T30	2		T17	2		T45	3
zero	12135	1			T34	1		T28	2		T29	1

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24446	1			T33	1		T87	1		T72	1
max_len	auto[1]	5654	1			T33	1		T116	1		T66	1
max_len_m1	auto[0]	595	1			T28	1		T45	1		T5	1
max_len_m1	auto[1]	254	1			T5	1		T6	2		T107	1
max_len_m2	auto[0]	541	1			T20	1		T45	3		T5	1
max_len_m2	auto[1]	272	1			T5	1		T66	1		T152	1
max_len_m3	auto[0]	521	1			T30	1		T45	3		T70	2
max_len_m3	auto[1]	228	1			T6	1		T152	2		T153	1
five	auto[0]	594	1			T45	3		T4	1		T6	1
five	auto[1]	528	1			T4	1		T6	1		T66	1
four	auto[0]	592	1			T45	2		T70	1		T66	4
four	auto[1]	587	1			T66	4		T105	14		T153	1
three	auto[0]	412	1			T28	1		T17	1		T45	2
three	auto[1]	461	1			T17	1		T105	13		T505	1
one	auto[0]	395	1			T30	1		T17	1		T45	3
one	auto[1]	485	1			T30	1		T17	1		T105	12
zero	auto[0]	543	1			T34	1		T30	1		T17	1
zero	auto[1]	11592	1			T28	2		T29	1		T30	8