Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109512

1

T1

1

T2

1

T17

1

auto[1]

46009

1

T18

7

T19

14

T29

12

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30065	1			T117	2		T80	1		T4	3
max_len_m1	793	1			T41	1		T67	1		T4	3
max_len_m2	829	1			T4	1		T153	4		T63	5
max_len_m3	811	1			T41	1		T4	2		T5	2
five	1073	1			T18	1		T41	3		T66	1
four	1203	1			T18	1		T41	3		T4	4
three	756	1			T19	1		T41	2		T66	2
one	882	1			T6	1		T105	2		T63	4
zero	11719	1			T17	1		T18	7		T19	9

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24196	1			T117	1		T80	1		T4	2
max_len	auto[1]	5869	1			T117	1		T4	1		T5	1
max_len_m1	auto[0]	543	1			T41	1		T67	1		T4	2
max_len_m1	auto[1]	250	1			T4	1		T5	1		T6	1
max_len_m2	auto[0]	572	1			T4	1		T153	2		T63	5
max_len_m2	auto[1]	257	1			T153	2		T160	1		T161	1
max_len_m3	auto[0]	551	1			T41	1		T4	1		T5	1
max_len_m3	auto[1]	260	1			T4	1		T5	1		T151	1
five	auto[0]	551	1			T18	1		T41	3		T66	1
five	auto[1]	522	1			T5	1		T62	1		T63	4
four	auto[0]	624	1			T18	1		T41	3		T4	2
four	auto[1]	579	1			T4	2		T6	1		T62	2
three	auto[0]	367	1			T19	1		T41	2		T66	2
three	auto[1]	389	1			T45	1		T105	1		T527	1
one	auto[0]	399	1			T6	1		T105	1		T63	2
one	auto[1]	483	1			T105	1		T63	2		T268	12
zero	auto[0]	542	1			T17	1		T41	1		T150	1
zero	auto[1]	11177	1			T18	7		T19	9		T35	16