Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137232

1

T1

2

T2

2

T18

22

auto[1]

77614

1

T18

14

T19

23

T29

24

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	18920	1			T2	2		T19	11		T24	15
endpoints[0x1]	17514	1			T19	4		T29	4		T43	6
endpoints[0x2]	15103	1			T19	3		T29	4		T528	2
endpoints[0x3]	16764	1			T19	2		T29	4		T8	4
endpoints[0x4]	16000	1			T19	4		T29	4		T80	2
endpoints[0x5]	20270	1			T19	2		T29	4		T150	4
endpoints[0x6]	17130	1			T19	3		T29	4		T30	21
endpoints[0x7]	18659	1			T19	4		T29	4		T526	2
endpoints[0x8]	17281	1			T19	2		T29	4		T31	2
endpoints[0x9]	17621	1			T1	2		T19	2		T29	4
endpoints[0xa]	19484	1			T19	11		T29	4		T34	4
endpoints[0xb]	20100	1			T18	36		T19	3		T29	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1288	1			T19	5		T30	2		T66	2
ack	104025	1			T1	1		T2	1		T18	18
data1	50426	1			T18	2		T19	14		T24	1
data0	59031	1			T1	1		T2	1		T18	16

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	57	1			T115	4		T272	1		T529	1
nak	auto[0]	endpoints[0x1]	141	1			T50	1		T54	1		T312	1
nak	auto[0]	endpoints[0x2]	90	1			T114	14		T116	5		T126	1
nak	auto[0]	endpoints[0x3]	127	1			T501	1		T121	1		T114	13
nak	auto[0]	endpoints[0x4]	77	1			T530	1		T531	1		T532	1
nak	auto[0]	endpoints[0x5]	105	1			T114	14		T177	7		T418	6
nak	auto[0]	endpoints[0x6]	105	1			T30	2		T66	2		T247	1
nak	auto[0]	endpoints[0x7]	120	1			T68	1		T533	1		T138	1
nak	auto[0]	endpoints[0x8]	83	1			T67	2		T534	1		T141	1
nak	auto[0]	endpoints[0x9]	27	1			T114	13		T143	1		T144	1
nak	auto[0]	endpoints[0xa]	95	1			T115	10		T173	10		T146	1
nak	auto[0]	endpoints[0xb]	75	1			T173	7		T441	5		T147	1
nak	auto[1]	endpoints[0x0]	18	1			T19	1		T535	1		T536	1
nak	auto[1]	endpoints[0x1]	15	1			T537	1		T538	2		T535	1
nak	auto[1]	endpoints[0x2]	14	1			T105	1		T539	1		T540	1
nak	auto[1]	endpoints[0x3]	12	1			T541	1		T538	1		T540	1
nak	auto[1]	endpoints[0x4]	14	1			T19	1		T535	1		T542	2
nak	auto[1]	endpoints[0x5]	14	1			T105	1		T539	1		T537	1
nak	auto[1]	endpoints[0x6]	15	1			T19	1		T111	1		T541	1
nak	auto[1]	endpoints[0x7]	20	1			T105	1		T543	3		T539	1
nak	auto[1]	endpoints[0x8]	13	1			T537	1		T544	1		T545	1
nak	auto[1]	endpoints[0x9]	13	1			T105	2		T543	1		T545	1
nak	auto[1]	endpoints[0xa]	18	1			T19	2		T105	1		T539	1
nak	auto[1]	endpoints[0xb]	20	1			T111	1		T543	1		T537	1
ack	auto[0]	endpoints[0x0]	6212	1			T2	1		T19	3		T24	7
ack	auto[0]	endpoints[0x1]	5407	1			T19	1		T29	1		T43	2
ack	auto[0]	endpoints[0x2]	4280	1			T19	1		T29	1		T528	1
ack	auto[0]	endpoints[0x3]	4785	1			T19	1		T29	1		T8	1
ack	auto[0]	endpoints[0x4]	4528	1			T19	1		T29	1		T80	1
ack	auto[0]	endpoints[0x5]	6915	1			T19	1		T29	1		T150	1
ack	auto[0]	endpoints[0x6]	5213	1			T29	1		T30	8		T66	8
ack	auto[0]	endpoints[0x7]	5536	1			T19	2		T29	1		T526	1
ack	auto[0]	endpoints[0x8]	4806	1			T19	1		T29	1		T31	1
ack	auto[0]	endpoints[0x9]	5273	1			T1	1		T19	1		T29	1
ack	auto[0]	endpoints[0xa]	6333	1			T19	1		T29	1		T34	1
ack	auto[0]	endpoints[0xb]	6545	1			T18	11		T19	1		T29	1
ack	auto[1]	endpoints[0x0]	3035	1			T19	1		T29	1		T45	1
ack	auto[1]	endpoints[0x1]	3034	1			T19	1		T29	1		T43	1
ack	auto[1]	endpoints[0x2]	3033	1			T29	1		T5	53		T153	7
ack	auto[1]	endpoints[0x3]	3330	1			T29	1		T8	1		T97	7
ack	auto[1]	endpoints[0x4]	3174	1			T29	1		T4	6		T6	4
ack	auto[1]	endpoints[0x5]	2906	1			T29	1		T150	1		T6	4
ack	auto[1]	endpoints[0x6]	3031	1			T29	1		T152	1		T153	7
ack	auto[1]	endpoints[0x7]	3473	1			T29	1		T4	6		T154	1
ack	auto[1]	endpoints[0x8]	3539	1			T29	1		T33	1		T4	6
ack	auto[1]	endpoints[0x9]	3283	1			T29	1		T44	1		T4	6
ack	auto[1]	endpoints[0xa]	3125	1			T19	2		T29	1		T35	10
ack	auto[1]	endpoints[0xb]	3229	1			T18	7		T29	1		T4	6
data1	auto[0]	endpoints[0x0]	2820	1			T19	1		T24	1		T45	1
data1	auto[0]	endpoints[0x1]	2444	1			T43	1		T4	1		T50	4
data1	auto[0]	endpoints[0x2]	1894	1			T5	26		T153	3		T151	1
data1	auto[0]	endpoints[0x3]	2102	1			T19	1		T153	1		T151	1
data1	auto[0]	endpoints[0x4]	1961	1			T19	1		T4	1		T6	1
data1	auto[0]	endpoints[0x5]	3154	1			T6	1		T151	1		T62	3
data1	auto[0]	endpoints[0x6]	2319	1			T30	5		T66	5		T153	3
data1	auto[0]	endpoints[0x7]	2485	1			T19	1		T68	1		T4	3
data1	auto[0]	endpoints[0x8]	2059	1			T67	5		T4	2		T6	2
data1	auto[0]	endpoints[0x9]	2341	1			T19	1		T44	1		T4	3
data1	auto[0]	endpoints[0xa]	2898	1			T19	1		T84	1		T4	3
data1	auto[0]	endpoints[0xb]	2967	1			T18	2		T19	1		T4	3
data1	auto[1]	endpoints[0x0]	1660	1			T19	1		T45	1		T6	2
data1	auto[1]	endpoints[0x1]	1631	1			T43	1		T4	4		T62	3
data1	auto[1]	endpoints[0x2]	1635	1			T19	1		T5	26		T153	3
data1	auto[1]	endpoints[0x3]	1860	1			T97	6		T4	5		T153	5
data1	auto[1]	endpoints[0x4]	1721	1			T19	1		T4	5		T6	2
data1	auto[1]	endpoints[0x5]	1578	1			T6	3		T151	3		T105	2
data1	auto[1]	endpoints[0x6]	1673	1			T153	4		T105	2		T62	3
data1	auto[1]	endpoints[0x7]	1951	1			T4	3		T154	1		T153	5
data1	auto[1]	endpoints[0x8]	1986	1			T4	4		T6	2		T63	8
data1	auto[1]	endpoints[0x9]	1797	1			T44	1		T4	3		T151	4
data1	auto[1]	endpoints[0xa]	1708	1			T19	3		T35	5		T84	1
data1	auto[1]	endpoints[0xb]	1782	1			T19	1		T4	3		T153	5
data0	auto[0]	endpoints[0x0]	3664	1			T2	1		T19	2		T24	7
data0	auto[0]	endpoints[0x1]	3369	1			T19	1		T29	1		T43	1
data0	auto[0]	endpoints[0x2]	2695	1			T19	1		T29	1		T528	1
data0	auto[0]	endpoints[0x3]	2985	1			T29	1		T8	1		T501	1
data0	auto[0]	endpoints[0x4]	2987	1			T29	1		T80	1		T82	1
data0	auto[0]	endpoints[0x5]	4180	1			T19	1		T29	1		T150	1
data0	auto[0]	endpoints[0x6]	3309	1			T29	1		T30	6		T66	6
data0	auto[0]	endpoints[0x7]	3451	1			T19	1		T29	1		T526	1
data0	auto[0]	endpoints[0x8]	3138	1			T19	1		T29	1		T31	1
data0	auto[0]	endpoints[0x9]	3309	1			T1	1		T29	1		T81	1
data0	auto[0]	endpoints[0xa]	3808	1			T29	1		T34	1		T117	1
data0	auto[0]	endpoints[0xb]	3932	1			T18	9		T29	1		T4	3
data0	auto[1]	endpoints[0x0]	1447	1			T19	2		T29	1		T546	1
data0	auto[1]	endpoints[0x1]	1468	1			T19	1		T29	1		T4	2
data0	auto[1]	endpoints[0x2]	1460	1			T29	1		T5	27		T153	4
data0	auto[1]	endpoints[0x3]	1559	1			T29	1		T8	1		T97	8
data0	auto[1]	endpoints[0x4]	1532	1			T29	1		T4	1		T6	2
data0	auto[1]	endpoints[0x5]	1406	1			T29	1		T150	1		T6	1
data0	auto[1]	endpoints[0x6]	1456	1			T19	2		T29	1		T152	1
data0	auto[1]	endpoints[0x7]	1617	1			T29	1		T4	3		T153	2
data0	auto[1]	endpoints[0x8]	1653	1			T29	1		T33	1		T4	2
data0	auto[1]	endpoints[0x9]	1569	1			T29	1		T4	3		T151	1
data0	auto[1]	endpoints[0xa]	1491	1			T19	2		T29	1		T34	1
data0	auto[1]	endpoints[0xb]	1546	1			T18	7		T29	1		T4	3