Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
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Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
78.95 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 18 0 18 100.00
Crosses 96 24 72 75.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_dir 2 0 2 100.00 100 1 1 2
cp_endp 12 0 12 100.00 100 1 1 0
cp_pid 4 0 4 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_X_dir_X_endp 96 24 72 75.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 69993 1 T2 1 T3 1 T28 5
auto[1] 78411 1 T28 4 T29 2 T30 28


Summary for Variable cp_endp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for cp_endp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
endpoints[0x0] 11593 1 T2 1 T30 5 T17 3
endpoints[0x1] 13784 1 T3 1 T30 3 T17 3
endpoints[0x2] 12747 1 T30 4 T17 3 T21 1
endpoints[0x3] 12329 1 T30 3 T17 3 T33 3
endpoints[0x4] 14390 1 T30 1 T17 3 T307 1
endpoints[0x5] 11443 1 T30 4 T17 3 T4 12
endpoints[0x6] 9793 1 T28 9 T30 1 T17 3
endpoints[0x7] 11942 1 T30 6 T17 3 T23 3
endpoints[0x8] 12310 1 T29 2 T30 6 T17 3
endpoints[0x9] 12477 1 T30 5 T17 3 T24 3
endpoints[0xa] 14563 1 T30 5 T17 3 T31 28
endpoints[0xb] 11033 1 T30 3 T17 3 T4 12


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_pid

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
nak 170 1 T30 4 T109 3 T112 4
ack 38611 1 T28 2 T29 1 T30 6
data1 51187 1 T28 2 T30 15 T20 5
data0 58368 1 T2 1 T3 1 T28 5


Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 96 24 72 75.00 24


Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes
cp_pidcp_dircp_endpCOUNTAT LEASTNUMBERSTATUS
[nak , ack] [auto[0]] * -- -- 24


Covered bins
cp_pid   cp_dir   cp_endp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
nak auto[1] endpoints[0x0] 14 1 T112 1 T308 1 T309 2
nak auto[1] endpoints[0x1] 24 1 T30 1 T109 1 T310 2
nak auto[1] endpoints[0x2] 17 1 T311 1 T308 2 T312 1
nak auto[1] endpoints[0x3] 8 1 T313 1 T314 1 T315 1
nak auto[1] endpoints[0x4] 15 1 T109 2 T316 1 T317 1
nak auto[1] endpoints[0x5] 15 1 T30 1 T308 1 T309 1
nak auto[1] endpoints[0x6] 9 1 T112 1 T316 1 T318 2
nak auto[1] endpoints[0x7] 13 1 T30 1 T112 1 T313 1
nak auto[1] endpoints[0x8] 10 1 T112 1 T313 1 T308 1
nak auto[1] endpoints[0x9] 20 1 T316 1 T309 2 T319 1
nak auto[1] endpoints[0xa] 10 1 T30 1 T313 1 T310 1
nak auto[1] endpoints[0xb] 15 1 T316 1 T319 1 T317 3
ack auto[1] endpoints[0x0] 2929 1 T30 1 T17 1 T4 4
ack auto[1] endpoints[0x1] 3355 1 T17 1 T151 1 T152 13
ack auto[1] endpoints[0x2] 3289 1 T17 1 T65 10 T107 7
ack auto[1] endpoints[0x3] 3266 1 T30 1 T17 1 T33 1
ack auto[1] endpoints[0x4] 3182 1 T17 1 T105 46 T153 10
ack auto[1] endpoints[0x5] 3238 1 T17 1 T4 4 T105 30
ack auto[1] endpoints[0x6] 2983 1 T28 2 T17 1 T4 4
ack auto[1] endpoints[0x7] 3478 1 T17 1 T23 1 T4 4
ack auto[1] endpoints[0x8] 3260 1 T29 1 T30 2 T17 1
ack auto[1] endpoints[0x9] 3308 1 T30 1 T17 1 T9 1
ack auto[1] endpoints[0xa] 3209 1 T17 1 T31 10 T65 11
ack auto[1] endpoints[0xb] 3114 1 T30 1 T17 1 T4 4
data1 auto[0] endpoints[0x0] 2429 1 T30 2 T48 1 T66 4
data1 auto[0] endpoints[0x1] 3122 1 T151 1 T52 4 T152 6
data1 auto[0] endpoints[0x2] 2576 1 T30 2 T32 5 T65 6
data1 auto[0] endpoints[0x3] 2442 1 T30 1 T4 1 T46 1
data1 auto[0] endpoints[0x4] 3523 1 T109 2 T105 19 T153 4
data1 auto[0] endpoints[0x5] 2010 1 T4 2 T55 3 T105 19
data1 auto[0] endpoints[0x6] 1420 1 T28 2 T30 1 T71 1
data1 auto[0] endpoints[0x7] 1989 1 T4 2 T6 12 T107 2
data1 auto[0] endpoints[0x8] 2409 1 T20 5 T70 5 T5 7
data1 auto[0] endpoints[0x9] 2418 1 T4 2 T66 4 T107 3
data1 auto[0] endpoints[0xa] 3589 1 T30 3 T152 4 T105 16
data1 auto[0] endpoints[0xb] 1989 1 T66 1 T107 3 T105 18
data1 auto[1] endpoints[0x0] 1565 1 T30 1 T4 3 T48 1
data1 auto[1] endpoints[0x1] 1851 1 T30 1 T151 1 T152 6
data1 auto[1] endpoints[0x2] 1826 1 T65 6 T107 4 T111 1
data1 auto[1] endpoints[0x3] 1807 1 T30 1 T4 3 T46 1
data1 auto[1] endpoints[0x4] 1763 1 T109 2 T105 23 T153 6
data1 auto[1] endpoints[0x5] 1790 1 T4 2 T105 15 T184 10
data1 auto[1] endpoints[0x6] 1613 1 T4 3 T5 8 T47 1
data1 auto[1] endpoints[0x7] 1952 1 T30 1 T4 2 T65 9
data1 auto[1] endpoints[0x8] 1804 1 T30 2 T5 9 T161 2
data1 auto[1] endpoints[0x9] 1819 1 T4 2 T66 4 T107 3
data1 auto[1] endpoints[0xa] 1797 1 T31 9 T65 7 T152 8
data1 auto[1] endpoints[0xb] 1684 1 T4 3 T66 7 T107 4
data0 auto[0] endpoints[0x0] 3208 1 T2 1 T17 1 T4 4
data0 auto[0] endpoints[0x1] 3846 1 T3 1 T30 1 T17 1
data0 auto[0] endpoints[0x2] 3520 1 T30 1 T17 1 T21 1
data0 auto[0] endpoints[0x3] 3284 1 T17 1 T33 1 T4 3
data0 auto[0] endpoints[0x4] 4371 1 T30 1 T17 1 T307 1
data0 auto[0] endpoints[0x5] 2847 1 T30 2 T17 1 T4 2
data0 auto[0] endpoints[0x6] 2337 1 T28 3 T17 1 T4 4
data0 auto[0] endpoints[0x7] 2832 1 T30 2 T17 1 T23 1
data0 auto[0] endpoints[0x8] 3288 1 T30 1 T17 1 T20 6
data0 auto[0] endpoints[0x9] 3364 1 T17 1 T24 1 T9 1
data0 auto[0] endpoints[0xa] 4412 1 T17 1 T320 1 T166 2
data0 auto[0] endpoints[0xb] 2750 1 T30 1 T17 1 T4 4
data0 auto[1] endpoints[0x0] 1443 1 T30 1 T17 1 T4 1
data0 auto[1] endpoints[0x1] 1579 1 T17 1 T152 7 T109 1
data0 auto[1] endpoints[0x2] 1517 1 T30 1 T17 1 T65 4
data0 auto[1] endpoints[0x3] 1518 1 T17 1 T33 1 T4 1
data0 auto[1] endpoints[0x4] 1530 1 T17 1 T109 1 T105 23
data0 auto[1] endpoints[0x5] 1536 1 T30 1 T17 1 T4 2
data0 auto[1] endpoints[0x6] 1425 1 T28 2 T17 1 T4 1
data0 auto[1] endpoints[0x7] 1672 1 T30 2 T17 1 T23 1
data0 auto[1] endpoints[0x8] 1531 1 T29 1 T30 1 T17 1
data0 auto[1] endpoints[0x9] 1541 1 T30 4 T17 1 T24 1
data0 auto[1] endpoints[0xa] 1539 1 T30 1 T17 1 T31 9
data0 auto[1] endpoints[0xb] 1478 1 T30 1 T17 1 T4 1