Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8001 1 T20 3 T23 1 T6 1
auto[1] 53756 1 T18 7 T19 14 T29 12


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 53650 1 T18 7 T19 14 T20 3
auto[1] 8107 1 T31 1 T6 33 T113 5


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55519 1 T18 7 T19 14 T20 1
auto[1] 6238 1 T20 2 T32 1 T103 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4260 1 T6 5 T322 3 T113 2
pkt_types[PidTypeInToken] 57497 1 T18 7 T19 14 T20 3


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1203 1 T6 1 T322 2 T369 2
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 829 1 T322 1 T114 13 T115 2
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 100 1 T113 1 T187 3 T394 2
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 13 1 T449 2 T498 1 T370 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1277 1 T6 1 T113 1 T140 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 713 1 T114 21 T115 21 T116 13
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 106 1 T6 3 T393 1 T389 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 19 1 T375 1 T387 1 T547 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3432 1 T20 1 T23 1 T322 3
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2353 1 T20 2 T140 1 T114 48
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 37 1 T113 3 T189 1 T487 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 34 1 T487 1 T420 1 T431 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41616 1 T18 7 T19 14 T29 12
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2227 1 T32 1 T103 1 T113 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7748 1 T31 1 T6 30 T102 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 50 1 T113 1 T140 1 T389 1

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