Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
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Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 7251 1 T36 4 T4 2 T65 147
auto[1] 55069 1 T28 2 T29 1 T30 18


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 54383 1 T28 2 T29 1 T30 18
auto[1] 7937 1 T18 1 T21 1 T4 7


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 55540 1 T28 2 T29 1 T30 18
auto[1] 6780 1 T36 4 T18 2 T22 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
ignore_pre[PidTypePre] 4317 1 T36 1 T18 1 T4 3
pkt_types[PidTypeInToken] 58003 1 T28 2 T29 1 T30 18


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pid   cp_in_enable   cp_in_iso   cp_in_stall   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1056 1 T65 15 T114 22 T181 1
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 740 1 T65 19 T114 17 T115 9
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 92 1 T4 2 T181 4 T365 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 18 1 T437 1 T486 1 T463 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1359 1 T36 1 T4 1 T65 15
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 954 1 T65 27 T265 1 T114 16
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 84 1 T181 1 T164 3 T365 4
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 14 1 T18 1 T366 1 T407 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3097 1 T65 57 T265 2 T114 37
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2149 1 T36 4 T65 56 T113 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 45 1 T447 2 T492 1 T402 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 54 1 T113 1 T437 1 T374 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 42223 1 T28 2 T29 1 T30 18
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2805 1 T18 1 T22 1 T65 56
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7584 1 T21 1 T4 5 T107 32
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 46 1 T418 1 T428 2 T405 1