Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.31	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	54	5	49	90.74

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	5	49	90.74	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20644	1			T4	86		T5	53		T50	1
solo	72983	1			T1	1		T17	1		T18	11
empty	4562	1			T2	1		T24	7		T30	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20677	1			T4	86		T49	2		T5	53
solo	31806	1			T2	1		T20	9		T23	1
empty	45824	1			T1	1		T17	1		T18	11

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75344

1

T1

1

T17

1

T18

11

setup

23079

1

T2

1

T20

9

T23

1

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rx

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	53	1			T51	1		T272	1		T178	1
solo	154	1			T24	1		T30	1		T66	1
empty	82800	1			T1	1		T2	1		T17	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	5	49	90.74	5

Automatically Generated Cross Bins for cr_fifo_X_pid

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[solo]	[full]	[solo]	[out]	0	1	1
[solo]	[empty]	[solo , empty]	[out]	--	--	2
[empty]	[empty]	[full , solo]	[setup]	--	--	2

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	full	out	1	1			T273	1		-	-		-	-
full	full	full	setup	3	1			T274	1		T275	1		T276	1
full	full	solo	out	2	1			T277	1		T278	1		-	-
full	full	solo	setup	3	1			T279	1		T280	1		T281	1
full	full	empty	out	15890	1			T4	69		T5	53		T6	34
full	full	empty	setup	4689	1			T4	17		T6	4		T153	21
full	solo	full	out	4	1			T282	1		T283	1		T284	1
full	solo	full	setup	1	1			T285	1		-	-		-	-
full	solo	solo	out	1	1			T286	1		-	-		-	-
full	solo	solo	setup	7	1			T287	1		T288	1		T289	1
full	solo	empty	out	6	1			T290	1		T291	1		T292	1
full	solo	empty	setup	2	1			T293	1		T294	1		-	-
full	empty	full	out	4	1			T51	1		T295	1		T296	1
full	empty	full	setup	3	1			T297	1		T298	1		T299	1
full	empty	solo	out	5	1			T300	1		T301	1		T302	1
full	empty	solo	setup	8	1			T52	1		T55	1		T303	1
full	empty	empty	out	1	1			T304	1		-	-		-	-
full	empty	empty	setup	9	1			T49	1		T52	1		T305	1
solo	full	full	out	3	1			T272	1		T306	1		T307	1
solo	full	full	setup	3	1			T308	1		T309	1		T310	1
solo	full	solo	setup	1	1			T311	1		-	-		-	-
solo	full	empty	out	9	1			T50	1		T54	1		T312	1
solo	full	empty	setup	5	1			T313	1		T314	1		T315	1
solo	solo	full	out	3	1			T316	1		T317	1		T318	1
solo	solo	full	setup	7	1			T319	1		T320	1		T321	1
solo	solo	solo	out	10	1			T24	1		T50	1		T54	1
solo	solo	solo	setup	8	1			T50	1		T54	1		T312	1
solo	solo	empty	out	8180	1			T103	1		T322	3		T113	4
solo	solo	empty	setup	7942	1			T20	9		T23	1		T72	1
solo	empty	full	out	4	1			T323	1		T324	1		T325	1
solo	empty	full	setup	2	1			T178	1		T326	1		-	-
solo	empty	solo	setup	78	1			T51	1		T272	1		T327	1
solo	empty	empty	setup	1963	1			T2	1		T24	1		T82	1
empty	full	full	out	2	1			T328	1		T329	1		-	-
empty	full	full	setup	1	1			T330	1		-	-		-	-
empty	full	solo	out	3	1			T182	1		T331	1		T332	1
empty	full	solo	setup	3	1			T333	1		T334	1		T335	1
empty	full	empty	out	7	1			T336	1		T337	1		T338	1
empty	full	empty	setup	1	1			T339	1		-	-		-	-
empty	solo	full	out	5	1			T340	1		T341	1		T342	1
empty	solo	full	setup	4	1			T343	1		T344	1		T345	1
empty	solo	solo	out	1	1			T346	1		-	-		-	-
empty	solo	solo	setup	5	1			T180	1		T347	1		T348	1
empty	solo	empty	out	43658	1			T1	1		T17	1		T18	11
empty	solo	empty	setup	5	1			T179	1		T349	1		T350	1
empty	empty	full	out	3	1			T351	1		T352	1		T353	1
empty	empty	solo	out	3	1			T354	1		T355	1		T356	1
empty	empty	empty	out	241	1			T30	1		T41	129		T66	1
empty	empty	empty	setup	145	1			T184	1		T185	1		T357	1