Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.46	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	39	15	27.78

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	39	15	27.78	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19466	1			T4	28		T5	32		T6	44
solo	75040	1			T3	1		T34	1		T28	5
empty	3757	1			T2	1		T36	1		T18	4

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19460	1			T4	28		T5	32		T6	44
solo	31823	1			T2	1		T36	5		T18	4
empty	47135	1			T3	1		T34	1		T28	5

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75985

1

T3

1

T34

1

T28

5

setup

22540

1

T2

1

T36

2

T18

4

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
full	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

solo

30

1

T20

1

T32

1

T70

1

empty

83361

1

T2

1

T3

1

T34

1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	39	15	27.78	39

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo]	*	*	--	--	6
[full]	[empty]	[full]	*	--	--	2
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full]	*	--	--	2
[empty]	[full , solo]	[full , solo]	*	--	--	8
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[empty]	[solo , empty]	[out]	--	--	2
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[solo , empty]	[out]	--	--	2
[empty]	[full , solo]	[empty]	[setup]	--	--	2

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	empty	out	14879	1			T4	15		T5	28		T6	24
full	full	empty	setup	4558	1			T4	13		T5	4		T6	20
full	empty	solo	setup	3	1			T297	1		T298	1		T299	1
full	empty	empty	setup	1	1			T300	1		-	-		-	-
solo	full	empty	out	5	1			T52	1		T53	1		T54	1
solo	solo	solo	out	5	1			T52	1		T53	1		T54	1
solo	solo	solo	setup	5	1			T52	1		T53	1		T54	1
solo	solo	empty	out	8169	1			T36	3		T65	151		T166	1
solo	solo	empty	setup	8326	1			T36	1		T65	181		T166	1
solo	empty	solo	setup	3	1			T301	1		T302	1		T303	1
solo	empty	empty	setup	2025	1			T2	1		T36	1		T18	4
empty	full	empty	out	2	1			T56	1		T304	1		-	-
empty	solo	empty	out	44926	1			T3	1		T34	1		T28	5
empty	empty	empty	out	251	1			T20	1		T32	1		T45	139
empty	empty	empty	setup	170	1			T235	1		T305	1		T306	1