Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	171553	1			T1	4		T2	6		T3	7
all_pins[1]	171553	1			T1	4		T2	6		T3	7
all_pins[2]	171553	1			T1	4		T2	6		T3	7
all_pins[3]	171553	1			T1	4		T2	6		T3	7
all_pins[4]	171553	1			T1	4		T2	6		T3	7
all_pins[5]	171553	1			T1	4		T2	6		T3	7
all_pins[6]	171553	1			T1	4		T2	6		T3	7
all_pins[7]	171553	1			T1	4		T2	6		T3	7
all_pins[8]	171553	1			T1	4		T2	6		T3	7
all_pins[9]	171553	1			T1	4		T2	6		T3	7
all_pins[10]	171553	1			T1	4		T2	6		T3	7
all_pins[11]	171553	1			T1	4		T2	6		T3	7
all_pins[12]	171553	1			T1	4		T2	6		T3	7
all_pins[13]	171553	1			T1	4		T2	6		T3	7
all_pins[14]	171553	1			T1	4		T2	6		T3	7
all_pins[15]	171553	1			T1	4		T2	6		T3	7
all_pins[16]	171553	1			T1	4		T2	6		T3	7
all_pins[17]	171553	1			T1	4		T2	6		T3	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5487333	1			T1	128		T2	191		T3	222
values[0x1]	2363	1			T2	1		T3	2		T17	1
transitions[0x0=>0x1]	2074	1			T2	1		T3	2		T17	1
transitions[0x1=>0x0]	2074	1			T2	1		T3	2		T17	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	171438	1			T1	4		T2	6		T3	7
all_pins[0]	values[0x1]	115	1			T233	1		T367	1		T368	1
all_pins[0]	transitions[0x0=>0x1]	100	1			T233	1		T367	1		T368	1
all_pins[0]	transitions[0x1=>0x0]	868	1			T29	12		T33	1		T8	1
all_pins[1]	values[0x0]	170670	1			T1	4		T2	6		T3	7
all_pins[1]	values[0x1]	883	1			T29	12		T33	1		T8	1
all_pins[1]	transitions[0x0=>0x1]	876	1			T29	12		T33	1		T8	1
all_pins[1]	transitions[0x1=>0x0]	115	1			T21	1		T60	1		T61	1
all_pins[2]	values[0x0]	171431	1			T1	4		T2	6		T3	7
all_pins[2]	values[0x1]	122	1			T21	1		T60	1		T61	1
all_pins[2]	transitions[0x0=>0x1]	100	1			T21	1		T60	1		T61	1
all_pins[2]	transitions[0x1=>0x0]	40	1			T41	1		T358	1		T360	1
all_pins[3]	values[0x0]	171491	1			T1	4		T2	6		T3	7
all_pins[3]	values[0x1]	62	1			T41	1		T209	1		T210	2
all_pins[3]	transitions[0x0=>0x1]	47	1			T41	1		T209	1		T210	2
all_pins[3]	transitions[0x1=>0x0]	55	1			T42	1		T207	2		T210	1
all_pins[4]	values[0x0]	171483	1			T1	4		T2	6		T3	7
all_pins[4]	values[0x1]	70	1			T42	1		T207	2		T210	1
all_pins[4]	transitions[0x0=>0x1]	44	1			T42	1		T207	2		T358	3
all_pins[4]	transitions[0x1=>0x0]	51	1			T207	1		T209	3		T210	1
all_pins[5]	values[0x0]	171476	1			T1	4		T2	6		T3	7
all_pins[5]	values[0x1]	77	1			T207	1		T209	3		T210	2
all_pins[5]	transitions[0x0=>0x1]	69	1			T207	1		T209	3		T210	1
all_pins[5]	transitions[0x1=>0x0]	105	1			T57	1		T64	1		T65	1
all_pins[6]	values[0x0]	171440	1			T1	4		T2	6		T3	7
all_pins[6]	values[0x1]	113	1			T57	1		T64	1		T65	1
all_pins[6]	transitions[0x0=>0x1]	102	1			T57	1		T64	1		T65	1
all_pins[6]	transitions[0x1=>0x0]	57	1			T46	1		T47	1		T48	1
all_pins[7]	values[0x0]	171485	1			T1	4		T2	6		T3	7
all_pins[7]	values[0x1]	68	1			T46	1		T47	1		T48	1
all_pins[7]	transitions[0x0=>0x1]	48	1			T46	1		T47	1		T48	1
all_pins[7]	transitions[0x1=>0x0]	76	1			T49	1		T52	1		T55	1
all_pins[8]	values[0x0]	171457	1			T1	4		T2	6		T3	7
all_pins[8]	values[0x1]	96	1			T49	1		T52	1		T55	1
all_pins[8]	transitions[0x0=>0x1]	77	1			T49	1		T52	1		T55	1
all_pins[8]	transitions[0x1=>0x0]	58	1			T3	2		T58	2		T59	2
all_pins[9]	values[0x0]	171476	1			T1	4		T2	6		T3	5
all_pins[9]	values[0x1]	77	1			T3	2		T58	2		T59	2
all_pins[9]	transitions[0x0=>0x1]	63	1			T3	2		T58	2		T59	2
all_pins[9]	transitions[0x1=>0x0]	46	1			T207	3		T209	1		T360	1
all_pins[10]	values[0x0]	171493	1			T1	4		T2	6		T3	7
all_pins[10]	values[0x1]	60	1			T207	3		T209	1		T359	1
all_pins[10]	transitions[0x0=>0x1]	44	1			T207	1		T359	1		T361	1
all_pins[10]	transitions[0x1=>0x0]	99	1			T69	1		T70	1		T71	1
all_pins[11]	values[0x0]	171438	1			T1	4		T2	6		T3	7
all_pins[11]	values[0x1]	115	1			T69	1		T70	1		T71	1
all_pins[11]	transitions[0x0=>0x1]	96	1			T69	1		T70	1		T71	1
all_pins[11]	transitions[0x1=>0x0]	80	1			T72	1		T73	1		T75	1
all_pins[12]	values[0x0]	171454	1			T1	4		T2	6		T3	7
all_pins[12]	values[0x1]	99	1			T72	1		T73	1		T75	1
all_pins[12]	transitions[0x0=>0x1]	71	1			T72	1		T73	1		T75	1
all_pins[12]	transitions[0x1=>0x0]	90	1			T17	1		T78	1		T79	1
all_pins[13]	values[0x0]	171435	1			T1	4		T2	6		T3	7
all_pins[13]	values[0x1]	118	1			T17	1		T78	1		T79	1
all_pins[13]	transitions[0x0=>0x1]	106	1			T17	1		T78	1		T79	1
all_pins[13]	transitions[0x1=>0x0]	60	1			T207	6		T359	4		T360	1
all_pins[14]	values[0x0]	171481	1			T1	4		T2	6		T3	7
all_pins[14]	values[0x1]	72	1			T207	6		T359	4		T360	3
all_pins[14]	transitions[0x0=>0x1]	48	1			T207	4		T359	3		T360	3
all_pins[14]	transitions[0x1=>0x0]	47	1			T209	1		T359	1		T360	2
all_pins[15]	values[0x0]	171482	1			T1	4		T2	6		T3	7
all_pins[15]	values[0x1]	71	1			T207	2		T209	1		T359	2
all_pins[15]	transitions[0x0=>0x1]	53	1			T207	2		T359	2		T360	1
all_pins[15]	transitions[0x1=>0x0]	72	1			T30	4		T66	4		T67	4
all_pins[16]	values[0x0]	171463	1			T1	4		T2	6		T3	7
all_pins[16]	values[0x1]	90	1			T30	4		T66	4		T67	4
all_pins[16]	transitions[0x0=>0x1]	75	1			T30	4		T66	4		T67	4
all_pins[16]	transitions[0x1=>0x0]	40	1			T2	1		T56	1		T209	1
all_pins[17]	values[0x0]	171498	1			T1	4		T2	5		T3	7
all_pins[17]	values[0x1]	55	1			T2	1		T56	1		T209	1
all_pins[17]	transitions[0x0=>0x1]	55	1			T2	1		T56	1		T209	1