Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	117162	1		T2	4		T3	2		T4	2
all_pins[1]	117162	1		T2	4		T3	2		T4	2
all_pins[2]	117162	1		T2	4		T3	2		T4	2
all_pins[3]	117162	1		T2	4		T3	2		T4	2
all_pins[4]	117162	1		T2	4		T3	2		T4	2
all_pins[5]	117162	1		T2	4		T3	2		T4	2
all_pins[6]	117162	1		T2	4		T3	2		T4	2
all_pins[7]	117162	1		T2	4		T3	2		T4	2
all_pins[8]	117162	1		T2	4		T3	2		T4	2
all_pins[9]	117162	1		T2	4		T3	2		T4	2
all_pins[10]	117162	1		T2	4		T3	2		T4	2
all_pins[11]	117162	1		T2	4		T3	2		T4	2
all_pins[12]	117162	1		T2	4		T3	2		T4	2
all_pins[13]	117162	1		T2	4		T3	2		T4	2
all_pins[14]	117162	1		T2	4		T3	2		T4	2
all_pins[15]	117162	1		T2	4		T3	2		T4	2
all_pins[16]	117162	1		T2	4		T3	2		T4	2
all_pins[17]	117162	1		T2	4		T3	2		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2107021	1		T2	72		T3	36		T4	36
values[0x1]	1895	1		T5	1		T34	1		T35	1
transitions[0x0=>0x1]	1628	1		T5	1		T34	1		T35	1
transitions[0x1=>0x0]	1643	1		T5	1		T34	1		T35	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	117010	1		T2	4		T3	2		T4	2
all_pins[0]	values[0x1]	152	1		T75	1		T76	1		T242	1
all_pins[0]	transitions[0x0=>0x1]	138	1		T75	1		T76	1		T242	1
all_pins[0]	transitions[0x1=>0x0]	669	1		T5	1		T77	1		T78	1
all_pins[1]	values[0x0]	116479	1		T2	4		T3	2		T4	2
all_pins[1]	values[0x1]	683	1		T5	1		T77	1		T78	1
all_pins[1]	transitions[0x0=>0x1]	671	1		T5	1		T77	1		T78	1
all_pins[1]	transitions[0x1=>0x0]	95	1		T8	1		T9	1		T11	1
all_pins[2]	values[0x0]	117055	1		T2	4		T3	2		T4	2
all_pins[2]	values[0x1]	107	1		T8	1		T9	1		T11	1
all_pins[2]	transitions[0x0=>0x1]	93	1		T8	1		T9	1		T11	1
all_pins[2]	transitions[0x1=>0x0]	56	1		T82	1		T79	1		T83	1
all_pins[3]	values[0x0]	117092	1		T2	4		T3	2		T4	2
all_pins[3]	values[0x1]	70	1		T82	3		T79	1		T83	2
all_pins[3]	transitions[0x0=>0x1]	51	1		T82	3		T79	1		T83	1
all_pins[3]	transitions[0x1=>0x0]	42	1		T79	2		T280	3		T288	2
all_pins[4]	values[0x0]	117101	1		T2	4		T3	2		T4	2
all_pins[4]	values[0x1]	61	1		T79	2		T83	1		T280	3
all_pins[4]	transitions[0x0=>0x1]	49	1		T79	2		T280	3		T288	3
all_pins[4]	transitions[0x1=>0x0]	52	1		T82	4		T281	1		T287	2
all_pins[5]	values[0x0]	117098	1		T2	4		T3	2		T4	2
all_pins[5]	values[0x1]	64	1		T82	4		T83	1		T281	1
all_pins[5]	transitions[0x0=>0x1]	44	1		T82	4		T281	1		T287	2
all_pins[5]	transitions[0x1=>0x0]	43	1		T79	3		T282	2		T288	3
all_pins[6]	values[0x0]	117099	1		T2	4		T3	2		T4	2
all_pins[6]	values[0x1]	63	1		T79	3		T83	1		T282	2
all_pins[6]	transitions[0x0=>0x1]	49	1		T79	2		T83	1		T282	2
all_pins[6]	transitions[0x1=>0x0]	45	1		T79	1		T81	1		T83	2
all_pins[7]	values[0x0]	117103	1		T2	4		T3	2		T4	2
all_pins[7]	values[0x1]	59	1		T79	2		T81	1		T83	2
all_pins[7]	transitions[0x0=>0x1]	42	1		T81	1		T83	2		T280	1
all_pins[7]	transitions[0x1=>0x0]	44	1		T81	1		T83	1		T280	1
all_pins[8]	values[0x0]	117101	1		T2	4		T3	2		T4	2
all_pins[8]	values[0x1]	61	1		T79	2		T81	1		T83	1
all_pins[8]	transitions[0x0=>0x1]	48	1		T79	1		T81	1		T83	1
all_pins[8]	transitions[0x1=>0x0]	44	1		T82	2		T79	2		T84	1
all_pins[9]	values[0x0]	117105	1		T2	4		T3	2		T4	2
all_pins[9]	values[0x1]	57	1		T82	2		T79	3		T84	1
all_pins[9]	transitions[0x0=>0x1]	47	1		T82	2		T79	3		T84	1
all_pins[9]	transitions[0x1=>0x0]	44	1		T81	1		T84	2		T83	2
all_pins[10]	values[0x0]	117108	1		T2	4		T3	2		T4	2
all_pins[10]	values[0x1]	54	1		T81	1		T84	2		T83	3
all_pins[10]	transitions[0x0=>0x1]	48	1		T81	1		T84	2		T83	3
all_pins[10]	transitions[0x1=>0x0]	91	1		T34	1		T35	1		T36	1
all_pins[11]	values[0x0]	117065	1		T2	4		T3	2		T4	2
all_pins[11]	values[0x1]	97	1		T34	1		T35	1		T36	1
all_pins[11]	transitions[0x0=>0x1]	82	1		T34	1		T35	1		T36	1
all_pins[11]	transitions[0x1=>0x0]	47	1		T79	2		T81	1		T84	2
all_pins[12]	values[0x0]	117100	1		T2	4		T3	2		T4	2
all_pins[12]	values[0x1]	62	1		T79	2		T81	1		T84	2
all_pins[12]	transitions[0x0=>0x1]	45	1		T79	2		T83	2		T280	1
all_pins[12]	transitions[0x1=>0x0]	50	1		T82	1		T79	2		T281	2
all_pins[13]	values[0x0]	117095	1		T2	4		T3	2		T4	2
all_pins[13]	values[0x1]	67	1		T82	1		T79	2		T81	1
all_pins[13]	transitions[0x0=>0x1]	54	1		T79	2		T81	1		T84	2
all_pins[13]	transitions[0x1=>0x0]	44	1		T79	1		T83	2		T280	2
all_pins[14]	values[0x0]	117105	1		T2	4		T3	2		T4	2
all_pins[14]	values[0x1]	57	1		T82	1		T79	1		T83	2
all_pins[14]	transitions[0x0=>0x1]	51	1		T82	1		T79	1		T83	2
all_pins[14]	transitions[0x1=>0x0]	50	1		T79	2		T81	2		T281	1
all_pins[15]	values[0x0]	117106	1		T2	4		T3	2		T4	2
all_pins[15]	values[0x1]	56	1		T79	2		T81	2		T281	1
all_pins[15]	transitions[0x0=>0x1]	35	1		T79	2		T281	1		T282	2
all_pins[15]	transitions[0x1=>0x0]	40	1		T83	4		T280	1		T282	1
all_pins[16]	values[0x0]	117101	1		T2	4		T3	2		T4	2
all_pins[16]	values[0x1]	61	1		T81	2		T83	4		T280	1
all_pins[16]	transitions[0x0=>0x1]	45	1		T81	1		T83	2		T280	1
all_pins[16]	transitions[0x1=>0x0]	48	1		T79	1		T81	1		T280	1
all_pins[17]	values[0x0]	117098	1		T2	4		T3	2		T4	2
all_pins[17]	values[0x1]	64	1		T79	1		T81	2		T83	2
all_pins[17]	transitions[0x0=>0x1]	36	1		T81	1		T83	1		T280	1
all_pins[17]	transitions[0x1=>0x0]	139	1		T75	1		T76	1		T242	1