Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
98.94 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 22 0 22 100.00
Crosses 72 1 71 98.61


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr_pin 18 0 18 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 72 1 71 98.61 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 18 0 18 100.00


User Defined Bins for cp_intr_pin

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_pins[0] 172056 1 T1 7 T2 4 T3 5
all_pins[1] 172056 1 T1 7 T2 4 T3 5
all_pins[2] 172056 1 T1 7 T2 4 T3 5
all_pins[3] 172056 1 T1 7 T2 4 T3 5
all_pins[4] 172056 1 T1 7 T2 4 T3 5
all_pins[5] 172056 1 T1 7 T2 4 T3 5
all_pins[6] 172056 1 T1 7 T2 4 T3 5
all_pins[7] 172056 1 T1 7 T2 4 T3 5
all_pins[8] 172056 1 T1 7 T2 4 T3 5
all_pins[9] 172056 1 T1 7 T2 4 T3 5
all_pins[10] 172056 1 T1 7 T2 4 T3 5
all_pins[11] 172056 1 T1 7 T2 4 T3 5
all_pins[12] 172056 1 T1 7 T2 4 T3 5
all_pins[13] 172056 1 T1 7 T2 4 T3 5
all_pins[14] 172056 1 T1 7 T2 4 T3 5
all_pins[15] 172056 1 T1 7 T2 4 T3 5
all_pins[16] 172056 1 T1 7 T2 4 T3 5
all_pins[17] 172056 1 T1 7 T2 4 T3 5


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x0] 5503465 1 T1 222 T2 128 T3 159
values[0x1] 2327 1 T1 2 T3 1 T34 1
transitions[0x0=>0x1] 2019 1 T1 2 T3 1 T34 1
transitions[0x1=>0x0] 2019 1 T1 2 T3 1 T34 1


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 72 1 71 98.61 1


Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTNUMBERSTATUS
[all_pins[17]] [transitions[0x1=>0x0]] 0 1 1


Covered bins
cp_intr_pin   cp_intr_pin_value   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_pins[0] values[0x0] 171948 1 T1 7 T2 4 T3 5
all_pins[0] values[0x1] 108 1 T85 1 T337 1 T338 1
all_pins[0] transitions[0x0=>0x1] 96 1 T85 1 T337 1 T338 1
all_pins[0] transitions[0x1=>0x0] 856 1 T17 12 T23 1 T49 1
all_pins[1] values[0x0] 171188 1 T1 7 T2 4 T3 5
all_pins[1] values[0x1] 868 1 T17 12 T23 1 T49 1
all_pins[1] transitions[0x0=>0x1] 855 1 T17 12 T23 1 T49 1
all_pins[1] transitions[0x1=>0x0] 108 1 T35 1 T63 1 T64 1
all_pins[2] values[0x0] 171935 1 T1 7 T2 4 T3 5
all_pins[2] values[0x1] 121 1 T35 1 T63 1 T64 1
all_pins[2] transitions[0x0=>0x1] 103 1 T35 1 T63 1 T64 1
all_pins[2] transitions[0x1=>0x0] 43 1 T45 1 T226 1 T227 1
all_pins[3] values[0x0] 171995 1 T1 7 T2 4 T3 5
all_pins[3] values[0x1] 61 1 T45 1 T226 2 T227 1
all_pins[3] transitions[0x0=>0x1] 47 1 T45 1 T226 1 T327 2
all_pins[3] transitions[0x1=>0x0] 53 1 T44 1 T226 1 T321 4
all_pins[4] values[0x0] 171989 1 T1 7 T2 4 T3 5
all_pins[4] values[0x1] 67 1 T44 1 T226 2 T227 1
all_pins[4] transitions[0x0=>0x1] 40 1 T44 1 T226 1 T227 1
all_pins[4] transitions[0x1=>0x0] 56 1 T226 3 T227 1 T321 1
all_pins[5] values[0x0] 171973 1 T1 7 T2 4 T3 5
all_pins[5] values[0x1] 83 1 T226 4 T227 1 T321 5
all_pins[5] transitions[0x0=>0x1] 58 1 T226 2 T227 1 T321 5
all_pins[5] transitions[0x1=>0x0] 110 1 T67 1 T68 1 T69 1
all_pins[6] values[0x0] 171921 1 T1 7 T2 4 T3 5
all_pins[6] values[0x1] 135 1 T67 1 T68 1 T69 1
all_pins[6] transitions[0x0=>0x1] 117 1 T67 1 T68 1 T69 1
all_pins[6] transitions[0x1=>0x0] 47 1 T3 1 T50 1 T51 1
all_pins[7] values[0x0] 171991 1 T1 7 T2 4 T3 4
all_pins[7] values[0x1] 65 1 T3 1 T50 1 T51 1
all_pins[7] transitions[0x0=>0x1] 47 1 T3 1 T50 1 T51 1
all_pins[7] transitions[0x1=>0x0] 57 1 T58 1 T59 1 T60 1
all_pins[8] values[0x0] 171981 1 T1 7 T2 4 T3 5
all_pins[8] values[0x1] 75 1 T58 1 T59 1 T60 1
all_pins[8] transitions[0x0=>0x1] 61 1 T58 1 T59 1 T60 1
all_pins[8] transitions[0x1=>0x0] 73 1 T1 2 T61 2 T62 2
all_pins[9] values[0x0] 171969 1 T1 5 T2 4 T3 5
all_pins[9] values[0x1] 87 1 T1 2 T61 2 T62 2
all_pins[9] transitions[0x0=>0x1] 71 1 T1 2 T61 2 T62 2
all_pins[9] transitions[0x1=>0x0] 53 1 T227 2 T321 4 T322 1
all_pins[10] values[0x0] 171987 1 T1 7 T2 4 T3 5
all_pins[10] values[0x1] 69 1 T227 2 T321 4 T322 1
all_pins[10] transitions[0x0=>0x1] 53 1 T227 2 T321 4 T322 1
all_pins[10] transitions[0x1=>0x0] 98 1 T73 1 T74 1 T75 1
all_pins[11] values[0x0] 171942 1 T1 7 T2 4 T3 5
all_pins[11] values[0x1] 114 1 T73 1 T74 1 T75 1
all_pins[11] transitions[0x0=>0x1] 95 1 T73 1 T74 1 T75 1
all_pins[11] transitions[0x1=>0x0] 55 1 T76 1 T77 1 T78 1
all_pins[12] values[0x0] 171982 1 T1 7 T2 4 T3 5
all_pins[12] values[0x1] 74 1 T76 1 T77 1 T78 1
all_pins[12] transitions[0x0=>0x1] 53 1 T76 1 T77 1 T78 1
all_pins[12] transitions[0x1=>0x0] 103 1 T34 1 T82 1 T83 1
all_pins[13] values[0x0] 171932 1 T1 7 T2 4 T3 5
all_pins[13] values[0x1] 124 1 T34 1 T82 1 T83 1
all_pins[13] transitions[0x0=>0x1] 107 1 T34 1 T82 1 T83 1
all_pins[13] transitions[0x1=>0x0] 41 1 T226 3 T325 1 T326 1
all_pins[14] values[0x0] 171998 1 T1 7 T2 4 T3 5
all_pins[14] values[0x1] 58 1 T226 3 T322 1 T325 1
all_pins[14] transitions[0x0=>0x1] 40 1 T325 1 T324 1 T323 3
all_pins[14] transitions[0x1=>0x0] 49 1 T227 2 T321 1 T322 1
all_pins[15] values[0x0] 171989 1 T1 7 T2 4 T3 5
all_pins[15] values[0x1] 67 1 T226 3 T227 2 T321 1
all_pins[15] transitions[0x0=>0x1] 44 1 T321 1 T322 1 T326 3
all_pins[15] transitions[0x1=>0x0] 61 1 T20 4 T32 4 T70 4
all_pins[16] values[0x0] 171972 1 T1 7 T2 4 T3 5
all_pins[16] values[0x1] 84 1 T20 4 T32 4 T70 4
all_pins[16] transitions[0x0=>0x1] 65 1 T20 4 T32 4 T70 4
all_pins[16] transitions[0x1=>0x0] 48 1 T228 1 T321 3 T325 1
all_pins[17] values[0x0] 171989 1 T1 7 T2 4 T3 5
all_pins[17] values[0x1] 67 1 T228 1 T226 1 T227 1
all_pins[17] transitions[0x0=>0x1] 67 1 T228 1 T226 1 T227 1