Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4415	1			T23	1		T4	9		T74	4
invalid_ep[0xd]	4464	1			T4	10		T113	2		T74	4
invalid_ep[0xe]	4296	1			T4	13		T114	83		T115	52
invalid_ep[0xf]	4421	1			T4	6		T113	1		T74	4
endpoints[0x0]	13515	1			T2	1		T17	1		T19	6
endpoints[0x1]	13572	1			T19	2		T20	6		T29	2
endpoints[0x2]	11757	1			T19	2		T20	6		T29	2
endpoints[0x3]	12656	1			T19	1		T29	2		T8	2
endpoints[0x4]	12178	1			T19	2		T29	2		T32	1
endpoints[0x5]	14108	1			T19	1		T20	2		T29	2
endpoints[0x6]	12732	1			T19	2		T23	2		T29	2
endpoints[0x7]	13337	1			T19	2		T23	1		T29	2
endpoints[0x8]	13076	1			T19	1		T29	2		T31	2
endpoints[0x9]	13000	1			T1	1		T19	1		T20	4
endpoints[0xa]	13989	1			T19	6		T29	2		T34	2
endpoints[0xb]	14997	1			T18	18		T19	2		T29	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23079	1			T2	1		T20	9		T23	1
pkt_types[PidTypeOutToken]	75344	1			T1	1		T17	1		T18	11
pkt_types[PidTypeInToken]	61287	1			T18	7		T19	14		T20	3

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	923	1			T114	31		T115	14		T116	9
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	973	1			T113	1		T114	22		T115	11
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	941	1			T114	15		T115	12		T116	15
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	944	1			T113	1		T114	34		T115	19
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1611	1			T2	1		T24	7		T45	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1605	1			T20	3		T43	1		T4	4
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1535	1			T20	3		T151	4		T322	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1696	1			T4	5		T153	5		T151	2
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1584	1			T82	1		T4	4		T6	2
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1536	1			T20	1		T157	1		T6	2
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1681	1			T23	1		T49	8		T103	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1663	1			T154	1		T153	3		T158	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1666	1			T4	4		T72	1		T74	1
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1559	1			T20	2		T44	1		T151	3
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1531	1			T84	1		T184	1		T153	3
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1631	1			T153	4		T107	1		T322	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1550	1			T4	9		T74	4		T114	23
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1563	1			T4	10		T113	1		T74	4
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1525	1			T4	13		T114	30		T115	19
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1527	1			T4	6		T74	4		T140	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	6533	1			T17	1		T19	3		T24	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	5675	1			T19	1		T20	2		T29	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	4644	1			T19	1		T29	1		T528	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5017	1			T19	1		T29	1		T8	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	4742	1			T19	1		T29	1		T80	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	7164	1			T19	1		T29	1		T150	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	5497	1			T29	1		T30	11		T66	11
pkt_types[PidTypeOutToken]	endpoints[0x7]	5729	1			T19	2		T23	1		T29	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	4988	1			T19	1		T29	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	5598	1			T1	1		T19	1		T20	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	6694	1			T19	1		T29	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	6898	1			T18	11		T19	1		T29	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	983	1			T114	27		T115	20		T116	8
pkt_types[PidTypeInToken]	invalid_ep[0xd]	980	1			T140	1		T114	35		T115	18
pkt_types[PidTypeInToken]	invalid_ep[0xe]	923	1			T114	13		T115	9		T116	12
pkt_types[PidTypeInToken]	invalid_ep[0xf]	904	1			T114	26		T115	12		T116	9
pkt_types[PidTypeInToken]	endpoints[0x0]	4309	1			T19	3		T29	1		T45	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5208	1			T19	1		T20	1		T29	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4444	1			T19	1		T20	2		T29	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4860	1			T29	1		T8	1		T97	14
pkt_types[PidTypeInToken]	endpoints[0x4]	4805	1			T19	1		T29	1		T32	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4318	1			T29	1		T150	1		T6	5
pkt_types[PidTypeInToken]	endpoints[0x6]	4488	1			T19	2		T23	1		T29	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4899	1			T29	1		T4	7		T154	1
pkt_types[PidTypeInToken]	endpoints[0x8]	5309	1			T29	1		T31	1		T33	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4773	1			T29	1		T44	1		T4	7
pkt_types[PidTypeInToken]	endpoints[0xa]	4684	1			T19	5		T29	1		T34	1
pkt_types[PidTypeInToken]	endpoints[0xb]	5400	1			T18	7		T19	1		T29	1