Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4417	1			T65	87		T153	12		T113	1
invalid_ep[0xd]	4371	1			T65	70		T153	11		T114	99
invalid_ep[0xe]	4451	1			T18	1		T65	80		T153	12
invalid_ep[0xf]	4477	1			T65	80		T153	22		T114	90
endpoints[0x0]	13075	1			T2	1		T30	4		T17	2
endpoints[0x1]	14289	1			T3	1		T30	2		T36	4
endpoints[0x2]	13412	1			T34	1		T30	4		T36	3
endpoints[0x3]	13295	1			T30	2		T36	3		T17	2
endpoints[0x4]	15306	1			T30	1		T17	2		T18	1
endpoints[0x5]	12392	1			T30	3		T17	2		T4	9
endpoints[0x6]	10537	1			T28	7		T30	1		T36	5
endpoints[0x7]	12943	1			T30	5		T36	4		T17	2
endpoints[0x8]	13392	1			T29	1		T30	4		T17	2
endpoints[0x9]	13270	1			T30	4		T17	2		T18	1
endpoints[0xa]	15273	1			T30	4		T17	2		T31	18
endpoints[0xb]	12584	1			T30	2		T17	2		T18	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	22540	1			T2	1		T36	2		T18	4
pkt_types[PidTypeOutToken]	75985	1			T3	1		T34	1		T28	5
pkt_types[PidTypeInToken]	61977	1			T28	2		T29	1		T30	18

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	972	1			T65	24		T114	18		T115	7
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1001	1			T65	16		T114	29		T115	5
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1010	1			T18	1		T65	27		T114	22
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	960	1			T65	22		T114	25		T437	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1430	1			T2	1		T4	3		T65	22
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1579	1			T36	1		T65	16		T151	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1582	1			T65	19		T107	2		T157	3
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1704	1			T4	2		T65	17		T46	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1535	1			T18	1		T65	18		T153	4
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1563	1			T90	1		T65	20		T235	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1430	1			T18	1		T4	3		T65	20
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1636	1			T36	1		T4	2		T65	17
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1511	1			T5	4		T65	26		T161	2
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1614	1			T18	1		T65	29		T114	17
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1531	1			T65	25		T166	1		T152	5
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1482	1			T4	3		T65	16		T66	7
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1465	1			T65	22		T153	12		T114	16
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1481	1			T65	15		T153	11		T114	24
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1500	1			T65	21		T153	12		T114	19
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1532	1			T65	22		T153	22		T114	21
pkt_types[PidTypeOutToken]	endpoints[0x0]	5772	1			T30	2		T17	1		T4	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	6993	1			T3	1		T30	1		T17	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	6024	1			T34	1		T30	3		T17	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5710	1			T30	1		T17	1		T33	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	7782	1			T30	1		T17	1		T307	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	4883	1			T30	2		T17	1		T4	4
pkt_types[PidTypeOutToken]	endpoints[0x6]	3740	1			T28	5		T30	1		T36	3
pkt_types[PidTypeOutToken]	endpoints[0x7]	4867	1			T30	2		T17	1		T23	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5611	1			T30	1		T17	1		T20	11
pkt_types[PidTypeOutToken]	endpoints[0x9]	5661	1			T17	1		T24	1		T9	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	7977	1			T30	3		T17	1		T320	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	4987	1			T30	1		T17	1		T45	139
pkt_types[PidTypeInToken]	invalid_ep[0xc]	987	1			T65	20		T113	1		T114	30
pkt_types[PidTypeInToken]	invalid_ep[0xd]	954	1			T65	18		T114	23		T115	7
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1017	1			T65	16		T114	18		T115	11
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1016	1			T65	18		T114	17		T437	1
pkt_types[PidTypeInToken]	endpoints[0x0]	4771	1			T30	2		T17	1		T4	5
pkt_types[PidTypeInToken]	endpoints[0x1]	4645	1			T30	1		T36	3		T17	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4645	1			T30	1		T36	1		T17	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4788	1			T30	1		T36	3		T17	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4894	1			T17	1		T65	14		T109	3
pkt_types[PidTypeInToken]	endpoints[0x5]	4831	1			T30	1		T17	1		T4	5
pkt_types[PidTypeInToken]	endpoints[0x6]	4262	1			T28	2		T17	1		T4	5
pkt_types[PidTypeInToken]	endpoints[0x7]	5316	1			T30	3		T36	1		T17	1
pkt_types[PidTypeInToken]	endpoints[0x8]	5201	1			T29	1		T30	3		T17	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4929	1			T30	4		T17	1		T24	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4676	1			T30	1		T17	1		T31	18
pkt_types[PidTypeInToken]	endpoints[0xb]	5045	1			T30	1		T17	1		T18	1