Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T207	7		T209	4		T210	4
all_values[1]	284	1			T207	7		T209	4		T210	4
all_values[2]	284	1			T207	7		T209	4		T210	4
all_values[3]	284	1			T207	7		T209	4		T210	4
all_values[4]	284	1			T207	7		T209	4		T210	4
all_values[5]	284	1			T207	7		T209	4		T210	4
all_values[6]	284	1			T207	7		T209	4		T210	4
all_values[7]	284	1			T207	7		T209	4		T210	4
all_values[8]	284	1			T207	7		T209	4		T210	4
all_values[9]	284	1			T207	7		T209	4		T210	4
all_values[10]	284	1			T207	7		T209	4		T210	4
all_values[11]	284	1			T207	7		T209	4		T210	4
all_values[12]	284	1			T207	7		T209	4		T210	4
all_values[13]	284	1			T207	7		T209	4		T210	4
all_values[14]	284	1			T207	7		T209	4		T210	4
all_values[15]	284	1			T207	7		T209	4		T210	4
all_values[16]	284	1			T207	7		T209	4		T210	4
all_values[17]	284	1			T207	7		T209	4		T210	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6732

1

T207

166

T209

93

T210

96

auto[1]

2356

1

T207

58

T209

35

T210

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6162

1

T207

155

T209

88

T210

93

auto[1]

2926

1

T207

69

T209

40

T210

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5285

1

T207

133

T209

77

T210

80

auto[1]

3803

1

T207

91

T209

51

T210

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	81	1			T207	3		T209	1		T358	1
all_values[0]	auto[0]	auto[1]	auto[0]	77	1			T207	1		T209	1		T210	3
all_values[0]	auto[1]	auto[0]	auto[1]	64	1			T207	2		T209	1		T210	1
all_values[0]	auto[1]	auto[1]	auto[1]	62	1			T207	1		T209	1		T358	1
all_values[1]	auto[0]	auto[0]	auto[0]	82	1			T207	1		T209	1		T210	2
all_values[1]	auto[0]	auto[1]	auto[0]	79	1			T207	2		T209	1		T210	1
all_values[1]	auto[1]	auto[0]	auto[1]	68	1			T207	2		T209	2		T210	1
all_values[1]	auto[1]	auto[1]	auto[1]	55	1			T207	2		T359	2		T360	1
all_values[2]	auto[0]	auto[0]	auto[0]	42	1			T209	1		T361	1		T362	2
all_values[2]	auto[0]	auto[0]	auto[1]	46	1			T207	2		T358	1		T359	3
all_values[2]	auto[0]	auto[1]	auto[0]	50	1			T207	2		T209	1		T359	1
all_values[2]	auto[0]	auto[1]	auto[1]	28	1			T209	1		T210	2		T358	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1			T207	3		T210	2		T358	2
all_values[2]	auto[1]	auto[1]	auto[1]	52	1			T209	1		T359	3		T363	1
all_values[3]	auto[0]	auto[0]	auto[0]	72	1			T207	5		T209	1		T210	2
all_values[3]	auto[0]	auto[0]	auto[1]	26	1			T209	1		T360	1		T363	2
all_values[3]	auto[0]	auto[1]	auto[0]	49	1			T207	2		T358	1		T360	1
all_values[3]	auto[0]	auto[1]	auto[1]	24	1			T210	1		T358	1		T364	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1			T358	1		T359	2		T360	1
all_values[3]	auto[1]	auto[1]	auto[1]	50	1			T209	2		T210	1		T360	2
all_values[4]	auto[0]	auto[0]	auto[0]	60	1			T207	1		T209	2		T210	1
all_values[4]	auto[0]	auto[0]	auto[1]	35	1			T207	2		T210	2		T359	1
all_values[4]	auto[0]	auto[1]	auto[0]	46	1			T207	2		T361	1		T365	3
all_values[4]	auto[0]	auto[1]	auto[1]	30	1			T358	2		T360	3		T363	1
all_values[4]	auto[1]	auto[0]	auto[1]	66	1			T207	2		T209	2		T210	1
all_values[4]	auto[1]	auto[1]	auto[1]	47	1			T358	1		T360	1		T363	2
all_values[5]	auto[0]	auto[0]	auto[0]	57	1			T207	2		T210	1		T358	2
all_values[5]	auto[0]	auto[0]	auto[1]	32	1			T209	1		T359	2		T360	1
all_values[5]	auto[0]	auto[1]	auto[0]	45	1			T207	2		T358	2		T361	1
all_values[5]	auto[0]	auto[1]	auto[1]	27	1			T207	1		T209	1		T359	1
all_values[5]	auto[1]	auto[0]	auto[1]	62	1			T207	1		T209	1		T210	2
all_values[5]	auto[1]	auto[1]	auto[1]	61	1			T207	1		T209	1		T210	1
all_values[6]	auto[0]	auto[0]	auto[0]	77	1			T207	6		T209	1		T358	1
all_values[6]	auto[0]	auto[0]	auto[1]	21	1			T360	2		T363	1		T365	1
all_values[6]	auto[0]	auto[1]	auto[0]	53	1			T209	1		T210	2		T359	3
all_values[6]	auto[0]	auto[1]	auto[1]	21	1			T358	1		T361	1		T364	1
all_values[6]	auto[1]	auto[0]	auto[1]	63	1			T207	1		T209	1		T210	1
all_values[6]	auto[1]	auto[1]	auto[1]	49	1			T209	1		T210	1		T358	2
all_values[7]	auto[0]	auto[0]	auto[0]	87	1			T207	1		T209	2		T210	1
all_values[7]	auto[0]	auto[1]	auto[0]	78	1			T207	2		T210	2		T359	3
all_values[7]	auto[1]	auto[0]	auto[1]	60	1			T207	2		T358	2		T359	2
all_values[7]	auto[1]	auto[1]	auto[1]	59	1			T207	2		T209	2		T210	1
all_values[8]	auto[0]	auto[0]	auto[0]	67	1			T209	1		T210	1		T359	1
all_values[8]	auto[0]	auto[1]	auto[0]	76	1			T207	3		T209	1		T210	1
all_values[8]	auto[1]	auto[0]	auto[1]	78	1			T207	3		T209	1		T358	1
all_values[8]	auto[1]	auto[1]	auto[1]	63	1			T207	1		T209	1		T210	2
all_values[9]	auto[0]	auto[0]	auto[0]	62	1			T207	3		T209	1		T210	3
all_values[9]	auto[0]	auto[0]	auto[1]	28	1			T209	1		T360	2		T361	1
all_values[9]	auto[0]	auto[1]	auto[0]	47	1			T209	1		T210	1		T358	1
all_values[9]	auto[0]	auto[1]	auto[1]	27	1			T207	1		T360	1		T363	1
all_values[9]	auto[1]	auto[0]	auto[1]	65	1			T207	2		T209	1		T358	1
all_values[9]	auto[1]	auto[1]	auto[1]	55	1			T207	1		T359	2		T360	1
all_values[10]	auto[0]	auto[0]	auto[0]	62	1			T207	1		T209	1		T358	1
all_values[10]	auto[0]	auto[0]	auto[1]	28	1			T358	1		T359	1		T360	1
all_values[10]	auto[0]	auto[1]	auto[0]	54	1			T207	1		T209	2		T210	2
all_values[10]	auto[0]	auto[1]	auto[1]	25	1			T207	1		T360	1		T366	1
all_values[10]	auto[1]	auto[0]	auto[1]	65	1			T207	2		T210	1		T358	1
all_values[10]	auto[1]	auto[1]	auto[1]	50	1			T207	2		T209	1		T210	1
all_values[11]	auto[0]	auto[0]	auto[0]	54	1			T210	4		T358	2		T359	1
all_values[11]	auto[0]	auto[0]	auto[1]	37	1			T207	1		T209	1		T358	1
all_values[11]	auto[0]	auto[1]	auto[0]	44	1			T360	1		T363	2		T361	1
all_values[11]	auto[0]	auto[1]	auto[1]	22	1			T207	1		T209	1		T359	1
all_values[11]	auto[1]	auto[0]	auto[1]	74	1			T207	2		T359	4		T360	2
all_values[11]	auto[1]	auto[1]	auto[1]	53	1			T207	3		T209	2		T358	1
all_values[12]	auto[0]	auto[0]	auto[0]	45	1			T207	3		T209	2		T210	1
all_values[12]	auto[0]	auto[0]	auto[1]	25	1			T359	1		T360	2		T363	1
all_values[12]	auto[0]	auto[1]	auto[0]	38	1			T207	2		T360	1		T364	1
all_values[12]	auto[0]	auto[1]	auto[1]	40	1			T209	1		T210	2		T358	2
all_values[12]	auto[1]	auto[0]	auto[1]	75	1			T209	1		T358	1		T359	2
all_values[12]	auto[1]	auto[1]	auto[1]	61	1			T207	2		T210	1		T359	3
all_values[13]	auto[0]	auto[0]	auto[0]	56	1			T207	4		T209	1		T210	2
all_values[13]	auto[0]	auto[0]	auto[1]	26	1			T360	1		T363	1		T361	1
all_values[13]	auto[0]	auto[1]	auto[0]	52	1			T207	2		T209	2		T358	1
all_values[13]	auto[0]	auto[1]	auto[1]	28	1			T360	1		T361	2		T366	1
all_values[13]	auto[1]	auto[0]	auto[1]	83	1			T207	1		T210	2		T358	1
all_values[13]	auto[1]	auto[1]	auto[1]	39	1			T209	1		T358	1		T359	2
all_values[14]	auto[0]	auto[0]	auto[0]	55	1			T209	2		T210	1		T358	3
all_values[14]	auto[0]	auto[0]	auto[1]	24	1			T359	1		T361	1		T365	1
all_values[14]	auto[0]	auto[1]	auto[0]	55	1			T209	1		T210	1		T358	1
all_values[14]	auto[0]	auto[1]	auto[1]	28	1			T207	4		T359	2		T360	1
all_values[14]	auto[1]	auto[0]	auto[1]	62	1			T207	1		T209	1		T359	2
all_values[14]	auto[1]	auto[1]	auto[1]	60	1			T207	2		T210	2		T359	1
all_values[15]	auto[0]	auto[0]	auto[0]	58	1			T210	2		T358	2		T359	2
all_values[15]	auto[0]	auto[0]	auto[1]	21	1			T209	1		T360	2		T361	1
all_values[15]	auto[0]	auto[1]	auto[0]	53	1			T207	1		T209	1		T358	1
all_values[15]	auto[0]	auto[1]	auto[1]	28	1			T207	2		T365	2		T366	2
all_values[15]	auto[1]	auto[0]	auto[1]	62	1			T207	3		T210	1		T360	1
all_values[15]	auto[1]	auto[1]	auto[1]	62	1			T207	1		T209	2		T210	1
all_values[16]	auto[0]	auto[0]	auto[0]	59	1			T209	1		T210	1		T358	1
all_values[16]	auto[0]	auto[0]	auto[1]	30	1			T207	3		T358	1		T359	1
all_values[16]	auto[0]	auto[1]	auto[0]	43	1			T207	1		T358	1		T360	1
all_values[16]	auto[0]	auto[1]	auto[1]	28	1			T207	1		T209	1		T360	1
all_values[16]	auto[1]	auto[0]	auto[1]	67	1			T207	2		T209	1		T210	2
all_values[16]	auto[1]	auto[1]	auto[1]	57	1			T209	1		T210	1		T359	2
all_values[17]	auto[0]	auto[0]	auto[0]	94	1			T209	2		T358	2		T359	3
all_values[17]	auto[0]	auto[1]	auto[0]	77	1			T207	4		T210	2		T358	1
all_values[17]	auto[1]	auto[0]	auto[1]	64	1			T207	1		T210	2		T359	2
all_values[17]	auto[1]	auto[1]	auto[1]	49	1			T207	2		T209	2		T358	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal