Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1			T228	4		T226	7		T227	4
all_values[1]	290	1			T228	4		T226	7		T227	4
all_values[2]	290	1			T228	4		T226	7		T227	4
all_values[3]	290	1			T228	4		T226	7		T227	4
all_values[4]	290	1			T228	4		T226	7		T227	4
all_values[5]	290	1			T228	4		T226	7		T227	4
all_values[6]	290	1			T228	4		T226	7		T227	4
all_values[7]	290	1			T228	4		T226	7		T227	4
all_values[8]	290	1			T228	4		T226	7		T227	4
all_values[9]	290	1			T228	4		T226	7		T227	4
all_values[10]	290	1			T228	4		T226	7		T227	4
all_values[11]	290	1			T228	4		T226	7		T227	4
all_values[12]	290	1			T228	4		T226	7		T227	4
all_values[13]	290	1			T228	4		T226	7		T227	4
all_values[14]	290	1			T228	4		T226	7		T227	4
all_values[15]	290	1			T228	4		T226	7		T227	4
all_values[16]	290	1			T228	4		T226	7		T227	4
all_values[17]	290	1			T228	4		T226	7		T227	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6786

1

T228

100

T226

155

T227

82

auto[1]

2494

1

T228

28

T226

69

T227

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6377

1

T228

100

T226

155

T227

96

auto[1]

2903

1

T228

28

T226

69

T227

32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5393

1

T228

81

T226

134

T227

90

auto[1]

3887

1

T228

47

T226

90

T227

38

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	90	1			T228	3		T226	3		T321	3
all_values[0]	auto[0]	auto[1]	auto[0]	79	1			T227	1		T321	1		T322	1
all_values[0]	auto[1]	auto[0]	auto[1]	61	1			T228	1		T226	3		T321	2
all_values[0]	auto[1]	auto[1]	auto[1]	60	1			T226	1		T227	3		T321	1
all_values[1]	auto[0]	auto[0]	auto[0]	92	1			T228	2		T226	3		T227	1
all_values[1]	auto[0]	auto[1]	auto[0]	81	1			T228	1		T226	2		T227	2
all_values[1]	auto[1]	auto[0]	auto[1]	67	1			T228	1		T227	1		T321	2
all_values[1]	auto[1]	auto[1]	auto[1]	50	1			T226	2		T321	1		T322	1
all_values[2]	auto[0]	auto[0]	auto[0]	54	1			T228	1		T322	2		T323	3
all_values[2]	auto[0]	auto[0]	auto[1]	45	1			T226	1		T227	1		T321	1
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T226	1		T322	1		T324	1
all_values[2]	auto[0]	auto[1]	auto[1]	42	1			T226	2		T321	3		T325	1
all_values[2]	auto[1]	auto[0]	auto[1]	77	1			T228	3		T226	2		T227	3
all_values[2]	auto[1]	auto[1]	auto[1]	48	1			T226	1		T321	2		T322	1
all_values[3]	auto[0]	auto[0]	auto[0]	78	1			T228	1		T226	1		T321	1
all_values[3]	auto[0]	auto[0]	auto[1]	23	1			T226	1		T321	2		T324	1
all_values[3]	auto[0]	auto[1]	auto[0]	55	1			T228	3		T227	2		T322	1
all_values[3]	auto[0]	auto[1]	auto[1]	26	1			T227	1		T321	1		T325	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1			T226	2		T321	2		T322	2
all_values[3]	auto[1]	auto[1]	auto[1]	49	1			T226	3		T227	1		T321	1
all_values[4]	auto[0]	auto[0]	auto[0]	68	1			T228	2		T226	2		T227	2
all_values[4]	auto[0]	auto[0]	auto[1]	28	1			T226	1		T322	1		T326	2
all_values[4]	auto[0]	auto[1]	auto[0]	55	1			T228	1		T226	1		T321	1
all_values[4]	auto[0]	auto[1]	auto[1]	24	1			T226	1		T227	1		T321	1
all_values[4]	auto[1]	auto[0]	auto[1]	56	1			T228	1		T226	1		T321	1
all_values[4]	auto[1]	auto[1]	auto[1]	59	1			T226	1		T227	1		T321	4
all_values[5]	auto[0]	auto[0]	auto[0]	43	1			T226	1		T227	1		T326	2
all_values[5]	auto[0]	auto[0]	auto[1]	37	1			T228	1		T321	1		T322	1
all_values[5]	auto[0]	auto[1]	auto[0]	48	1			T227	2		T326	2		T324	1
all_values[5]	auto[0]	auto[1]	auto[1]	32	1			T226	3		T321	1		T322	1
all_values[5]	auto[1]	auto[0]	auto[1]	59	1			T228	1		T226	1		T227	1
all_values[5]	auto[1]	auto[1]	auto[1]	71	1			T228	2		T226	2		T321	3
all_values[6]	auto[0]	auto[0]	auto[0]	57	1			T228	4		T227	2		T321	3
all_values[6]	auto[0]	auto[0]	auto[1]	28	1			T226	2		T325	1		T326	1
all_values[6]	auto[0]	auto[1]	auto[0]	54	1			T227	2		T321	3		T322	3
all_values[6]	auto[0]	auto[1]	auto[1]	35	1			T226	3		T325	1		T326	3
all_values[6]	auto[1]	auto[0]	auto[1]	64	1			T226	2		T321	1		T325	1
all_values[6]	auto[1]	auto[1]	auto[1]	52	1			T325	1		T326	2		T324	3
all_values[7]	auto[0]	auto[0]	auto[0]	83	1			T228	1		T226	2		T227	4
all_values[7]	auto[0]	auto[1]	auto[0]	87	1			T228	1		T226	3		T321	1
all_values[7]	auto[1]	auto[0]	auto[1]	66	1			T228	2		T226	2		T321	1
all_values[7]	auto[1]	auto[1]	auto[1]	54	1			T321	1		T322	1		T326	1
all_values[8]	auto[0]	auto[0]	auto[0]	101	1			T226	3		T227	2		T322	4
all_values[8]	auto[0]	auto[1]	auto[0]	77	1			T228	2		T226	3		T321	2
all_values[8]	auto[1]	auto[0]	auto[1]	48	1			T228	1		T321	1		T325	1
all_values[8]	auto[1]	auto[1]	auto[1]	64	1			T228	1		T226	1		T227	2
all_values[9]	auto[0]	auto[0]	auto[0]	56	1			T227	2		T322	1		T326	1
all_values[9]	auto[0]	auto[0]	auto[1]	28	1			T226	1		T321	1		T325	1
all_values[9]	auto[0]	auto[1]	auto[0]	48	1			T226	2		T321	1		T325	2
all_values[9]	auto[0]	auto[1]	auto[1]	30	1			T228	1		T322	1		T324	1
all_values[9]	auto[1]	auto[0]	auto[1]	73	1			T228	3		T226	2		T321	3
all_values[9]	auto[1]	auto[1]	auto[1]	55	1			T226	2		T227	2		T321	2
all_values[10]	auto[0]	auto[0]	auto[0]	60	1			T228	1		T226	5		T325	2
all_values[10]	auto[0]	auto[0]	auto[1]	23	1			T322	1		T325	1		T326	1
all_values[10]	auto[0]	auto[1]	auto[0]	58	1			T226	2		T227	2		T322	1
all_values[10]	auto[0]	auto[1]	auto[1]	33	1			T227	1		T321	2		T327	1
all_values[10]	auto[1]	auto[0]	auto[1]	52	1			T228	3		T321	3		T325	1
all_values[10]	auto[1]	auto[1]	auto[1]	64	1			T227	1		T321	2		T322	2
all_values[11]	auto[0]	auto[0]	auto[0]	69	1			T228	1		T227	2		T321	1
all_values[11]	auto[0]	auto[0]	auto[1]	21	1			T323	1		T328	1		T329	1
all_values[11]	auto[0]	auto[1]	auto[0]	49	1			T228	3		T226	1		T321	6
all_values[11]	auto[0]	auto[1]	auto[1]	30	1			T226	1		T227	1		T325	1
all_values[11]	auto[1]	auto[0]	auto[1]	68	1			T226	2		T325	2		T324	1
all_values[11]	auto[1]	auto[1]	auto[1]	53	1			T226	3		T227	1		T325	2
all_values[12]	auto[0]	auto[0]	auto[0]	54	1			T228	1		T226	1		T325	1
all_values[12]	auto[0]	auto[0]	auto[1]	24	1			T321	3		T322	1		T330	1
all_values[12]	auto[0]	auto[1]	auto[0]	62	1			T228	1		T226	1		T227	4
all_values[12]	auto[0]	auto[1]	auto[1]	27	1			T322	1		T325	2		T326	1
all_values[12]	auto[1]	auto[0]	auto[1]	62	1			T226	1		T321	1		T325	2
all_values[12]	auto[1]	auto[1]	auto[1]	61	1			T228	2		T226	4		T321	2
all_values[13]	auto[0]	auto[0]	auto[0]	56	1			T228	1		T226	3		T321	1
all_values[13]	auto[0]	auto[0]	auto[1]	24	1			T321	1		T325	3		T326	2
all_values[13]	auto[0]	auto[1]	auto[0]	68	1			T228	1		T226	3		T227	2
all_values[13]	auto[0]	auto[1]	auto[1]	23	1			T228	1		T227	1		T322	2
all_values[13]	auto[1]	auto[0]	auto[1]	60	1			T226	1		T321	2		T325	2
all_values[13]	auto[1]	auto[1]	auto[1]	59	1			T228	1		T227	1		T321	1
all_values[14]	auto[0]	auto[0]	auto[0]	58	1			T228	1		T226	1		T227	1
all_values[14]	auto[0]	auto[0]	auto[1]	23	1			T227	1		T321	1		T325	1
all_values[14]	auto[0]	auto[1]	auto[0]	60	1			T228	1		T226	2		T321	3
all_values[14]	auto[0]	auto[1]	auto[1]	21	1			T226	1		T322	1		T324	1
all_values[14]	auto[1]	auto[0]	auto[1]	75	1			T228	1		T227	2		T321	1
all_values[14]	auto[1]	auto[1]	auto[1]	53	1			T228	1		T226	3		T322	1
all_values[15]	auto[0]	auto[0]	auto[0]	68	1			T228	4		T226	3		T321	3
all_values[15]	auto[0]	auto[0]	auto[1]	27	1			T326	1		T328	2		T329	1
all_values[15]	auto[0]	auto[1]	auto[0]	53	1			T226	1		T227	1		T321	2
all_values[15]	auto[0]	auto[1]	auto[1]	29	1			T226	1		T227	1		T326	1
all_values[15]	auto[1]	auto[0]	auto[1]	62	1			T321	1		T326	1		T324	2
all_values[15]	auto[1]	auto[1]	auto[1]	51	1			T226	2		T227	2		T321	1
all_values[16]	auto[0]	auto[0]	auto[0]	64	1			T228	2		T226	1		T325	3
all_values[16]	auto[0]	auto[0]	auto[1]	33	1			T322	1		T326	2		T324	2
all_values[16]	auto[0]	auto[1]	auto[0]	47	1			T228	2		T226	1		T227	2
all_values[16]	auto[0]	auto[1]	auto[1]	33	1			T226	3		T227	1		T321	3
all_values[16]	auto[1]	auto[0]	auto[1]	60	1			T321	1		T325	2		T326	1
all_values[16]	auto[1]	auto[1]	auto[1]	53	1			T226	2		T227	1		T321	1
all_values[17]	auto[0]	auto[0]	auto[0]	72	1			T228	1		T226	2		T321	2
all_values[17]	auto[0]	auto[1]	auto[0]	89	1			T228	2		T226	3		T227	3
all_values[17]	auto[1]	auto[0]	auto[1]	70	1			T226	1		T325	1		T326	2
all_values[17]	auto[1]	auto[1]	auto[1]	59	1			T228	1		T226	1		T227	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal