75560c7848| Build Mode | Flow Warnings | Flow Errors | SDC Reviews | SDC Warnings | SDC Erros | Setup Reviews | Setup Warnings | Setup Errors | CDC Reviews | CDC Warnings | CDC Errors |
|---|---|---|---|---|---|---|---|---|---|---|---|
| default | 437 | 0 | 0 | 0 | 0 | 190 | 6 | 1 | 30916 | 0 | 929 |
'default' WARN [#104013] : on line 208 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 42213 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 43264 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 44519 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 90159 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#39270] : on line 901 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 947 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 983 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 985 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 986 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 994 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39336] : on line 872 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 126 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 211 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 283 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 287 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 289 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 301 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 124 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 177 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 179 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25014] : on line 187 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25014] : on line 275 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39073] : on line 894 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 895 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 901 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 968 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 969 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39147] : on line 57 in file /workspace/default/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh
WARN [#39066] : on line 244 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39066] : on line 157 in file /workspace/default/src/lowrisc_ip_lc_ctrl_pkg_0.1/rtl/lc_ctrl_pkg.sv
WARN [#39066] : on line 86 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39066] : on line 188 in file /workspace/default/src/lowrisc_ip_lc_ctrl_pkg_0.1/rtl/lc_ctrl_pkg.sv
WARN [#39066] : on line 112 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39316] : on line 48 in file /workspace/default/src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv
WARN [#39244] : on line 80 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39066] : on line 539 in file /workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_pkg.sv
WARN [#39066] : on line 466 in file /workspace/default/src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv
WARN [#39316] : on line 48 in file /workspace/default/src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv
WARN [#25017] : on line 870 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#74005] : chip_earlgrey_asic.sdc:236 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:235 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_dft/prim_clock_buf_tck/clk_o]] on line 236 did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:235 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:234 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == out} -of_objects [get_nets -segments -of_objects [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_dft/prim_clock_buf_tck/clk_o]]] on line 235 did not produce any result
WARN [#74707] : chip_earlgrey_asic.sdc:361 option '-of_objects': invalid collection type
WARN [#74005] : chip_earlgrey_asic.sdc:361 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:361 expected arguments '<ref_objects>', but command [get_pins -leaf -of_objects [get_pins {top_earlgrey/u_spi_device/u_csb_buf/out_o[0]}]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:414 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:414 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:414 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:414 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:414 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:414 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:508 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:508 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:508 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:508 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:508 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:508 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:696 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:696 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:696 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:696 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:696 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:696 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#26020] : on line 203 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 203 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 205 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 205 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 213 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 213 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26080] : on line 397 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26080] : on line 399 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26005] : on line 2 in file /workspace/mnt/repo_top/hw/top_earlgrey/cdc/top_user.env
WARN [#26018] : on line 2 in file /workspace/mnt/repo_top/hw/top_earlgrey/cdc/top_user.env
WARN [#26049] : on line 401 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26049] : on line 401 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_status_23_to_1_sync.*") && (ReconSignal=~"*u_spid_status.outclk_p2s_byte_*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.rxf_full_q*") && (ReceivingFlop=~"*u_spi_device.u_sync_rxf*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"*u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (MultiClockDomains=="SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"*u_spi_device.u_memory_2p.*") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q[0]") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_busy") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association == "Blocked-Dangling") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass == "DATA") && (ErrorType == "Uncontrolled-Tx-MASYNC") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_rptr.q[12:2]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass == "CNTL") && (ErrorType == "") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:2]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_rx_full.q[0]") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_rx_watermark.q[0]") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.rxlvl") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.txlvl") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:2]") && (ReceivingFlop == "top_earlgrey.u_spi_device.sram_rxf_full_q") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '( (Signal=~"*.u_spi_device.u_reg.u_tpm_did*") || (Signal=~"*.u_spi_device.u_reg.u_tpm_int*") || (Signal=~"*.u_spi_device.u_reg.u_tpm_rid*") ) && (MultiClockDomains=="IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*u_spi_device.u_reg.u_cmd_info*") && ((MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") || (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK"))' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*.u_spi_device.u_reg*u_cmd_info*") && (MultiClockDomains =~ "IO_DIV4_CLK::*SPI_DEV*CLK*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*u_spi_device*io_mode_outclk*") && (ReceivingFlop =~ "*u_spi_device.u_memory_2p*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "SPI_DEV_D*") && (ReceivingFlop =~ "*u_spi_device.u_memory_2p*b_rdata*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '( (ReceivingFlop=~"*u_spi_device.u_fwmode.u_*xf_ctrl.*") || (ReceivingFlop=~"*u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr*") || (ReceivingFlop=~"*u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr*") ) && (MultiClockDomains=~"IO_DIV4_CLK::*SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_uart_core.tx_out_q*") && (ReceivingFlop=~"IO*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver=~"*u_uart_core.tx_out_q*") && (ReceivingFlop=~"IO*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_gpio.gen_filter*") && (ReconSignal=~"*u_gpio.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_alert_handler.gen_alerts*u_secure_anchor_flop*") && (ReceivingFlop=~"*u_*alert_sender*.u_decode_ack*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_alert_handler.gen_alerts*u_secure_anchor_flop*") && (ReceivingFlop=~"*u_*alert_sender*.u_decode_ping*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_abort.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_jedec.st_q.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "SPI_HOST_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "IOA*") && (ReceivingFlop=~"top_earlgrey.u_spi_host0.*.*u_shift_reg*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_lc_ctrl.u_dmi_jtag.*_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.bypass_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.*zero1*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "SPI_HOST*") && (ReceivingFlop=~"*u_pinmux_aon.dio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.intg_err_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_fatal_*_err.q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.core_outputs_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.state_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.alert_set_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.u_s1n_*.fifo_h.rspfifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.gen_regfile_ff*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.load_store_unit_i.rdata_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_prim_lc_sender.gen_flops*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.gen_wkup_detect*.u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "IO*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device*.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device*.u_passthrough.passthrough_s_en*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_passthrough.addr_phase_outclk*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_sys_sel.clk_*_en_q*") && (ReceivingFlop=~"u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_ext_aoff*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff*") && (ReceivingFlop=~"top_earlgrey.u_pwrmgr_aon.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*_i*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"top_earlgrey.u_usbdev.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt.wptr_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.sram_wdata[31:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Driver =~ "IOR2")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[15:0]") && (Driver =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.data_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "USB_*") && (Driver =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Driver =~ "top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"top_earlgrey.u_pinmux_aon.*invert") && (GatedClock=~ "top_earlgrey.u_rv_dm.jtag_in_int.tck")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.*q_o*") && (GatedClock=~ "top_earlgrey.u_rv_dm.jtag_in_int.tck")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q*") && (GatedClock=~ "top_earlgrey.u_rv_dm.jtag_in_int.tck")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"IO*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_ext_*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.*.u_impl_generic.q_o*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.*.*h_o*") && (GatedClock=~ "u_ast.u_*_clk.u_*_osc.u_clk_ckgt.gen_generic.u_impl_generic.clk_o*")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClock=~ "top_earlgrey.u_clkmgr_aon.*.gen_generic.u_impl_generic.clk_o*")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"SPI_DEV_CS_L*") && (ReceivingFlop=~"*u_spi_device.u_spi_tpm.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.u_pinmux_aon.mio_pad_attr_q*") && (ReceivingFlop=~"*u_spi_device.spi_clk_csb_rst_toggle*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"IO*") && (ReceivingFlop=~"*u_spi_device.u_spi_tpm.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.*.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.*.i_dmi_cdc.i_cdc_resp.fifo_rptr*_q[0]*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rv_core_ibex*.*gen_alert_senders*.*alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_flash_ctrl*.*gen_alert_senders*.*alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.u_falut_alert.state_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.*.u_fault_alert_state_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*.u_reg.*.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_sender.alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_sysrst_ctrl_aon.u_reg.*.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_aon_timer_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.u_dio_pad_sleep_statue_en_0.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*meas_ctrl_en_cdc*.id_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*u_io_meas.src_err_req")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_handler.gen_alerts**.u_alert_receiver*.*impl_generic*.q_o*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.i_wake_info.info*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rstmgr_aon.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_ast_clks_byp.*io_clk*src*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "IO_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "*u_pinmux_aon.dio_o*_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.*readbuf*sync.src_level*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.u_readbuffer.*buffer_addr*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.u_readbuffer.watermark_crossed*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.readbuf_addr*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_readcmd.u_*.*_q*") && (ReceivingFlop =~ "*top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_DEV_D*") && (ReceivingFlop =~ "*top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host*.q*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host*.*reg*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_xbar_main.u_asf_*.reqfifo.*q*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host0.u_spi_core.u_fsm*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host1.*.q*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.mio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host1.*.*_q*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.mio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.sram_rdata_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_en_q") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_sel") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.all_clks_byp_en_src")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_aoff") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.all_clks_byp_en_src")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_en_q") &&
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_ext*") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_ext_en_q")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.*_clk_byp_dgl.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_sel")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon*_scan*") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.*_o") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[1]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.step_down_ack_o") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[0]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.gen_div2.step_down_nq") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*.u_spi_device.u_reg*u_cmd_info*") && (MultiClockDomains =~ "IO_DIV4_CLK::*SPI_DEV*CLK*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_pinmux_aon.dio_pad_attr_q*.invert")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_*fifo.r_rptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.spi_clk_csb_rst_toggle")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.sys_clk_tog")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_rptr.q[12:2]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.io_mode_outclk[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.storage*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.fifo_*ptr_gray_q[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_sync_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][19:16]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_*ptr_gray_q[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_*fifo.r_rptr_gray_q[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_wptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.fifo_wptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_rptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.fifo_rptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_gray_q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Signal =~ "top_earlgrey.u_spi_device.rxf_full_q")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass =~ "FEEDBACK") && (ErrorType =~ "") && (MultiClockDomains =~ "AST_EXT_CLK,JTAG_TCK,MAIN_CLK::AST_EXT_CLK,MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_*xf_ctrl.*ptr*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_*x*.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression 'Driver =~ "*u_lc_ctrl*.u_prim_lc_sender_escalate_en*"' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.num_req_outstanding[8:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_spi_core.u_fsm.speed_cpha1[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0]") && (Association =~ "None")' did not match any (non-) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dn_o.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dp_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dn_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1:0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_en.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:3]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.readbuf_addr_busclk[31:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_readcmd.readbuf_addr[31:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_rxf_overflow.src_level") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.u_fifo_cnt.*ptr_o*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.sram_wdata[31:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.st_q") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.storage[1:0][23:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q[3:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_tpm_cfg_en.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (MultiClockDomains =~ "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "SPI_DEV_D0")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (MultiClockDomains =~ "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.io_mode_outclk[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_jedec.cc_count[7:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_jedec.byte_sel_q[1:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][31:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_sync_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][31:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Driver =~ "IOR2")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal =~ "IO*") && (Association == "None") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sd_i_q[3:0]") && (Signal =~ "IO*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q[3:0]") && (Signal =~ "IO*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[3:0]") && (Signal =~ "IO*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK") && (ReceivingFlop =~ "IO*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap_q[0]") && (Signal == "IOC3") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap_q[1]") && (Signal == "IOC4") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[0]") && (Signal == "IOC8") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1]") && (Signal == "IOC5") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Signal == "IOB1") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[11:0]") && (Signal == "IOB2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal == "IOR0") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (ReceivingFlop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.bypass_q") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.bypass_q") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "u_ast.padmux2ast_i[4]") && (Signal == "IOB2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,USB_CLK") && (ReceivingFlop == "u_ast.padmux2ast_i[4]") && (Signal == "IOB2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "u_ast.padmux2ast_i[4]") && (Signal == "IOB2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,USB_CLK") && (ReceivingFlop == "u_ast.padmux2ast_i[7]") && (Signal == "IOC3") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "SPI_DEV_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Signal =~ "SPI_DEV_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*") && (Signal =~ "SPI_HOST_D*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*") && (Signal =~ "SPI_DEV_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "SPI_HOST_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cmd_info*.q*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg*.q*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_pinmux_aon.dio_pad_attr_q*.invert")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.in_o") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_p2s.cnt[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (SampleRxSignal == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_lc_ctrl.u_prim_clock_mux2.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o") && (MultiClockDomains == "IO_DIV2_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.src_level") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_s2p.data_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.byte_sel_q[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_p2s.cnt[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"IO*") && (ReceivingFlop=~"*u_i2c*.*.u_sync_1*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal =~ "u_ast.u_ast_clks_byp.*u_impl_generic.q_o*") && (ReconSignal=~"top_earlgrey.*.u_reg*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal =~ "*u_pinmux_aon.u_reg.u_wkup_detector*cdc.u_src_to_dst_req*.u_sync1.*u_impl_generic.q_o*") && (ReconSignal=~"top_earlgrey.*.u_reg*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*u_pinmux_aon.dio_pad_attr_q*")' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_HOST_*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_HOST_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_pinmux_aon.dio_pad_attr_*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockTreeSignal=~"u_ast.u_ast_clks_byp.*") && (DrivenFlop =~ "u_ast.u_ast_clks_byp.*")' did not match any (non-Waived) violations for rule S_GENCLK. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockTreeSignal=~"IOC*") && (DrivenFlop =~ "u_ast.u_ast_clks_byp.*")' did not match any (non-Waived) violations for rule S_GENCLK. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"IO*") && (ReceivingFlop=~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_HOST*") && (ReceivingFlop=~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
CLK_GROUPS: RI_SYNC_GRP_1 AST_EXT_CLK_gated 19.7904 19.7904 - - - New New
CLK_GROUPS: RI_SYNC_GRP_1 USB_CLK 19.76 19.76 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASS_CSB_CLK 60 60 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_HOST_PASS_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASS_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_HOST_CLK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASS_CLK 30 30 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 JTAG_TCK 31.635 31.635 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_TPM_CLK 40 40 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_DIV4_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 LC_JTAG_TCK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_TPM_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 AST_EXT_CLK 19.7904 19.7904 - - - New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASS_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 RV_JTAG_TCK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 MAIN_CLK 8.5 8.5 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_CLK 9.8952 9.8952 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_DIV2_CLK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_CLK 20 20 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_TPM_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_CSB_CLK 40 40 - - - chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK USB_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_CSB_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_IN_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_OUT_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASS_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASS_CSB_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASS_IN_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASS_OUT_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_HOST_PASS_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_TPM_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_TPM_IN_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_TPM_OUT_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_CSB_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_IN_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_OUT_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASS_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASS_CSB_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASS_IN_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASS_OUT_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_HOST_PASS_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_TPM_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_TPM_IN_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_TPM_OUT_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CSB_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CSB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CSB_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CSB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASS_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASS_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CSB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CSB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASS_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CSB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CSB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASS_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CSB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CSB_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CSB_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CSB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CSB_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_CSB_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_IN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_IN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_OUT_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASS_OUT_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASS_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASS_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASS_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV4_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV4_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV4_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:731 New New
CLK_GROUPS: RI_WAVEFORM_ASYNC_0 RI_WAVEFORM_ASYNC_0 8.5 8.5 - - - New New
CLK_GROUPS: RI_WAVEFORM_ASYNC_1 RI_WAVEFORM_ASYNC_1 8.5 8.5 - - - New New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:155 Auto-operator New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:156 Auto-operator New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:157 Auto-operator New
BLACK_BOX: prim_generic_ram_1p-39-32h8000-39 mem prim_generic_ram_1p.sv:48 Auto-large-array New
BLACK_BOX: otbn_mac_bignum (operator) otbn_mac_bignum.sv:101 Auto-operator New
BLACK_BOX: prim_generic_ram_1p-32h4c-32h10000-32h4c mem prim_generic_ram_1p.sv:48 Auto-large-array New
BLACK_BOX: prim_generic_ram_2p top_earlgrey.u_usbdev.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic prim_ram_2p.sv:48 User-defined-module New
BLACK_BOX: prim_packer_fifo-36-9 (operator) prim_packer_fifo.sv:135 Auto-operator New
BLACK_BOX: alert_handler_ping_timer-32hd693e579-160h5dbf54f634c4afa998e470c258641e5239b63c4d (operator) alert_handler_ping_timer.sv:266 Auto-operator New
BLACK_BOX: prim_generic_ram_2p top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic prim_ram_2p.sv:48 User-defined-module New
MULTCLK_CROSSINGS: - top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.in_o top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.st[0] smultclkcrossings19.dbg,rxclockpath19.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0] top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2] txclockpath20.dbg,smultclkcrossings20.dbg,rxclockpath20.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0] top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] txclockpath21.dbg,smultclkcrossings21.dbg,rxclockpath21.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0] top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2] txclockpath22.dbg,smultclkcrossings22.dbg,rxclockpath22.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0] top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] txclockpath23.dbg,smultclkcrossings23.dbg,rxclockpath23.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::IO_DIV4_CLK top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[2] txclockpath24.dbg,smultclkcrossings24.dbg,rxclockpath24.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[0] txclockpath25.dbg,smultclkcrossings25.dbg,rxclockpath25.dbg New New
MULTCLK_CROSSINGS: - top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK SPI_DEV_CS_L top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.st[0] smultclkcrossings26.dbg,rxclockpath26.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o top_earlgrey.u_lc_ctrl.u_prim_clock_mux2.gen_generic.u_impl_generic.clk_o IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK u_ast.dft_scan_md_o[3] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[0] txclockpath27.dbg,smultclkcrossings27.dbg,rxclockpath27.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o txclockpath28.dbg,smultclkcrossings28.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o txclockpath29.dbg,smultclkcrossings29.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o IO_DIV4_CLK::IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] txclockpath30.dbg,smultclkcrossings30.dbg,rxclockpath30.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_s2p.data_q[0] top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q txclockpath31.dbg,smultclkcrossings31.dbg,rxclockpath31.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0] top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] txclockpath32.dbg,smultclkcrossings32.dbg,rxclockpath32.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_gray_q[0] top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] txclockpath33.dbg,smultclkcrossings33.dbg,rxclockpath33.dbg New New
S_CONF_ENV: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV4_CLK AST_EXT_CLK,IO_CLK IO_DIV4_CLK constraints.sdc.env:153 PostResetPhase prim_clock_div-32h4 New
S_CONF_ENV: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV2_CLK AST_EXT_CLK,IO_CLK IO_DIV2_CLK constraints.sdc.env:149 PostResetPhase,sconfenv35.dbg prim_clock_div New
S_MISSING_SPEC: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV4_CLK AST_EXT_CLK constraints.sdc.env:153 prim_clock_div-32h4 New
S_MISSING_SPEC: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV2_CLK AST_EXT_CLK constraints.sdc.env:149 prim_clock_div New
S_MISSING_SPEC: top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o prim_clock_buf.sv:49 IO_DIV2_CLK,SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK create_clock waveform=SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK IO_DIV2_CLK constraints.sdc.env:165,constraints.sdc.env:173,constraints.sdc.env:189 prim_clock_buf-1=1h1 New
S_MISSING_SPEC: top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o prim_clock_buf.sv:49 IO_DIV2_CLK,SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK create_clock waveform=SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK IO_DIV2_CLK constraints.sdc.env:169,constraints.sdc.env:177,constraints.sdc.env:193 prim_clock_buf-1=1h1 New
S_INPUT_NO_WAVE: SPI_HOST_CS_L top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK_gated prim_generic_flop.sv:21 sinputnowave40.dbg New Flat-to-Flat
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99261.dbg
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99262.dbg
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_i2c0.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c0.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99263.dbg
CNTL: IOR0 top_earlgrey.u_i2c0.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c0.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_i2c0.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c0.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99264.dbg
CNTL: IOR13 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99265.dbg
CNTL: IOC8 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c1.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99266.dbg
CNTL: IOB4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[3].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_scl.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99267.dbg
CNTL: IOR0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_i2c2.i2c_core.u_i2c_sync_sda.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_sensor_ctrl_aon.u_io_status_chg.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sensor_ctrl_aon.u_io_status_chg.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl99268.dbg
CNTL: IOC1 top_earlgrey.u_sensor_ctrl_aon.u_io_status_chg.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sensor_ctrl_aon.u_io_status_chg.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New --
CNTL: IOR12 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99269.dbg
CNTL: IOC1 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR9 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl99270.dbg
CNTL: IOR8 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[1] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[1] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl99271.dbg
CNTL: IOR0 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99272.dbg
CNTL: IOR2 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99273.dbg
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99274.dbg
CNTL: IOB4 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart0.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99275.dbg
CNTL: IOR1 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart1.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99276.dbg
CNTL: IOB10 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart2.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99277.dbg
CNTL: IOC9 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_uart3.uart_core.sync_rx.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99278.dbg
CNTL: IOC12 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR3 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99279.dbg
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99280.dbg
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[4].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99281.dbg
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99282.dbg
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99283.dbg
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99284.dbg
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99285.dbg
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99286.dbg
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99287.dbg
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99288.dbg
CNTL: USB_P top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99289.dbg
CNTL: USB_P top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[3] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[3] 2 None SlowToFast Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99290.dbg
CNTL: USB_P top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[1] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[1] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99291.dbg
CNTL: USB_N top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[2:1] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[2:1] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: SPI_DEV_CS_L top_earlgrey.u_spi_device.u_csb_edge_sysclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_csb_edge_sysclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat chip_earlgrey_asic New cntl99292.dbg
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: u_ast.io_clk_byp_ack_o[3:0] top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl99293.dbg
CNTL: u_ast.all_clk_byp_ack_o[3:0] top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl99294.dbg
CNTL: top_earlgrey.u_spi_device.rxf_full_q top_earlgrey.u_spi_device.u_sync_rxf.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sync_rxf.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl99295.dbg
CNTL: top_earlgrey.u_spi_device.sys_clk_tog top_earlgrey.u_spi_device.u_sck_tog_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sck_tog_edge.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl99296.dbg
CNTL: top_earlgrey.u_spi_device.txf_empty_q top_earlgrey.u_spi_device.u_sync_txe.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sync_txe.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl99297.dbg
CNTL: top_earlgrey.u_rv_core_ibex.core_sleep_q top_earlgrey.u_pwrmgr_aon.u_cdc.u_sleeping_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_pwrmgr_aon.u_cdc.u_sleeping_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback FastToSlow Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99298.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[22] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[22] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99299.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[21] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[21] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99300.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[18] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[18] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99301.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[17] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[17] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99302.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[14] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[14] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99303.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[13] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[13] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99304.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[10] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[10] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99305.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[9] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[9] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99306.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[6] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[6] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99307.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[5] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[5] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99308.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[2] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[2] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99309.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[1] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[1] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99310.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_fmt_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[107] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[107] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99311.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_fmt_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[92] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[92] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99312.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_fmt_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[77] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[77] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99313.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_readbuf_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[74] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[74] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99314.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_payload_not_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[72] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[72] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99315.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_cmdfifo_not_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[71] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[71] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99316.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[28] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[28] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99317.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[20] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[20] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99318.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[12] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[12] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99319.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[4] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[4] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99320.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_host_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[121] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[121] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99321.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_acq_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[119] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[119] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99322.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_fmt_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[109] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[109] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99323.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classb.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[128] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[128] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99324.dbg
CNTL: top_earlgrey.u_adc_ctrl_aon.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[154] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[154] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99325.dbg
CNTL: top_earlgrey.u_pattgen.u_pattgen_core.intr_hw_done_ch1.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[123] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[123] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99326.dbg
CNTL: top_earlgrey.u_pattgen.u_pattgen_core.intr_hw_done_ch0.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[122] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[122] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99327.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_sda_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[113] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[113] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99328.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_scl_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[112] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[112] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99329.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_sda_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[98] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[98] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99330.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_scl_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[97] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[97] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99331.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_sda_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[83] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[83] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99332.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_scl_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[82] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[82] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99333.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_tpm_cmdaddr_notempty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[76] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[76] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99334.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classd.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[130] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[130] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99335.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classc.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[129] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[129] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99336.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[25] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[25] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99337.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classa.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[127] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[127] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99338.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_stretch_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[114] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[114] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99339.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_stretch_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[99] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[99] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99340.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_stretch_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[84] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[84] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99341.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[32] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[32] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99342.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[24] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[24] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99343.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[16] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[16] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99344.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[8] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[8] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99345.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[30] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[30] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99346.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[29] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[29] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99347.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[26] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[26] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99348.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxoverflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[69] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[69] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99349.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_unexp_stop.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[105] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[105] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99350.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[102] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[102] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99351.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_unexp_stop.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[90] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[90] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99352.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[87] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[87] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99353.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[27] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[27] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99354.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[19] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[19] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99355.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[11] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[11] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99356.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99357.dbg
CNTL: top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[124] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[124] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99358.dbg
CNTL: top_earlgrey.u_sysrst_ctrl_aon.u_prim_intr_hw.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[153] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[153] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99359.dbg
CNTL: top_earlgrey.u_otp_ctrl.u_intr_operation_done.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[125] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[125] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99360.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_readbuf_flip.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[75] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[75] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99361.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_txunderflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[70] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[70] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99362.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_sda_unstable.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[115] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[115] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99363.dbg
CNTL: top_earlgrey.u_sensor_ctrl_aon.u_init_intr.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[158] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[158] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99364.dbg
CNTL: top_earlgrey.u_sensor_ctrl_aon.u_io_intr.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[157] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[157] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99365.dbg
CNTL: top_earlgrey.u_aon_timer_aon.u_intr_hw.intr_o[1:0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[156:155] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[156:155] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99366.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_nak.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[111] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[111] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99367.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_nak.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[96] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[96] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99368.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_nak.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[81] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[81] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99369.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxerr.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[68] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[68] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99370.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_txlvl.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[67] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[67] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99371.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxlvl.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[66] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[66] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99372.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.intr_wakeup.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[152] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[152] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99373.dbg
CNTL: top_earlgrey.u_otp_ctrl.u_intr_error.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[126] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[126] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99374.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxf.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[65] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[65] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99375.dbg
CNTL: top_earlgrey.u_gpio.intr_hw.intr_o[31:0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[64:33] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[64:33] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99376.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_unexp_stop.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[120] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[120] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99377.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_fmt_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[94] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[94] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99378.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_sda_unstable.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[100] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[100] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99379.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_cmd_complete.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[101] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[101] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99380.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_acq_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[104] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[104] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99381.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[117] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[117] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99382.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_host_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[106] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[106] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99383.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_rx_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[93] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[93] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99384.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_host_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[91] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[91] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99385.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_rx_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[108] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[108] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99386.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_acq_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[89] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[89] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99387.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_cmd_complete.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[86] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[86] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99388.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_sda_unstable.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[85] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[85] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99389.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_cmd_complete.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[116] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[116] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99390.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_rx_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[78] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[78] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99391.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[80] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[80] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99392.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_tx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[88] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[88] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99393.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[95] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[95] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99394.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_tx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[103] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[103] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99395.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[110] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[110] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99396.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_tx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[118] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[118] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99397.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99398.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[15] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[15] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99399.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[23] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[23] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99400.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[31] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[31] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99401.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_payload_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[73] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[73] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99402.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_fmt_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[79] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[79] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99403.dbg
CNTL: top_earlgrey.u_usbdev.intr_av_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[142] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[142] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99404.dbg
CNTL: top_earlgrey.u_usbdev.intr_host_lost.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[138] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[138] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99405.dbg
CNTL: top_earlgrey.u_usbdev.intr_powered.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[150] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[150] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99406.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_reset.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[139] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[139] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99407.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_crc_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[146] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[146] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99408.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_pid_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[147] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[147] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99409.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_full.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[143] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[143] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99410.dbg
CNTL: top_earlgrey.u_usbdev.intr_frame.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[149] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[149] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99411.dbg
CNTL: top_earlgrey.u_usbdev.intr_disconnected.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[137] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[137] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99412.dbg
CNTL: top_earlgrey.u_usbdev.intr_hw_pkt_sent.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[136] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[136] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99413.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_resume.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[141] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[141] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99414.dbg
CNTL: top_earlgrey.u_usbdev.intr_av_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[144] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[144] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99415.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_in_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[145] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[145] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99416.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_bitstuff_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[148] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[148] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99417.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_suspend.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[140] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[140] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99418.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_out_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[151] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[151] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99419.dbg
CNTL: top_earlgrey.u_usbdev.intr_hw_pkt_received.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[135] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[135] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99420.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99421.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99422.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99423.dbg
CNTL: top_earlgrey.u_aon_timer_aon.u_intr_hw.intr_o[1] top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99424.dbg
CNTL: top_earlgrey.u_spi_host0.intr_hw_error.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[131] AST_EXT_CLK,IO_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[131] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99425.dbg
CNTL: top_earlgrey.u_spi_host0.intr_hw_spi_event.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[132] AST_EXT_CLK,IO_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[132] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99426.dbg
CNTL: top_earlgrey.u_spi_host1.intr_hw_error.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[133] IO_DIV2_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[133] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99427.dbg
CNTL: top_earlgrey.u_spi_host1.intr_hw_spi_event.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[134] IO_DIV2_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[134] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99428.dbg
CNTL: top_earlgrey.u_spi_device.spi_clk_csb_rst_toggle top_earlgrey.u_spi_device.u_clk_csb_edge_0.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_clk_csb_edge_0.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl99429.dbg
CNTL: top_earlgrey.u_spi_device.u_rxf_overflow.src_level top_earlgrey.u_spi_device.u_rxf_overflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_rxf_overflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat prim_pulse_sync New cntl99430.dbg
CNTL: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[0].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[3] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[3] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56.q[5:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[1].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[2] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[2] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,cntl99431.dbg
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[28].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[3].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[7].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[4].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[5].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[6].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[9].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[8].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_spi_device.u_txf_underflow.src_level top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat prim_pulse_sync New cntl99432.dbg
CNTL: top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q[0] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SameFreq Flat-To-Flat spi_device New Missing-Feedback,cntl99433.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_1.q[0] top_earlgrey.u_rstmgr_aon.u_d0_spi_host0.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_spi_host0.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat rstmgr New cntl99434.dbg
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl99435.dbg
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_2.q[0] top_earlgrey.u_rstmgr_aon.u_d0_spi_host1.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_spi_host1.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat rstmgr New cntl99436.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_3.q[0] top_earlgrey.u_rstmgr_aon.u_d0_usb.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_usb.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat rstmgr New cntl99437.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl99438.dbg
CNTL: top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.kmac_fsm_err_q top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat lc_ctrl_kmac_if New cntl99439.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl99440.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans New cntl99441.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl99442.dbg
CNTL: top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0] top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99443.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.combined_en_q top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl99444.dbg
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl99445.dbg
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_decode_esc.level_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32he417ad9a-20=160h7443a428fe2de15c7d33b199c90dfda37790088b-21=32h10800-22=32h10810-24=128hdc260a79998eff5c710b67838adfb99a-25=64h5eca671672cf19bc New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.ping_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_ping_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[8:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_ping_timer.u_prim_count_esc_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[21:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32he417ad9a-20=160h7443a428fe2de15c7d33b199c90dfda37790088b-21=32h10800-22=32h10810-24=128hdc260a79998eff5c710b67838adfb99a-25=64h5eca671672cf19bc New --
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[21:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32he417ad9a-20=160h7443a428fe2de15c7d33b199c90dfda37790088b-21=32h10800-22=32h10810-24=128hdc260a79998eff5c710b67838adfb99a-25=64h5eca671672cf19bc New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.esc_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.state_q[2:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32he417ad9a-20=160h7443a428fe2de15c7d33b199c90dfda37790088b-21=32h10800-22=32h10810-24=128hdc260a79998eff5c710b67838adfb99a-25=64h5eca671672cf19bc New --
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.combined_en_q top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl99446.dbg
Note: 29916 more messages have been suppressed (max_msg_count = 1000)
W_CNTL: top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q[0] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SameFreq Flat-To-Flat Missing-Feedback,cntl99433.dbg spi_device New
W_CNTL: top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.src_level top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SameFreq Flat-To-Flat Missing-Feedback,cntl99486.dbg prim_pulse_sync New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[1:0] prim_fifo_sync_cnt.sv:79 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82838.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[1:0] prim_fifo_sync_cnt.sv:79 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82839.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[1:0] prim_fifo_sync_cnt.sv:91 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82842.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[1:0] prim_fifo_sync_cnt.sv:91 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82843.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82846.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82847.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82848.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82849.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82850.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82851.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82852.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82853.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82854.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82855.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82856.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82857.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82858.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82859.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82860.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82861.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82862.dbg spi_device New Waived multiple source to readcmd sram in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage[1:0][7:0] prim_fifo_sync.sv:151 IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82863.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o[7:0] spi_readcmd.sv:534 IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82864.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o[7:0] spi_readcmd.sv:534 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82865.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[0] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82880.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[0] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82881.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[1] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82882.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[17] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[1] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82883.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[2] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82884.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[10] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[2] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82885.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[3] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82886.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[11] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[3] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82887.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[4] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82888.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[12] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[4] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82889.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[5] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82890.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[13] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[5] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82891.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[6] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82892.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[14] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[6] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82893.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[7] spid_status.sv:229 IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82894.dbg spi_device New New
W_MASYNC: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[15] top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[7] spid_status.sv:229 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK DATA,wmasync82895.dbg spi_device New Waived multiple source to 2p memory in spi device; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: SPI_DEV_D0 top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q prim_ram_2p_async_adv.sv:146 SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82902.dbg chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q prim_ram_2p_async_adv.sv:146 IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82903.dbg chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_MASYNC: top_earlgrey.u_spi_device.io_mode_outclk[0] top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q prim_ram_2p_async_adv.sv:146 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA,wmasync82904.dbg chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_spi_device.u_cmdparse.cmd_info_q.addr_mode[0] top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q prim_ram_2p_async_adv.sv:146 SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK DATA chip_earlgrey_asic New Waived SPI to Dual port memory read port; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR2 top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4] dmi_jtag_tap.sv:109 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK,LC_JTAG_TCK DATA,wmasync82941.dbg chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4] dmi_jtag_tap.sv:109 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK DATA,wmasync82942.dbg chip_earlgrey_asic New Waived retention regs; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR2 top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31] dmi_jtag_tap.sv:308 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK,LC_JTAG_TCK DATA,wmasync82951.dbg chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31] dmi_jtag_tap.sv:308 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK DATA,wmasync82952.dbg chip_earlgrey_asic New Waived retention regs; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOA0 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sd_i_q[3:0] spi_host_shift_register.sv:106 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV2_CLK DATA,wmasync82983.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR0 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sd_i_q[3:0] spi_host_shift_register.sv:106 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV2_CLK DATA,wmasync82984.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR3 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sd_i_q[3:0] spi_host_shift_register.sv:106 JTAG_TCK::IO_DIV2_CLK DATA,wmasync82985.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sd_i_q[3:0] spi_host_shift_register.sv:106 IO_DIV4_CLK::IO_DIV2_CLK DATA chip_earlgrey_asic New New
W_MASYNC: IOA0 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[3:0] spi_host_shift_register.sv:107 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV2_CLK DATA,wmasync82995.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR0 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[3:0] spi_host_shift_register.sv:107 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV2_CLK DATA,wmasync82996.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR3 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[3:0] spi_host_shift_register.sv:107 JTAG_TCK::IO_DIV2_CLK DATA,wmasync82997.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[3:0] spi_host_shift_register.sv:107 IO_DIV4_CLK::IO_DIV2_CLK DATA chip_earlgrey_asic New New
W_MASYNC: IOA0 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q[3:0] spi_host_shift_register.sv:109 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV2_CLK DATA,wmasync83007.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR0 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q[3:0] spi_host_shift_register.sv:109 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV2_CLK DATA,wmasync83008.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: IOR3 top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q[3:0] spi_host_shift_register.sv:109 JTAG_TCK::IO_DIV2_CLK DATA,wmasync83009.dbg chip_earlgrey_asic New Waived w_masync issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.rx_buf_q[3:0] spi_host_shift_register.sv:109 IO_DIV4_CLK::IO_DIV2_CLK DATA chip_earlgrey_asic New New
W_MASYNC: IOR2 top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] dmi_jtag.sv:96 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK DATA,wmasync83292.dbg chip_earlgrey_asic New Waived retention regs; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] dmi_jtag.sv:96 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK DATA,wmasync83293.dbg chip_earlgrey_asic New Waived retention regs; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:23 PDT
W_MASYNC: top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] dmi_jtag.sv:96 AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK DATA,wmasync83294.dbg chip_earlgrey_asic New New
W_MASYNC: IOA0 SPI_DEV_D0 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83313.dbg chip_earlgrey_asic New New
W_MASYNC: IOR0 SPI_DEV_D0 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83314.dbg chip_earlgrey_asic New New
W_MASYNC: IOR3 SPI_DEV_D0 chip_earlgrey_asic.sv:250 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83315.dbg chip_earlgrey_asic New New
W_MASYNC: SPI_HOST_D0 SPI_DEV_D0 chip_earlgrey_asic.sv:250 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[6] SPI_DEV_D0 chip_earlgrey_asic.sv:250 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_MASYNC: IOA0 SPI_DEV_D1 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83316.dbg chip_earlgrey_asic New New
W_MASYNC: IOR0 SPI_DEV_D1 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83317.dbg chip_earlgrey_asic New New
W_MASYNC: IOR3 SPI_DEV_D1 chip_earlgrey_asic.sv:250 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83318.dbg chip_earlgrey_asic New New
W_MASYNC: SPI_HOST_D1 SPI_DEV_D1 chip_earlgrey_asic.sv:250 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[7] SPI_DEV_D1 chip_earlgrey_asic.sv:250 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_MASYNC: IOA0 SPI_DEV_D2 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83319.dbg chip_earlgrey_asic New New
W_MASYNC: IOR0 SPI_DEV_D2 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83320.dbg chip_earlgrey_asic New New
W_MASYNC: IOR3 SPI_DEV_D2 chip_earlgrey_asic.sv:250 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83321.dbg chip_earlgrey_asic New New
W_MASYNC: SPI_HOST_D2 SPI_DEV_D2 chip_earlgrey_asic.sv:250 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[8] SPI_DEV_D2 chip_earlgrey_asic.sv:250 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_MASYNC: IOA0 SPI_DEV_D3 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83322.dbg chip_earlgrey_asic New New
W_MASYNC: IOR0 SPI_DEV_D3 chip_earlgrey_asic.sv:250 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83323.dbg chip_earlgrey_asic New New
W_MASYNC: IOR3 SPI_DEV_D3 chip_earlgrey_asic.sv:250 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT,wmasync83324.dbg chip_earlgrey_asic New New
W_MASYNC: SPI_HOST_D3 SPI_DEV_D3 chip_earlgrey_asic.sv:250 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_MASYNC: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[9] SPI_DEV_D3 chip_earlgrey_asic.sv:250 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK INOUT chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_timer_v.q[7:0] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.cur_timer[7:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:134 None Flat-To-Flat data82043.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_cc_cc.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data82051.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_id_mf.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data82052.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_id_id.q[15:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data82073.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_ptr_wptr.q[12:0] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.wptr_q[12:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:177 None Flat-To-Flat data82093.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[1:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:107 None Flat-To-Flat data82096.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[11:2] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:106 None Flat-To-Flat data82097.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:103 None Flat-To-Flat data82098.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[11:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:104 None Flat-To-Flat data82099.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[11:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:104 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[1:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:107 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:103 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_rxf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[11:2] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_rxf_ctrl.sv:106 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:2] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:188 None Flat-To-Flat data82100.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[11:2] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:192 None Flat-To-Flat data82101.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:2] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:188 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:191 None Flat-To-Flat data82102.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[1:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:193 None Flat-To-Flat data82103.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_limit.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[1:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:189 None Flat-To-Flat data82104.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[1:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:189 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[1:0] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:193 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[11:2] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:192 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_txf_addr_base.q[11:2] top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12] IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spi_fwm_txf_ctrl.sv:191 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_cc_num_cc.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data82106.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:2] top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_rx_full.q[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK prim_subreg.sv:59 None Flat-To-Flat data82107.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:0] top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_rx_watermark.q[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK prim_subreg.sv:59 None Flat-To-Flat data82108.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:0] top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK prim_subreg.sv:59 None Flat-To-Flat data82109.dbg spi_device New New
W_DATA: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.gen_generic.u_impl_generic.step_down_ack_o top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[1] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 None Flat-To-Flat data82260.dbg clkmgr New New
W_DATA: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.step_down_nq top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 None Flat-To-Flat data82261.dbg clkmgr New New
W_DATA: IOA5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82387.dbg chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D0 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82388.dbg chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D1 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82389.dbg chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D2 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82390.dbg chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D3 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_DEV_D0 SPI_HOST_D0 SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82397.dbg chip_earlgrey_asic New New
W_DATA: SPI_DEV_D1 SPI_HOST_D1 SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82398.dbg chip_earlgrey_asic New New
W_DATA: SPI_DEV_D2 SPI_HOST_D2 SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82399.dbg chip_earlgrey_asic New New
W_DATA: SPI_DEV_D3 SPI_HOST_D3 SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82400.dbg chip_earlgrey_asic New New
W_DATA: SPI_HOST_D0 SPI_DEV_D0 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D1 SPI_DEV_D1 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D2 SPI_DEV_D2 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D3 SPI_DEV_D3 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_DEV_CS_L SPI_HOST_CS_L SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat data82402.dbg chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[6] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].pull_select SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].drive_strength[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[7].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[8].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[9].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[6].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[5].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].pull_en SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[3].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[4].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_tpm_cfg_en.q[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q[5:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:21 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:22 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_6.q[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[28].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].virt_od_en SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[9].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[28].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].pull_select SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_8.q[0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].pull_en SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:22 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:21 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[6].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[7].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[8].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q[5:0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[5].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[4].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[8] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].drive_strength[0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].virt_od_en SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[4].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[3].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].invert SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_tpm_cfg_en.q[0] SPI_DEV_D2 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[9].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[3].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[6].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q[5:0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[9] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].virt_od_en SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].drive_strength[0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_tpm_cfg_en.q[0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_9.q[0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[8].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[4].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].pull_select SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[7].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[5].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:21 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:22 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].pull_en SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[28].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].invert SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] SPI_DEV_D3 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_payload_swap_data.q[31:0] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_payload_swap_mask.q[31:0] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_2.q[0] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].drive_strength[0] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].virt_od_en SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[2] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].invert SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].pull_select SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_addr_swap_data.q[31:0] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_addr_swap_mask.q[31:0] SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].pull_en SPI_HOST_D0 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_3.q[0] SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[3] SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3].drive_strength[0] SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].invert SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3].invert SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3].virt_od_en SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3].pull_select SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3].pull_en SPI_HOST_D1 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[4].virt_od_en SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[4].drive_strength[0] SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[4] SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[4].pull_en SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[4].pull_select SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[4].invert SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].invert SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_4.q[0] SPI_HOST_D2 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5].pull_en SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5].invert SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5].virt_od_en SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5].drive_strength[0] SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[5] SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5].pull_select SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_5.q[0] SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].invert SPI_HOST_D3 IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[15].pull_en SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[15].pull_select SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_15.q[0] SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[15].drive_strength[0] SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[15].virt_od_en SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[15].invert SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:57 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[15] SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_HOST_CS_L IO_DIV4_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_speed_q[1:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_reg_if.outstanding_q SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_wr_en_q SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.num_req_outstanding[8:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.byte_cntr_cpha0_q[8:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cpha_q SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[7:6] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_accessinval.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.clk_cntr_q[15:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.wait_cntr_q[3:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.speed_cpha1[1:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdbusy.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[106:104] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csaat_q SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[100:99] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_underflow.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_csidinval.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csb_q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_overflow.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdinval.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_sw_rst.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.state_q[2:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csid_q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.bit_cntr_q[2:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[90:23] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[4] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[17:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_spien.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.dev_select_outstanding[1:0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_configopts_cpha_0.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_output_en.q[0] SPI_HOST_D0 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.wait_cntr_q[3:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_sw_rst.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[7] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.state_q[2:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_output_en.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[17:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csb_q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_configopts_cpha_0.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.speed_cpha1[1:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.num_req_outstanding[8:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csid_q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[100:99] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_reg_if.outstanding_q SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_wr_en_q SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_spien.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.bit_cntr_q[2:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.clk_cntr_q[15:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_csidinval.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_accessinval.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[106:104] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdbusy.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_speed_q[1:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.byte_cntr_cpha0_q[8:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.dev_select_outstanding[1:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_underflow.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cpha_q SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdinval.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[5] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[90:23] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csaat_q SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_overflow.q[0] SPI_HOST_D1 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_output_en.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cpha_q SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdbusy.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.clk_cntr_q[15:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_configopts_cpha_0.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_reg_if.outstanding_q SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_wr_en_q SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.state_q[2:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[6] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.wait_cntr_q[3:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[106:104] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdinval.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csb_q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.speed_cpha1[1:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_speed_q[1:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.num_req_outstanding[8:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.byte_cntr_cpha0_q[8:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_overflow.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_accessinval.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.dev_select_outstanding[1:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csid_q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_spien.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_csidinval.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_underflow.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_sw_rst.q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csaat_q SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.bit_cntr_q[2:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[90:23] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[17:0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_q[0] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[100:99] SPI_HOST_D2 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.byte_cntr_cpha0_q[8:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdinval.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.speed_cpha1[1:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_accessinval.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[17:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_output_en.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[7] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_configopts_cpha_0.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_overflow.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csid_q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_spien.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[106:104] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.num_req_outstanding[8:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.state_q[2:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.wait_cntr_q[3:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_speed_q[1:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csb_q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.bit_cntr_q[2:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[100:99] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cpha_q SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.rdata_o[90:23] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csaat_q SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_sw_rst.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_underflow.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_cmdbusy.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.clk_cntr_q[15:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_error_status_csidinval.q[0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.cmd_wr_en_q SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_reg_if.outstanding_q SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_socket.dev_select_outstanding[1:0] SPI_HOST_D3 AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_spi_core.u_fsm.csb_q[0] SPI_HOST_CS_L AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_host0.u_reg.u_control_output_en.q[0] SPI_HOST_CS_L AST_EXT_CLK,IO_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:0] top_earlgrey.u_spi_device.rxlvl IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK spi_device.sv:501 None Flat-To-Flat data82489.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:2] top_earlgrey.u_spi_device.sram_rxf_full_q IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK spi_device.sv:484 None Flat-To-Flat data82490.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:0] top_earlgrey.u_spi_device.txlvl IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV4_CLK spi_device.sv:502 None Flat-To-Flat data82491.dbg spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_payload_swap_en_outclk SPI_HOST_D0 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.addrcnt_outclk[4:0] SPI_HOST_D0 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.passthrough_s_en[0] SPI_HOST_D0 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_addr_swap_en_outclk SPI_HOST_D0 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.addr_phase_outclk SPI_HOST_D0 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.payload_replace_outclk SPI_HOST_D0 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.payloadcnt_outclk[4:0] SPI_HOST_D0 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.payload_replace_outclk SPI_HOST_D1 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.passthrough_s_en[1] SPI_HOST_D1 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_addr_swap_en_outclk SPI_HOST_D1 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.addr_phase_outclk SPI_HOST_D1 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_payload_swap_en_outclk SPI_HOST_D1 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.payload_replace_outclk SPI_HOST_D2 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.passthrough_s_en[2] SPI_HOST_D2 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_addr_swap_en_outclk SPI_HOST_D2 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.addr_phase_outclk SPI_HOST_D2 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_payload_swap_en_outclk SPI_HOST_D2 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.addr_phase_outclk SPI_HOST_D3 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.passthrough_s_en[3] SPI_HOST_D3 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.payload_replace_outclk SPI_HOST_D3 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_payload_swap_en_outclk SPI_HOST_D3 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.cmd_info_addr_swap_en_outclk SPI_HOST_D3 SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_passthrough.csb_deassert_outclk SPI_HOST_CS_L SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] SPI_HOST_CS_L IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D0 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D1 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D2 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0] SPI_HOST_D3 IO_DIV2_CLK,SPI_DEV_CSB_CLK,SPI_DEV_PASS_CSB_CLK::SPI_HOST_CLK,SPI_HOST_PASS_CLK chip_earlgrey_asic.sv:250 None Flat-To-Flat -- chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37:0].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93037.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93038.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93039.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93040.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46:39].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93041.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93042.dbg chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:21 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_tpm_cfg_en.q[0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93043.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q[5:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93044.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93045.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93046.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93047.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_7.q[0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93048.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[7] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93049.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].virt_od_en SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93050.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_active_locality[4:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93051.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.int_enable[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93052.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.int_status[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93053.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.intf_capacity[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93054.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.status[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93055.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.id[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93056.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.access[39:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93057.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.int_vector[7:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93058.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.rid[7:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93059.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].drive_strength[0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93060.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].pull_en SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93061.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].pull_select SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93062.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D1 SPI_DEV_D1 SPI_HOST_CLK,SPI_HOST_PASS_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93063.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93064.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93065.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93066.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93067.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93068.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface93036.dbg,winterface93069.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94002.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94003.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94004.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94005.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94006.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94007.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94008.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94009.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94010.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94011.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94012.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94013.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB9 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94014.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94015.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94016.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94017.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94018.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94019.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94020.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94021.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94022.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94023.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94024.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94025.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC9 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94026.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94027.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94028.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94029.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94030.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94031.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94032.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR3 SPI_DEV_D1 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94033.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94034.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94035.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94036.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94037.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94038.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94039.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94040.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR13 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:250 Load-Cntl,winterface94001.dbg,winterface94041.dbg chip_earlgrey_asic New New
W_INTERFACE: CNTL top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.fifo_wptr_gray_q[4:0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK prim_generic_flop.sv:21 Depth=1,winterface94042.dbg chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.fifo_rptr_gray_q[4:0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] SPI_DEV_OUT_CLK,SPI_DEV_PASS_OUT_CLK,SPI_TPM_OUT_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:293 Load-Cntl,winterface94043.dbg,winterface94044.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:293 Load-Cntl,winterface94043.dbg,winterface94045.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:293 Load-Cntl,winterface94043.dbg,winterface94046.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:293 Load-Cntl,winterface94043.dbg,winterface94047.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:293 Load-Cntl,winterface94043.dbg,winterface94048.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.data_q[1:0] top_earlgrey.u_rv_dm.dap.dr_q[40] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:293 Load-Cntl,winterface94043.dbg,winterface94049.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR2 top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:293 Load-Cntl,winterface94043.dbg,winterface94050.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: CNTL top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK prim_generic_flop.sv:21 Depth=1,winterface94051.dbg chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.csb_q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94053.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94054.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94055.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94056.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94057.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_socket.num_req_outstanding[8:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94058.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94059.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_reg_if.outstanding_q top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94060.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94061.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_control_sw_rst.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94062.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_control_spien.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94063.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_cmdbusy.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94064.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_overflow.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94065.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_underflow.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94066.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_cmdinval.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94067.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_csidinval.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface94052.dbg,winterface94068.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_accessinval.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95002.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.clk_cntr_q[15:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95003.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.state_q[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95004.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.bit_cntr_q[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95005.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.byte_cntr_cpha0_q[8:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95006.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.csaat_q top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95007.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.wait_cntr_q[3:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95008.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_configopts_cpha_0.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95009.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:58 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.cmd_speed_q[1:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95010.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.speed_cpha1[1:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95011.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[7:4] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95012.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.u_sck_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95013.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA u_ast.ast2padmux_o[4:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95014.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95015.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.csid_q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95016.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95017.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.cpha_q top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95018.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95019.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95020.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95021.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95022.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95023.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95024.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA6 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95025.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95026.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA8 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95027.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95028.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95029.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95030.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95031.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95032.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95033.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB6 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95034.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95035.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB8 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95036.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB9 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95037.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB10 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95038.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB11 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95039.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB12 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95040.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95041.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95042.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95043.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95044.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95045.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95046.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95047.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC8 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95048.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC9 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95049.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC10 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95050.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC11 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95051.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC12 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95052.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95053.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95054.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95055.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] JTAG_TCK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95056.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95057.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95058.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR6 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95059.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95060.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR10 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95061.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR11 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95062.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR12 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95063.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR13 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95064.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_xbar_main.u_asf_39.reqfifo.rdata_o[90:23] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95065.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_xbar_main.u_asf_39.reqfifo.rdata_o[17:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95066.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_xbar_main.u_asf_39.reqfifo.rdata_o[106:104] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95067.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_xbar_main.u_asf_39.reqfifo.rdata_o[100:99] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:421 Fifo-Cntl,winterface95001.dbg,winterface95068.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: CNTL top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2,winterface96001.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_aes_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_hmac_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_kmac_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_otbn_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][15:8] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][31:24] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][23:16] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][7:0] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_classes[3:0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_classes[3:0].u_accu.u_prim_count.gen_cnts[1:0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_classes[3:0].u_esc_timer.u_prim_count.gen_cnts[1:0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_ping_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[8:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_ping_timer.u_prim_count_esc_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.esc_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.ping_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_decode_esc.level_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.state_q[2:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_prim_count.gen_cnts[1:0].u_cnt_flop.gen_generic.u_impl_generic.q_o[21:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:43 PDT
W_FANOUT: top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New New
W_FANOUT: top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New New
W_FANOUT: top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New New
W_FANOUT: top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New Waived Independent fanout in different clock domains; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:44 PDT
W_FANOUT: top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New Waived Independent fanout in different clock domains; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:44 PDT
W_FANOUT: top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New Waived included in waived paths; set_rule_status run by user default on host smart-0beaafa1-df4b-413e-8977-0b70ed2831a2 at Sunday, 17 December 2023 12:13:44 PDT
W_FANOUT: top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New New