f8b3c19a2| Build Mode | Flow Warnings | Flow Errors | SDC Reviews | SDC Warnings | SDC Erros | Setup Reviews | Setup Warnings | Setup Errors | CDC Reviews | CDC Warnings | CDC Errors |
|---|---|---|---|---|---|---|---|---|---|---|---|
| default | 294 | 0 | 0 | 0 | 0 | 136 | 7 | 0 | 22487 | 0 | 67 |
'default' WARN [#104013] : on line 208 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 42213 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 43264 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 44519 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 90159 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#39270] : on line 900 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 946 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 982 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 984 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 985 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 993 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39336] : on line 871 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 126 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 211 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 283 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 287 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 289 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 301 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 124 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 177 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 179 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25014] : on line 187 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25014] : on line 275 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39073] : on line 893 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 894 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 900 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 967 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 968 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39147] : on line 57 in file /workspace/default/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh
WARN [#39066] : on line 244 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39066] : on line 157 in file /workspace/default/src/lowrisc_ip_lc_ctrl_pkg_0.1/rtl/lc_ctrl_pkg.sv
WARN [#39066] : on line 86 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39066] : on line 188 in file /workspace/default/src/lowrisc_ip_lc_ctrl_pkg_0.1/rtl/lc_ctrl_pkg.sv
WARN [#39066] : on line 112 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39316] : on line 48 in file /workspace/default/src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv
WARN [#39244] : on line 80 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39066] : on line 539 in file /workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_pkg.sv
WARN [#39066] : on line 465 in file /workspace/default/src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv
WARN [#39316] : on line 48 in file /workspace/default/src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv
WARN [#25017] : on line 869 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#26020] : on line 173 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 173 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 175 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 175 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26005] : on line 2 in file /workspace/mnt/repo_top/hw/top_earlgrey/cdc/top_user.env
WARN [#26018] : on line 2 in file /workspace/mnt/repo_top/hw/top_earlgrey/cdc/top_user.env
WARN [#26100] : Exclusive relationships not inherited from reference signal to clock signal "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o" as waveforms propagating to reference signal do not have direct mapping with waveforms specified on clock signal. Exclusive relationships need to be specified manually.
WARN [#26100] : Exclusive relationships not inherited from reference signal to clock signal "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o" as waveforms propagating to reference signal do not have direct mapping with waveforms specified on clock signal. Exclusive relationships need to be specified manually.
WARN [#26100] : Exclusive relationships not inherited from reference signal to clock signal "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o" as waveforms propagating to reference signal do not have direct mapping with waveforms specified on clock signal. Exclusive relationships need to be specified manually.
WARN [#26100] : Exclusive relationships not inherited from reference signal to clock signal "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o" as waveforms propagating to reference signal do not have direct mapping with waveforms specified on clock signal. Exclusive relationships need to be specified manually.
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_status_23_to_1_sync.*") && (ReconSignal=~"*u_spid_status.outclk_p2s_byte_*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.rxf_full_q*") && (ReceivingFlop=~"*u_spi_device.u_sync_rxf*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"*u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (MultiClockDomains=="SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"*u_spi_device.u_memory_2p.*") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_busy") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association == "Blocked-Dangling") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass == "DATA") && (ErrorType == "Uncontrolled-Tx-MASYNC") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_rptr.q[12:2]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass == "CNTL") && (ErrorType == "") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '( (Signal=~"*.u_spi_device.u_reg.u_tpm_did*") || (Signal=~"*.u_spi_device.u_reg.u_tpm_int*") || (Signal=~"*.u_spi_device.u_reg.u_tpm_rid*") ) && (MultiClockDomains=="IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*.u_spi_device.u_reg*u_cmd_info*") && (MultiClockDomains =~ "IO_DIV4_CLK::*SPI_DEV*CLK*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "SPI_DEV_D*") && (ReceivingFlop =~ "*u_spi_device.u_memory_2p*b_rdata*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_uart_core.tx_out_q*") && (ReceivingFlop=~"IO*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver=~"*u_uart_core.tx_out_q*") && (ReceivingFlop=~"IO*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_gpio.gen_filter*") && (ReconSignal=~"*u_gpio.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_alert_handler.gen_alerts*u_secure_anchor_flop*") && (ReceivingFlop=~"*u_*alert_sender*.u_decode_ack*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_alert_handler.gen_alerts*u_secure_anchor_flop*") && (ReceivingFlop=~"*u_*alert_sender*.u_decode_ping*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_abort.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_jedec.st_q.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "SPI_HOST_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "IOA*") && (ReceivingFlop=~"top_earlgrey.u_spi_host0.*.*u_shift_reg*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_lc_ctrl.u_dmi_jtag.*_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.bypass_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.*zero1*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "SPI_HOST*") && (ReceivingFlop=~"*u_pinmux_aon.dio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.intg_err_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_fatal_*_err.q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.core_outputs_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.state_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.alert_set_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.u_s1n_*.fifo_h.rspfifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.gen_regfile_ff*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.load_store_unit_i.rdata_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_prim_lc_sender.gen_flops*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.gen_wkup_detect*.u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "IO*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device*.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device*.u_passthrough.passthrough_s_en*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_passthrough.addr_phase_outclk*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_sys_sel.clk_*_en_q*") && (ReceivingFlop=~"u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_ext_aoff*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff*") && (ReceivingFlop=~"top_earlgrey.u_pwrmgr_aon.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*_i*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"top_earlgrey.u_usbdev.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt.wptr_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.sram_wdata[31:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "USB_*") && (Driver =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"IO*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_ext_*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.*.u_impl_generic.q_o*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.*.*h_o*") && (GatedClock=~ "u_ast.u_*_clk.u_*_osc.u_clk_ckgt.gen_generic.u_impl_generic.clk_o*")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClock=~ "top_earlgrey.u_clkmgr_aon.*.gen_generic.u_impl_generic.clk_o*")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"SPI_DEV_CS_L*") && (ReceivingFlop=~"*u_spi_device.u_spi_tpm.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.u_pinmux_aon.mio_pad_attr_q*") && (ReceivingFlop=~"*u_spi_device.spi_clk_csb_rst_toggle*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"IO*") && (ReceivingFlop=~"*u_spi_device.u_spi_tpm.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.*.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.*.i_dmi_cdc.i_cdc_resp.fifo_rptr*_q[0]*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rv_core_ibex*.*gen_alert_senders*.*alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_flash_ctrl*.*gen_alert_senders*.*alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.u_falut_alert.state_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.*.u_fault_alert_state_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*.u_reg.*.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_sender.alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_sysrst_ctrl_aon.u_reg.*.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_aon_timer_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.u_dio_pad_sleep_statue_en_0.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*meas_ctrl_en_cdc*.id_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*u_io_meas.src_err_req")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_handler.gen_alerts**.u_alert_receiver*.*impl_generic*.q_o*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.i_wake_info.info*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rstmgr_aon.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_ast_clks_byp.*io_clk*src*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "IO_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "*u_pinmux_aon.dio_o*_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.*readbuf*sync.src_level*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.u_readbuffer.*buffer_addr*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.u_readbuffer.watermark_crossed*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.readbuf_addr*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_readcmd.u_*.*_q*") && (ReceivingFlop =~ "*top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host*.q*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host*.*reg*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_xbar_main.u_asf_*.reqfifo.*q*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host0.u_spi_core.u_fsm*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host1.*.q*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.mio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host1.*.*_q*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.mio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.sram_rdata_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_en_q") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_sel") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.all_clks_byp_en_src")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_aoff") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.all_clks_byp_en_src")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_en_q") &&
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_ext*") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_ext_en_q")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.*_clk_byp_dgl.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_sel")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*.u_spi_device.u_reg*u_cmd_info*") && (MultiClockDomains =~ "IO_DIV4_CLK::*SPI_DEV*CLK*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_pinmux_aon.dio_pad_attr_q*.invert")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.spi_clk_csb_rst_toggle")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.sys_clk_tog")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_rptr.q[12:2]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.io_mode_outclk[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.storage*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_sync_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][19:16]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_*fifo.r_rptr_gray_q[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_wptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_rptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_gray_q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Signal =~ "top_earlgrey.u_spi_device.rxf_full_q")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_*xf_ctrl.*ptr*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_*x*.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression 'Driver =~ "*u_lc_ctrl*.u_prim_lc_sender_escalate_en*"' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.num_req_outstanding[8:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_spi_core.u_fsm.speed_cpha1[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0]") && (Association =~ "None")' did not match any (non-) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dn_o.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dp_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dn_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1:0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_en.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:3]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.sram_wdata[31:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.storage[1:0][23:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][31:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_sync_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][31:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "u_ast.padmux2ast_i[4]") && (Signal == "IOB2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Signal =~ "SPI_DEV_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "SPI_HOST_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.in_o") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"IO*") && (ReceivingFlop=~"*u_i2c*.*.u_sync_1*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal =~ "u_ast.u_ast_clks_byp.*u_impl_generic.q_o*") && (ReconSignal=~"top_earlgrey.*.u_reg*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal =~ "*u_pinmux_aon.u_reg.u_wkup_detector*cdc.u_src_to_dst_req*.u_sync1.*u_impl_generic.q_o*") && (ReconSignal=~"top_earlgrey.*.u_reg*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*u_pinmux_aon.dio_pad_attr_q*")' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockTreeSignal=~"u_ast.u_ast_clks_byp.*") && (DrivenFlop =~ "u_ast.u_ast_clks_byp.*")' did not match any (non-Waived) violations for rule S_GENCLK. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockTreeSignal=~"IOC*") && (DrivenFlop =~ "u_ast.u_ast_clks_byp.*")' did not match any (non-Waived) violations for rule S_GENCLK. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"IO*") && (ReceivingFlop=~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_HOST*") && (ReceivingFlop=~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
CLK_GROUPS: RI_SYNC_GRP_1 AST_EXT_CLK_gated 19.7904 19.7904 - - - New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_DIV4_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_CLK 16 16 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_CLK 9.8952 9.8952 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 USB_CLK 19.76 19.76 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASSTHRU_CSB_CLK 25 25 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_HOST_CLK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 AST_EXT_CLK 19.7904 19.7904 - - - New New
CLK_GROUPS: RI_SYNC_GRP_1 JTAG_TCK 47.5 47.5 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 MAIN_CLK 8.5 8.5 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_CSB_CLK 16 16 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASSTHRU_CLK 25 25 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASSTHRU_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_DIV2_CLK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_HOST_PASSTHRU_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_PASSTHRU_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK USB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASSTHRU_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASSTHRU_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_PASSTHRU_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_HOST_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASSTHRU_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASSTHRU_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_PASSTHRU_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_HOST_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK SPI_DEV_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK SPI_DEV_PASSTHRU_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK SPI_DEV_PASSTHRU_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK SPI_DEV_PASSTHRU_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK SPI_HOST_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_DEV_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_DEV_PASSTHRU_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_DEV_PASSTHRU_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_DEV_PASSTHRU_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_HOST_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK SPI_DEV_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK SPI_DEV_PASSTHRU_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK SPI_DEV_PASSTHRU_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK SPI_DEV_PASSTHRU_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK SPI_HOST_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK SPI_DEV_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK SPI_DEV_PASSTHRU_CSB_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK SPI_DEV_PASSTHRU_IN_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK SPI_DEV_PASSTHRU_OUT_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK SPI_HOST_PASSTHRU_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_CSB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CSB_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CSB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASSTHRU_CLK IO_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASSTHRU_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CSB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASSTHRU_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CSB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASSTHRU_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_CSB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_PASSTHRU_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_PASSTHRU_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV4_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:416 New New
CLK_GROUPS: RI_WAVEFORM_ASYNC_0 RI_WAVEFORM_ASYNC_0 8.5 8.5 - - - New New
CLK_GROUPS: RI_WAVEFORM_ASYNC_1 RI_WAVEFORM_ASYNC_1 8.5 8.5 - - - New New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:155 Auto-operator New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:156 Auto-operator New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:157 Auto-operator New
BLACK_BOX: prim_generic_ram_1p-39-32h8000-39 mem prim_generic_ram_1p.sv:48 Auto-large-array New
BLACK_BOX: otbn_mac_bignum (operator) otbn_mac_bignum.sv:101 Auto-operator New
BLACK_BOX: prim_generic_ram_1p-32h4c-32h10000-32h4c mem prim_generic_ram_1p.sv:48 Auto-large-array New
BLACK_BOX: prim_generic_ram_2p top_earlgrey.u_usbdev.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic prim_ram_2p.sv:48 User-defined-module New
BLACK_BOX: prim_packer_fifo-36-9 (operator) prim_packer_fifo.sv:135 Auto-operator New
BLACK_BOX: alert_handler_ping_timer-32h762a1f91-160h375ed89d2a1d32862f7a7785f940950cc1cbdb05 (operator) alert_handler_ping_timer.sv:266 Auto-operator New
BLACK_BOX: prim_generic_ram_2p top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic prim_ram_2p.sv:48 User-defined-module New
MULTCLK_CROSSINGS: u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.in_o top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK top_earlgrey.u_spi_device.u_passthrough.u_pt_isck_cg.gen_generic.u_impl_generic.en_latch top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14] txclockpath23.dbg,smultclkcrossings23.dbg,rxclockpath23.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.clk_o top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK top_earlgrey.u_spi_device.u_passthrough.u_pt_isck_cg.gen_generic.u_impl_generic.en_latch top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14] txclockpath24.dbg,smultclkcrossings24.dbg,rxclockpath24.dbg New New
MULTCLK_CROSSINGS: SPI_DEV_CLK top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK top_earlgrey.u_spi_device.u_passthrough.u_pt_isck_cg.gen_generic.u_impl_generic.en_latch top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14] txclockpath29.dbg,smultclkcrossings29.dbg,rxclockpath29.dbg New New
S_CONF_ENV: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o prim_clock_div.sv:115 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV4_CLK AST_EXT_CLK,IO_CLK IO_DIV4_CLK constraints.sdc.env:139 PostResetPhase prim_clock_div-32h4 New
S_CONF_ENV: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o prim_clock_div.sv:115 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV2_CLK AST_EXT_CLK,IO_CLK IO_DIV2_CLK constraints.sdc.env:135 PostResetPhase,sconfenv49.dbg prim_clock_div New
S_CONF_ENV: top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o prim_clock_buf.sv:42 IO_DIV2_CLK create_clock waveform=SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK IO_DIV2_CLK SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK constraints.sdc.env:115,constraints.sdc.env:127 PostResetPhase,sconfenv50.dbg prim_clock_buf-1h1 New
S_MISSING_SPEC: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o prim_clock_div.sv:115 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV4_CLK AST_EXT_CLK constraints.sdc.env:139 prim_clock_div-32h4 New
S_MISSING_SPEC: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o prim_clock_div.sv:115 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV2_CLK AST_EXT_CLK constraints.sdc.env:135 prim_clock_div New
S_MISSING_SPEC: top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o prim_clock_buf.sv:42 IO_DIV2_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK create_clock waveform=SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK IO_DIV2_CLK constraints.sdc.env:143,constraints.sdc.env:151 prim_clock_buf-1=1h1 New
S_MISSING_SPEC: top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o prim_clock_buf.sv:42 IO_DIV2_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK create_clock waveform=SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK IO_DIV2_CLK constraints.sdc.env:147,constraints.sdc.env:155 prim_clock_buf-1=1h1 New
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100427.dbg
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100428.dbg
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100429.dbg
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100430.dbg
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100431.dbg
CNTL: USB_P top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100432.dbg
CNTL: USB_P top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_activity.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100433.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[5].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_N top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK_gated prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_bus_reset.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: USB_P top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[1] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[1] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100434.dbg
CNTL: USB_P top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[3] RI_WAVEFORM_ASYNC_0::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[3] 2 None SlowToFast Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100435.dbg
CNTL: USB_N top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[2:1] RI_WAVEFORM_ASYNC_1::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[2:1] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: SPI_DEV_CS_L top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SameFreq Flat-To-Flat chip_earlgrey_asic New Missing-Feedback,MASYNC,cntl100436.dbg
CNTL: SPI_DEV_CS_L top_earlgrey.u_spi_device.u_csb_edge_sysclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_csb_edge_sysclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl100437.dbg
CNTL: u_ast.io_clk_byp_ack_o[3:0] top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl100438.dbg
CNTL: u_ast.all_clk_byp_ack_o[3:0] top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New cntl100439.dbg
CNTL: top_earlgrey.u_spi_device.rxf_full_q top_earlgrey.u_spi_device.u_sync_rxf.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sync_rxf.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl100440.dbg
CNTL: top_earlgrey.u_spi_device.sys_clk_tog top_earlgrey.u_spi_device.u_sck_tog_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sck_tog_edge.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl100441.dbg
CNTL: top_earlgrey.u_spi_device.txf_empty_q top_earlgrey.u_spi_device.u_sync_txe.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_sync_txe.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl100442.dbg
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100443.dbg
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_rv_core_ibex.core_sleep_q top_earlgrey.u_pwrmgr_aon.u_cdc.u_sleeping_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_pwrmgr_aon.u_cdc.u_sleeping_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback FastToSlow Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100444.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[15] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[15] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100445.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_payload_not_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[72] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[72] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100446.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[23] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[23] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100447.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[31] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[31] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100448.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_payload_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[73] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[73] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100449.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_rx_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[78] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[78] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100450.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_fmt_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[79] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[79] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100451.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_sda_unstable.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[85] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[85] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100452.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_cmd_complete.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[86] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[86] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100453.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_acq_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[89] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[89] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100454.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_host_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[91] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[91] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100455.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_rx_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[93] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[93] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100456.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_fmt_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[94] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[94] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100457.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_sda_unstable.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[100] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[100] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100458.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_cmd_complete.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[101] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[101] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100459.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_acq_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[104] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[104] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100460.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_host_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[106] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[106] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100461.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_rx_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[108] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[108] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100462.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_fmt_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[109] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[109] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100463.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_sda_unstable.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[115] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[115] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100464.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_cmd_complete.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[116] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[116] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100465.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_acq_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[119] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[119] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100466.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_host_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[121] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[121] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100467.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[4] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[4] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100468.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[12] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[12] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100469.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[20] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[20] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100470.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[28] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[28] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100471.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_cmdfifo_not_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[71] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[71] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100472.dbg
CNTL: top_earlgrey.u_gpio.intr_hw.intr_o[31:0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[64:33] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[64:33] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100473.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[19] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[19] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100474.dbg
CNTL: top_earlgrey.u_sensor_ctrl.u_init_intr.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[158] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[158] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100475.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_nak.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[81] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[81] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100476.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_nak.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[96] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[96] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100477.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_nak.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[111] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[111] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100478.dbg
CNTL: top_earlgrey.u_aon_timer_aon.u_intr_hw.intr_o[1:0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[156:155] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[156:155] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100479.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxoverflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[69] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[69] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100480.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_txunderflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[70] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[70] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100481.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_readbuf_flip.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[75] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[75] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100482.dbg
CNTL: top_earlgrey.u_otp_ctrl.u_intr_operation_done.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[125] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[125] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100483.dbg
CNTL: top_earlgrey.u_sysrst_ctrl_aon.u_prim_intr_hw.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[153] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[153] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100484.dbg
CNTL: top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[124] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[124] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100485.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100486.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[11] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[11] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100487.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100488.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_tx_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[27] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[27] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100489.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[87] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[87] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100490.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_unexp_stop.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[90] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[90] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100491.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[102] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[102] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100492.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_unexp_stop.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[105] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[105] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100493.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[117] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[117] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100494.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_unexp_stop.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[120] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[120] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100495.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[80] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[80] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100496.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_tx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[88] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[88] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100497.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[95] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[95] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100498.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_tx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[103] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[103] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100499.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_rx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[110] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[110] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100500.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_tx_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[118] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[118] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100501.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_scl_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[112] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[112] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100502.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_stretch_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[99] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[99] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100503.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_stretch_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[114] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[114] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100504.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classa.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[127] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[127] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100505.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classb.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[128] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[128] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100506.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classc.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[129] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[129] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100507.dbg
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_irq_classd.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[130] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[130] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100508.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_tpm_cmdaddr_notempty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[76] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[76] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100509.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_scl_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[82] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[82] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100510.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_sda_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[83] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[83] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100511.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_scl_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[97] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[97] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100512.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_sda_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[98] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[98] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100513.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_fmt_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[77] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[77] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100514.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_sda_interference.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[113] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[113] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100515.dbg
CNTL: top_earlgrey.u_pattgen.u_pattgen_core.intr_hw_done_ch0.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[122] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[122] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100516.dbg
CNTL: top_earlgrey.u_pattgen.u_pattgen_core.intr_hw_done_ch1.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[123] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[123] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100517.dbg
CNTL: top_earlgrey.u_adc_ctrl_aon.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[154] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[154] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100518.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxerr.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[68] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[68] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100519.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_txlvl.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[67] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[67] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100520.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxlvl.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[66] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[66] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100521.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.intr_wakeup.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[152] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[152] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100522.dbg
CNTL: top_earlgrey.u_sensor_ctrl.u_io_intr.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[157] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[157] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100523.dbg
CNTL: top_earlgrey.u_otp_ctrl.u_intr_error.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[126] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[126] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100524.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_rxf.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[65] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[65] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100525.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[32] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[32] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100526.dbg
CNTL: top_earlgrey.u_spi_device.u_intr_readbuf_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[74] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[74] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100527.dbg
CNTL: top_earlgrey.u_i2c1.i2c_core.intr_hw_fmt_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[92] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[92] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100528.dbg
CNTL: top_earlgrey.u_i2c2.i2c_core.intr_hw_fmt_threshold.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[107] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[107] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100529.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[1] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[1] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100530.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[2] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[2] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100531.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[5] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[5] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100532.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[6] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[6] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100533.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[9] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[9] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100534.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[10] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[10] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100535.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[13] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[13] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100536.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[14] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[14] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100537.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[18] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[18] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100538.dbg
CNTL: top_earlgrey.u_i2c0.i2c_core.intr_hw_stretch_timeout.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[84] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[84] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100539.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[24] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[24] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100540.dbg
CNTL: top_earlgrey.u_uart1.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[16] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[16] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100541.dbg
CNTL: top_earlgrey.u_uart0.uart_core.intr_hw_rx_parity_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[8] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[8] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100542.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[30] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[30] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100543.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[26] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[26] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100544.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[17] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[17] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100545.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[21] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[21] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100546.dbg
CNTL: top_earlgrey.u_uart2.uart_core.intr_hw_rx_break_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[22] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[22] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100547.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_tx_watermark.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[25] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[25] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100548.dbg
CNTL: top_earlgrey.u_uart3.uart_core.intr_hw_rx_frame_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[29] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[29] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100549.dbg
CNTL: top_earlgrey.u_usbdev.intr_powered.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[150] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[150] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100550.dbg
CNTL: top_earlgrey.u_usbdev.intr_hw_pkt_sent.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[136] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[136] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100551.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_resume.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[141] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[141] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100552.dbg
CNTL: top_earlgrey.u_usbdev.intr_av_overflow.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[144] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[144] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100553.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_in_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[145] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[145] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100554.dbg
CNTL: top_earlgrey.u_usbdev.intr_frame.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[149] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[149] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100555.dbg
CNTL: top_earlgrey.u_usbdev.intr_disconnected.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[137] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[137] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100556.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_suspend.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[140] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[140] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100557.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_out_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[151] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[151] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100558.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_full.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[143] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[143] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100559.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_crc_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[146] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[146] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100560.dbg
CNTL: top_earlgrey.u_usbdev.intr_av_empty.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[142] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[142] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100561.dbg
CNTL: top_earlgrey.u_usbdev.intr_hw_pkt_received.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[135] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[135] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100562.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_bitstuff_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[148] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[148] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100563.dbg
CNTL: top_earlgrey.u_usbdev.intr_host_lost.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[138] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[138] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100564.dbg
CNTL: top_earlgrey.u_usbdev.intr_rx_pid_err.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[147] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[147] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100565.dbg
CNTL: top_earlgrey.u_usbdev.intr_link_reset.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[139] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[139] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100566.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100567.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100568.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100569.dbg
CNTL: top_earlgrey.u_aon_timer_aon.u_intr_hw.intr_o[1] top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100570.dbg
CNTL: top_earlgrey.u_spi_host0.intr_hw_error.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[131] AST_EXT_CLK,IO_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[131] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100571.dbg
CNTL: top_earlgrey.u_spi_host0.intr_hw_spi_event.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[132] AST_EXT_CLK,IO_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[132] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100572.dbg
CNTL: top_earlgrey.u_spi_host1.intr_hw_error.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[133] IO_DIV2_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[133] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100573.dbg
CNTL: top_earlgrey.u_spi_host1.intr_hw_spi_event.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[134] IO_DIV2_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[134] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100574.dbg
CNTL: top_earlgrey.u_spi_device.spi_clk_csb_rst_toggle top_earlgrey.u_spi_device.u_clk_csb_edge_0.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_clk_csb_edge_0.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spi_device New cntl100575.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[6].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_spi_device.u_rxf_overflow.src_level top_earlgrey.u_spi_device.u_rxf_overflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_rxf_overflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat prim_pulse_sync New cntl100576.dbg
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,cntl100577.dbg
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[3].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[6].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[7].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[5].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[8].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[9].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[4].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56.q[5:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[1].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[2] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[2] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,cntl100578.dbg
CNTL: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[0].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[3] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[3] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[28].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].invert top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_usbdev.i_usbdev_iomux.cdc_io_to_usb.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None MixedFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New MASYNC,--
CNTL: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[13].invert top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SameFreq Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New Missing-Feedback,MASYNC,--
CNTL: top_earlgrey.u_spi_device.u_txf_underflow.src_level top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat prim_pulse_sync New cntl100579.dbg
CNTL: top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q[0] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SameFreq Flat-To-Flat spi_device New Missing-Feedback,cntl100580.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_1.q[0] top_earlgrey.u_rstmgr_aon.u_d0_spi_host0.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_spi_host0.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat rstmgr New cntl100581.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_2.q[0] top_earlgrey.u_rstmgr_aon.u_d0_spi_host1.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_spi_host1.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat rstmgr New cntl100582.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_reg.u_sw_rst_ctrl_n_3.q[0] top_earlgrey.u_rstmgr_aon.u_d0_usb.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_usb.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat rstmgr New cntl100583.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl100584.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl100585.dbg
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100586.dbg
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans New cntl100587.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.hold_err top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl100588.dbg
CNTL: top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0] top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100589.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.combined_en_q top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl100590.dbg
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[21:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32hf17463db-20=160h7d3352c576e13e90efc895c136094776203e9b4d-21=32h10800-22=32h10810-24=128hc10d8dd7f82d15844e53a6af23823858-25=64h2f4520c32d5e0d6d New cntl100591.dbg
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_ping_timer.u_prim_count_esc_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[21:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32hf17463db-20=160h7d3352c576e13e90efc895c136094776203e9b4d-21=32h10800-22=32h10810-24=128hc10d8dd7f82d15844e53a6af23823858-25=64h2f4520c32d5e0d6d New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_accu.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_accu.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[2].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[3].u_esc_timer.u_prim_count.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[0].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.esc_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.gen_classes[1].u_esc_timer.u_prim_count.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_decode_esc.level_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32hf17463db-20=160h7d3352c576e13e90efc895c136094776203e9b4d-21=32h10800-22=32h10810-24=128hc10d8dd7f82d15844e53a6af23823858-25=64h2f4520c32d5e0d6d New --
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.state_q[2:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat rv_core_ibex-19=32hf17463db-20=160h7d3352c576e13e90efc895c136094776203e9b4d-21=32h10800-22=32h10810-24=128hc10d8dd7f82d15844e53a6af23823858-25=64h2f4520c32d5e0d6d New --
CNTL: top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.ping_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_alert_handler.u_ping_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[8:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.combined_en_q top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl100592.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.combined_en_q top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat clkmgr_trans New cntl100593.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.combined_en_q top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat clkmgr_trans-1h0 New cntl100594.dbg
CNTL: top_earlgrey.u_spi_device.u_spid_addr_4b.spi_cfg_addr_4b_en_o top_earlgrey.u_spi_device.u_spid_addr_4b.u_spi2sys_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spid_addr_4b.u_spi2sys_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat spid_addr_4b New cntl100595.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100596.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[7].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback FastToSlow Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100597.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_35.rspfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100598.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_35.rspfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100599.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100600.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100601.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_37.rspfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100602.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_37.rspfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100603.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100604.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100605.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_39.rspfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100606.dbg
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100607.dbg
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_xbar_main.u_asf_39.rspfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100608.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_41.reqfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_41.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_41.reqfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100609.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_41.reqfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_41.reqfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_41.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h6b-32h1-1h0-1h1 New cntl100610.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_41.rspfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100611.dbg
CNTL: top_earlgrey.u_xbar_main.u_asf_41.rspfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_fifo_async-32h40-32h1-1h0-1h1 New cntl100612.dbg
CNTL: top_earlgrey.u_spi_device.u_upload.u_cmdfifo.r_rptr_gray_q[4:0] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 Data SameFreq Flat-To-Flat prim_fifo_async_sram_adapter-0=32h8-2=32ha-4=10h380 New Missing-Feedback,cntl100613.dbg
CNTL: top_earlgrey.u_spi_device.u_upload.u_cmdfifo.w_wptr_gray_q[4:0] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 None SameFreq Flat-To-Flat prim_fifo_async_sram_adapter-0=32h8-2=32ha-4=10h380 New cntl100614.dbg
CNTL: top_earlgrey.u_spi_device.u_upload.u_addrfifo.r_rptr_gray_q[4:0] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 Data SameFreq Flat-To-Flat prim_fifo_async_sram_adapter-2=32ha-4=10h390 New Missing-Feedback,cntl100615.dbg
CNTL: top_earlgrey.u_spi_device.u_upload.u_addrfifo.w_wptr_gray_q[4:0] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 None SameFreq Flat-To-Flat prim_fifo_async_sram_adapter-2=32ha-4=10h390 New cntl100616.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_io_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_io_peri_sw_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat clkmgr New cntl100617.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[8].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_aes_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat clkmgr New cntl100618.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_usb_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_usb_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_usb_peri_sw_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat clkmgr New cntl100619.dbg
CNTL: top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[3:0] top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 None MixedFreq Flat-To-Flat prim_fifo_async-32h8-32h8 New cntl100620.dbg
CNTL: top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0] top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 Data MixedFreq Flat-To-Flat prim_fifo_async-32h8-32h8 New Missing-Feedback,cntl100621.dbg
CNTL: top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_gray_q[3:0] top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 None MixedFreq Flat-To-Flat prim_fifo_async-32h8-32h8 New cntl100622.dbg
CNTL: top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_gray_q[3:0] top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 None MixedFreq Flat-To-Flat prim_fifo_async-32h8-32h8 New cntl100623.dbg
CNTL: top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.fifo_rptr_gray_q[4:0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 Is-Feedback SameFreq Flat-To-Flat prim_fifo_async-32h20-32h10-1h1 New cntl100624.dbg
CNTL: top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.fifo_wptr_gray_q[4:0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 Data,Has-Feedback SameFreq Flat-To-Flat prim_fifo_async-32h20-32h10-1h1 New cntl100625.dbg
CNTL: top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.fifo_rptr_gray_q[6:0] top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[6:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[6:0] 2 Data,Has-Feedback SameFreq Flat-To-Flat prim_fifo_async-32h8-32h40-1h1 New cntl100626.dbg
CNTL: top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.fifo_wptr_gray_q[6:0] top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[6:0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[6:0] 2 Data,Has-Feedback SameFreq Flat-To-Flat prim_fifo_async-32h8-32h40-1h1 New cntl100627.dbg
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100628.dbg
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_hmac_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback SlowToFast Flat-To-Flat clkmgr New cntl100629.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_kmac_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat clkmgr New cntl100630.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_otbn_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat clkmgr New cntl100631.dbg
CNTL: top_earlgrey.u_spi_device.u_flash_readbuf_flip_pulse_sync.src_level top_earlgrey.u_spi_device.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat prim_pulse_sync New cntl100632.dbg
CNTL: top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.src_level top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SameFreq Flat-To-Flat prim_pulse_sync New Missing-Feedback,cntl100633.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_div2_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat clkmgr New cntl100634.dbg
CNTL: top_earlgrey.u_flash_ctrl.u_reg_idle.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_pwrmgr_aon.u_cdc.u_sync_flash_idle.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_pwrmgr_aon.u_cdc.u_sync_flash_idle.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback FastToSlow Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100635.dbg
CNTL: top_earlgrey.u_spi_device.u_flash_readbuf_watermark_pulse_sync.src_level top_earlgrey.u_spi_device.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SameFreq Flat-To-Flat prim_pulse_sync New cntl100636.dbg
CNTL: top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_rptr_gray_q[1:0] top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 Data SameFreq Flat-To-Flat prim_fifo_async-32h20-32h2-1h1 New Missing-Feedback,cntl100637.dbg
CNTL: top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_wptr_gray_q[1:0] top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 Data,Has-Feedback SameFreq Flat-To-Flat prim_fifo_async-32h20-32h2-1h1 New cntl100638.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[9].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_io_meas.u_err_sync.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_clkmgr_aon.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100639.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_io_meas.u_err_sync.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_clkmgr_aon.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100640.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100641.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100642.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_otp_ctrl.u_keygmr_key_valid.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New Missing-Feedback,cntl100643.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100644.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100645.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_clkmgr_aon.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_clkmgr_aon.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100646.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_clkmgr_aon.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100647.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100648.dbg
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100649.dbg
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[1].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100650.dbg
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100651.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100652.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100653.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg.q[9:0] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SlowToFast Flat-To-Flat prim_pulse_sync New Missing-Feedback,cntl100654.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_clkmgr_aon.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100655.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_clkmgr_aon.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100656.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100657.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New cntl100658.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg.q[8:0] top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr_reg_top New --
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SlowToFast Flat-To-Flat prim_pulse_sync New Missing-Feedback,cntl100659.dbg
CNTL: top_earlgrey.u_pwrmgr_aon.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_usb_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_usb_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100660.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[10].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SlowToFast Flat-To-Flat prim_pulse_sync New Missing-Feedback,cntl100661.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100662.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100663.dbg
CNTL: top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][15:8] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100664.dbg
CNTL: top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100665.dbg
CNTL: top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][31:24] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][23:16] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100666.dbg
CNTL: top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 Is-Feedback SlowToFast Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data SlowToFast Flat-To-Flat prim_pulse_sync New Missing-Feedback,cntl100667.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100668.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100669.dbg
CNTL: top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.fifo_rptr_gray_q[1:0] top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 Is-Feedback SameFreq Flat-To-Flat prim_fifo_async-32h18-32h2-1h1 New cntl100670.dbg
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100671.dbg
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.fifo_wptr_gray_q[1:0] top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 Data,Has-Feedback SameFreq Flat-To-Flat prim_fifo_async-32h18-32h2-1h1 New cntl100672.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_pulse_sync New cntl100673.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100674.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100675.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_pulse_sync New cntl100676.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_pulse_sync New cntl100677.dbg
CNTL: top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_sync_reqack New cntl100678.dbg
CNTL: top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat prim_sync_reqack New cntl100679.dbg
CNTL: top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_sync_reqack New cntl100680.dbg
CNTL: top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat prim_sync_reqack New cntl100681.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[11].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100682.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_pulse_sync New cntl100683.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV2_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_pulse_sync New cntl100684.dbg
CNTL: top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100685.dbg
CNTL: top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,JTAG_TCK,MAIN_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100686.dbg
CNTL: top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,JTAG_TCK,MAIN_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100687.dbg
CNTL: top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100688.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat clkmgr New cntl100689.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_usb_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_usb_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_usb_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat clkmgr New cntl100690.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_main_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_main_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat clkmgr New cntl100691.dbg
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100692.dbg
CNTL: IOB12 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC11 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC12 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR10 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR11 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB11 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB10 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC9 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA1 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA2 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA3 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA4 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA5 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR6 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR7 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR5 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR4 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR0 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA0 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR13 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC8 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA7 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA6 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR2 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB0 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC10 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR12 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_clkmgr_aon.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[1] IO_DIV2_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic.q_o[1] 2 Is-Feedback FastToSlow Flat-To-Flat clkmgr New cntl100693.dbg
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_sync_reqack New cntl100694.dbg
CNTL: top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat prim_sync_reqack New cntl100695.dbg
CNTL: top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK prim_generic_flop.sv:21 top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100696.dbg
CNTL: top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK,JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100697.dbg
CNTL: top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_pwrmgr_aon.u_ndm_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_pwrmgr_aon.u_ndm_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New cntl100698.dbg
CNTL: top_earlgrey.u_rv_dm.u_tlul_lc_gate_rom.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[8:0] top_earlgrey.u_pwrmgr_aon.u_ndm_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_pwrmgr_aon.u_ndm_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat top_earlgrey-2=1h1-11=1h1-12=573h4c000000460000004e0000004a000000480000003c00000036000000320000003400000000000000020000007003690000000092400000092000000012480000002480000-21=1h1 New --
CNTL: top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK,JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100699.dbg
CNTL: top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK prim_generic_flop.sv:21 top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback MixedFreq Flat-To-Flat prim_sync_reqack-1=1h1 New cntl100700.dbg
CNTL: top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback SlowToFast Flat-To-Flat prim_sync_reqack New cntl100701.dbg
CNTL: top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Is-Feedback FastToSlow Flat-To-Flat prim_sync_reqack New cntl100702.dbg
CNTL: IOR3 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] JTAG_TCK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[12].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100703.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100704.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100705.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100706.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_d0_usb.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_rstmgr_aon.u_d0_usb.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_usb.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100707.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_d0_usb.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_rstmgr_aon.u_d0_usb.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_d0_usb.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100708.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback FastToSlow Flat-To-Flat prim_pulse_sync New cntl100709.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.dst_ack_q top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat prim_sync_reqack New cntl100710.dbg
CNTL: top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.src_req_q top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None SlowToFast Flat-To-Flat prim_sync_reqack New cntl100711.dbg
CNTL: top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_clkmgr_aon.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 Data,Has-Feedback FastToSlow Flat-To-Flat prim_pulse_sync New cntl100712.dbg
CNTL: IOB6 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,cntl100713.dbg
CNTL: IOC1 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC5 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC4 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOR1 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC3 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC2 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC0 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOA8 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB9 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB8 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB7 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOC7 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB5 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB4 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB3 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB2 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_gpio.gen_filter[13].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 None FastToSlow Flat-To-Flat chip_earlgrey_asic New MASYNC,--
CNTL: IOB1