be3d980075| Build Mode | Flow Warnings | Flow Errors | SDC Reviews | SDC Warnings | SDC Erros | Setup Reviews | Setup Warnings | Setup Errors | CDC Reviews | CDC Warnings | CDC Errors |
|---|---|---|---|---|---|---|---|---|---|---|---|
| default | 497 | 0 | 0 | 0 | 0 | 238 | 6 | 1 | 33015 | 0 | 1533 |
'default' WARN [#104013] : on line 208 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 6067 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 42213 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 43264 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 44519 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#104001] : on line 90159 in file /workspace/mnt/repo_top/hw/top_earlgrey/ip/ast/lib/ast.lib
WARN [#39270] : on line 890 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 936 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 972 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 974 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 975 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 983 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39336] : on line 861 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39270] : on line 126 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 211 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 283 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 287 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 289 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39270] : on line 301 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 124 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 177 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25015] : on line 179 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25014] : on line 187 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#25014] : on line 275 in file /workspace/default/syn-icarus/RI_compiled_libs/verix_libs/ast.v
WARN [#39073] : on line 883 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 884 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 890 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 957 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 958 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39073] : on line 968 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#39147] : on line 57 in file /workspace/default/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh
WARN [#39066] : on line 244 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39066] : on line 157 in file /workspace/default/src/lowrisc_ip_lc_ctrl_pkg_0.1/rtl/lc_ctrl_pkg.sv
WARN [#39066] : on line 188 in file /workspace/default/src/lowrisc_ip_lc_ctrl_pkg_0.1/rtl/lc_ctrl_pkg.sv
WARN [#39066] : on line 86 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39066] : on line 112 in file /workspace/default/src/lowrisc_prim_mubi_0.1/rtl/prim_mubi_pkg.sv
WARN [#39316] : on line 48 in file /workspace/default/src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv
WARN [#39244] : on line 80 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 83 in file /workspace/default/src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv
WARN [#39244] : on line 175 in file /workspace/default/src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv
WARN [#39066] : on line 543 in file /workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_pkg.sv
WARN [#39066] : on line 389 in file /workspace/default/src/lowrisc_ip_sha3_0.1/rtl/keccak_2share.sv
WARN [#39316] : on line 48 in file /workspace/default/src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv
WARN [#25017] : on line 859 in file /workspace/default/src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv
WARN [#74005] : chip_earlgrey_asic.sdc:236 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:235 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_dft/prim_clock_buf_tck/clk_o]] on line 236 did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:235 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:234 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == out} -of_objects [get_nets -segments -of_objects [get_pins top_earlgrey/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_dft/prim_clock_buf_tck/clk_o]]] on line 235 did not produce any result
WARN [#74707] : chip_earlgrey_asic.sdc:360 option '-of_objects': invalid collection type
WARN [#74005] : chip_earlgrey_asic.sdc:360 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:360 expected arguments '<ref_objects>', but command [get_pins -leaf -of_objects [get_pins {top_earlgrey/u_spi_device/u_csb_buf/out_o[0]}]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:415 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:415 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:415 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:415 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:415 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:415 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#74707] : chip_earlgrey_asic.sdc:465 option '-of_objects': invalid collection type
WARN [#74005] : chip_earlgrey_asic.sdc:465 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:465 expected arguments '<ref_objects>', but command [get_pins -leaf -of_objects [get_pins {top_earlgrey/u_spi_device/u_csb_buf/out_o[0]}]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:520 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:520 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:520 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:520 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:520 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:520 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:662 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:662 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:662 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:662 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:662 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:662 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:851 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:851 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:851 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:851 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:851 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:851 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:996 pattern 'u_ast/u_scan_clk/in_i*' results in an empty collection (matched pattern components: u_ast)
WARN [#74731] : chip_earlgrey_asic.sdc:996 option '-of_objects' expected arguments, but command [get_pins u_ast/u_scan_clk/in_i*] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:996 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:996 option '-of_objects' expected arguments, but command [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]] did not produce any result
WARN [#74005] : chip_earlgrey_asic.sdc:996 pattern '' results in an empty collection (matched pattern components: None)
WARN [#74731] : chip_earlgrey_asic.sdc:996 expected arguments '<ref_objects>', but command [get_pins -leaf -filter {@pin_direction == in} -of_objects [get_nets -segments -of_objects [get_pins u_ast/u_scan_clk/in_i*]]] did not produce any result
WARN [#26020] : on line 241 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 241 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 243 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26020] : on line 243 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26080] : on line 445 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26080] : on line 447 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26005] : on line 2 in file /workspace/mnt/repo_top/hw/top_earlgrey/cdc/top_user.env
WARN [#26018] : on line 2 in file /workspace/mnt/repo_top/hw/top_earlgrey/cdc/top_user.env
WARN [#26049] : on line 449 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#26049] : on line 449 in file /workspace/default/syn-icarus/constraints.sdc.env
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"*u_spi_device.u_reg.u_control_mode.q*") && (ReceivingFlop=~"*u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_status_23_to_1_sync.*") && (ReconSignal=~"*u_spid_status.outclk_p2s_byte_*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.rxf_full_q*") && (ReceivingFlop=~"*u_spi_device.u_sync_rxf*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"*u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (MultiClockDomains=="SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"*u_spi_device.u_memory_2p.*") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_fwmode.u_*x_fifo.fifo_*ptr*_q*") && (ReceivingFlop=~"*u_spi_device.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*.u_spi_device.u_reg.u_rxf_ptr_rptr*") && (ReceivingFlop=~"*.u_spi_device.u_fwmode*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q[0]") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_busy") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_busy_clr_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_spid_status.u_busy_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association == "Blocked-Dangling") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_spid_status.u_status_23_to_1_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.src_level") && (Association == "Data") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_spi_device.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass == "DATA") && (ErrorType == "Uncontrolled-Tx-MASYNC") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_rptr.q[12:2]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass == "CNTL") && (ErrorType == "") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK,SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:2]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_rx_full.q[0]") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_rx_watermark.q[0]") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.rdata_o[7:0]")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage[7:0][7:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.rdata_o[7:0]")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.rxlvl") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:0]") && (ReceivingFlop == "top_earlgrey.u_spi_device.txlvl") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal == "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:2]") && (ReceivingFlop == "top_earlgrey.u_spi_device.sram_rxf_full_q") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Association == "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '( (Signal=~"*.u_spi_device.u_reg.u_tpm_did*") || (Signal=~"*.u_spi_device.u_reg.u_tpm_int*") || (Signal=~"*.u_spi_device.u_reg.u_tpm_rid*") ) && (MultiClockDomains=="IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*u_spi_device.u_reg.u_cmd_info*") && ((MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") || (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK"))' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*.u_spi_device.u_reg.u_control_abort*") && (ReceivingFlop=~"*.u_spi_device.u_fwmode*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*.u_spi_device.u_reg*u_cmd_info*") && (MultiClockDomains =~ "IO_DIV4_CLK::*SPI_DEV*CLK*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*u_spi_device*io_mode_outclk*") && (ReceivingFlop =~ "*u_spi_device.u_memory_2p*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "SPI_DEV_D*") && (ReceivingFlop =~ "*u_spi_device.u_memory_2p*b_rdata*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '( (ReceivingFlop=~"*u_spi_device.u_fwmode.u_*xf_ctrl.*") || (ReceivingFlop=~"*u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr*") || (ReceivingFlop=~"*u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr*") ) && (MultiClockDomains=~"IO_DIV4_CLK::*SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClock=~"*.u_spi_device.clk_spi_*") || (GatedClock=~"*.u_spi_device.u_sram_clk_*")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_uart_core.tx_out_q*") && (ReceivingFlop=~"IO*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver=~"*u_uart_core.tx_out_q*") && (ReceivingFlop=~"IO*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_gpio.gen_filter*") && (ReconSignal=~"*u_gpio.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_alert_handler.gen_alerts*u_secure_anchor_flop*") && (ReceivingFlop=~"*u_*alert_sender*.u_decode_ack*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_alert_handler.gen_alerts*u_secure_anchor_flop*") && (ReceivingFlop=~"*u_*alert_sender*.u_decode_ping*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_abort.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_jedec.st_q.*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_cmdparse.cmd_info_q.addr_mode*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "SPI_HOST_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "IOA*") && (ReceivingFlop=~"top_earlgrey.u_spi_host0.*.*u_shift_reg*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_lc_ctrl.u_dmi_jtag.*_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.bypass_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_rv_dm.u_lc_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_rv_dm.dap.*zero1*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "SPI_HOST*") && (ReceivingFlop=~"*u_pinmux_aon.dio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.*num_req_outstanding*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.intg_err_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_fatal_*_err.q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.core_outputs_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.state_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.alert_set_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.u_s1n_*.fifo_h.rspfifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.gen_regfile_ff*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.load_store_unit_i.rdata_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.u_prim_lc_sender.gen_flops*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.reqfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_DEV*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_DEV*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.gen_wkup_detect*.u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*SPI_*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "IO*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device*.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device*.u_passthrough.passthrough_s_en*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_passthrough.addr_phase_outclk*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage*") && (ReceivingFlop=~"top_earlgrey.u_usbdev.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_sys_sel.clk_*_en_q*") && (ReceivingFlop=~"u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_ext_aoff*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff*") && (ReceivingFlop=~"top_earlgrey.u_pwrmgr_aon.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.a_*_i*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop=~"top_earlgrey.u_usbdev.gen_no_stubbed_memory.u_memory_2p.i_prim_ram_2p_async_adv.u_mem.gen_generic.u_impl_generic.a_*_i*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop=~"top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "top_earlgrey.u_xbar_main.u_asf_*.rspfifo.storage[0]*") && (ReceivingFlop=~"top_earlgrey.u_xbar_main.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt.wptr_o*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.sram_wdata[31:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Driver =~ "IOR2")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[15:0]") && (Driver =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.data_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "USB_*") && (Driver =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Driver =~ "top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Driver =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"top_earlgrey.u_pinmux_aon.*invert") && (GatedClock=~ "top_earlgrey.u_rv_dm.jtag_in_int.tck")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.*q_o*") && (GatedClock=~ "top_earlgrey.u_rv_dm.jtag_in_int.tck")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q*") && (GatedClock=~ "top_earlgrey.u_rv_dm.jtag_in_int.tck")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"IO*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_ext_*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.*.u_impl_generic.q_o*") && (GatedClock=~ "u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_o")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClockInput=~"u_ast.*.*h_o*") && (GatedClock=~ "u_ast.u_*_clk.u_*_osc.u_clk_ckgt.gen_generic.u_impl_generic.clk_o*")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(GatedClock=~ "top_earlgrey.u_clkmgr_aon.*.gen_generic.u_impl_generic.clk_o*")' did not match any (non-Waived) violations for rule W_G_CLK_GLITCH. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"SPI_DEV_CS_L*") && (ReceivingFlop=~"*u_spi_device.u_spi_tpm.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.u_pinmux_aon.mio_pad_attr_q*") && (ReceivingFlop=~"*u_spi_device.spi_clk_csb_rst_toggle*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.u_pinmux_aon.mio_pad_attr_q*") && (ReceivingFlop=~"*u_spi_device.spi_clk_csb_rst_toggle*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"IO*") && (ReceivingFlop=~"*u_spi_device.u_spi_tpm.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"SPI_DEV_CS_L") && (ReceivingFlop=~"*u_spi_device.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.u_spi_device.u_reg.u_control*.q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.u_spi_device.u_reg.u_control*.q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(DrivingSignal=~"top_earlgrey.*.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.*.i_dmi_cdc.i_cdc_resp.fifo_rptr*_q[0]*")' did not match any (non-Waived) violations for rule W_ASYNC_RST_FLOPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rv_core_ibex*.*gen_alert_senders*.*alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_flash_ctrl*.*gen_alert_senders*.*alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.u_falut_alert.state_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_keymgr.*.u_fault_alert_state_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*.u_reg.*.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_sender.alert_test_seq_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_sysrst_ctrl_aon.u_reg.*.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_aon_timer_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pinmux_aon.u_reg.*.u_dio_pad_sleep_statue_en_0.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*meas_ctrl_en_cdc*.id_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_clkmgr_aon.u_reg.*.*u_io_meas.src_err_req")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_alert_handler.gen_alerts**.u_alert_receiver*.*impl_generic*.q_o*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_kmac.gen_entropy.*.u_lfsr_chunk.lfsr_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_pwrmgr_aon.i_wake_info.info*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_rstmgr_aon.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.u_intr_state.q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_adc_ctrl_aon.u_reg.*.src_busy_q*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal=~"*u_sync_1.gen_generic.u_impl_generic.q_o**") && (ReconSignal=~"*u_ast_clks_byp.*io_clk*src*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "IO_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "*u_pinmux_aon.dio_o*_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.*readbuf*sync.src_level*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.u_readbuffer.*buffer_addr*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.u_readbuffer.watermark_crossed*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_cmd_info*.q*") && (ReceivingFlop =~ "*u_spi_device.u_readcmd.readbuf_addr*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_reg.u_*.*q*") && (ReceivingFlop =~ "*top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_spi_device.u_readcmd.u_*.*_q*") && (ReceivingFlop =~ "*top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_DEV_D*") && (ReceivingFlop =~ "*top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host*.q*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host*.*reg*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_xbar_main.u_asf_*.reqfifo.*q*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host0.u_spi_core.u_fsm*") && (ReceivingFlop=~"top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host1.*.q*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.mio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_host1.*.*_q*") && (ReceivingFlop =~ "*top_earlgrey.u_pinmux_aon.mio_oe_retreg_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.sram_rdata_q*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.p2s_byte_o*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.u_mem.gen_generic.u_impl_generic.b_rdata_o*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.storage*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:0]") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_en_q") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_aoff")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_sel") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.all_clks_byp_en_src")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_aoff") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.all_clks_byp_en_src")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_*_en_q") &&
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.u_clk_src*_sel.clk_ext*") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_ext_en_q")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"u_ast.u_ast_clks_byp.*_clk_byp_dgl.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "u_ast.u_ast_clks_byp.u_clk_src_*_sel.clk_*_sel")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon*_scan*") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.*_o") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[1]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.step_down_ack_o") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[0]") && (Signal =~ "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.gen_div2.step_down_nq") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o*") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o*") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.sys_status_o[23:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.watermark_crossed*") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_read_threshold.q[9:0]*") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "*.u_spi_device.u_reg*u_cmd_info*") && (MultiClockDomains =~ "IO_DIV4_CLK::*SPI_DEV*CLK*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.io_mode_outclk*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_pinmux_aon.dio_pad_attr_q*.invert")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.io_mode_outclk[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.spi_clk_csb_rst_toggle")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.sys_clk_tog")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_rptr.q[12:2]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.io_mode_outclk[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_s2p.cnt[2:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_cmdparse.st[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_cmdparse.cmd_info_q.addr_mode[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_s2p.data_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spid_addr_4b.spi_cfg_addr_4b_en_o")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_readcmd.main_st[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_readcmd.addr_cnt_q[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.u_fifo_cnt.*ptr_o[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.st_q[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.st_q[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_cmdfifo.w_wptr_q[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_normal_case.mask[2:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.addrcnt[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_addrfifo.w_wptr_q[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_wptr_gray_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.storage*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.fifo_*ptr_gray_q[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_sync_q[3:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][19:16]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_*ptr_gray_q[1:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_upload.u_*fifo.r_rptr_gray_q[4:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_addr_4b_en.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_wptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.fifo_wptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.fifo_rptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo.fifo_rptr_gray_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][15:8]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][31:24]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][23:16]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_gray_q[0]")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Signal =~ "top_earlgrey.u_spi_device.rxf_full_q")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ComponentClass =~ "FEEDBACK") && (ErrorType =~ "") && (MultiClockDomains =~ "AST_EXT_CLK,JTAG_TCK,MAIN_CLK::AST_EXT_CLK,MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_*xf_ctrl.*ptr*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_*x*.q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_alert_handler.*.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal =~ "top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_clkmgr_aon.u_clk_io_div2_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression 'Driver =~ "*u_lc_ctrl*.u_prim_lc_sender_escalate_en*"' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[124]") && (Driver =~ "top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0]")' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0]")' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(FanoutDepth =~ "1") && (Fanout =~ "top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o*") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions*.gen_buffered.u_part_buf.dout_locked_q*")' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Fanout =~ "top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Driver =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[0]")' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.num_req_outstanding[8:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_spi_core.u_fsm.speed_cpha1[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0]") && (Association =~ "None")' did not match any (non-) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.cnt[2:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_cpha.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dn_o.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[0]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dp_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1]") && (Signal =~ "top_earlgrey.u_usbdev.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.u_usb_dn_o_flop.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[1:0]") && (Signal =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_en.q[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:3]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_tx_watermark.q[0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_rxf_ptr_wptr.q[12:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.wptr[12:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_txf_ptr_rptr.q[12:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_txf_ctrl.rptr[12:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_o[2:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[5:2]") && (Signal =~ "top_earlgrey.u_spi_host0.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.mio_oe_retreg_q[46:0]") && (Signal =~ "top_earlgrey.u_spi_host1.u_reg.u_socket.dev_select_outstanding[1:0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[3:1]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0]") && (Association =~ "None")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_rxf_overflow.src_level") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.u_fifo_cnt.*ptr_o*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_p2s.out_shift[7:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_fwmode.u_rxf_ctrl.sram_wdata[31:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.storage[7:0][7:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.st_q") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.storage[1:0][23:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q[3:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_tpm_cfg_en.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (MultiClockDomains =~ "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "SPI_DEV_D0")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (MultiClockDomains =~ "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.io_mode_outclk[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_jedec.cc_count[7:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_jedec.byte_sel_q[1:0]") && (MultiClockDomains =~ "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[3:0]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][31:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_sync_q[0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[19:16]") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Driver =~ "top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.storage[1:0][31:0]")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q*") && (MultiClockDomains =~ "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Driver =~ "IOR2")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Unknown status waived. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap_q[0]") && (Signal == "IOC3") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap_q[1]") && (Signal == "IOC4") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4]") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0]") && (Signal == "IOR0") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (ReceivingFlop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.bypass_q") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.bypass_q") && (Signal == "IOR2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "u_ast.padmux2ast_i[4]") && (Signal == "IOB2") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "SPI_DEV_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (Signal =~ "SPI_DEV_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*") && (Signal =~ "SPI_HOST_D*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*") && (Signal =~ "SPI_DEV_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "SPI_HOST_*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Signal =~ "IO*") && (Association == "None")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Could not parse given expression into a valid database query. Perhaps some column headers are wrong. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cmd_info*.q*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg*.q*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_pinmux_aon.dio_pad_attr_q*.invert")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_control_mode.q*")' did not match any (non-Waived) violations for rule DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_o") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.in_o") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_sel.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "-") && (MultiClockDomains == "JTAG_TCK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "IOR3") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_mux.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_p2s.cnt[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (SampleRxSignal == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[0]") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_lc_ctrl.u_prim_clock_mux2.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o") && (MultiClockDomains == "IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o") && (SampleTxSignal == "u_ast.dft_scan_md_o[3]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_cg.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o") && (MultiClockDomains == "IO_DIV2_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_rx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_reg.u_reg_if.rdata_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_wptr_q[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[2]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_txf_underflow.src_level") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_memory_2p.b_rvalid_sram_q") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_s2p.data_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "SPI_DEV_CLK") && (MultiClockDomains == "SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK::IO_DIV4_CLK") && (SampleRxSignal == "top_earlgrey.u_pinmux_aon.dio_out_retreg_q[14]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.en_latch") && (ToClockSignal == "top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.byte_sel_q[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_p2s.cnt[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o") && (MultiClockDomains == "SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK::IO_DIV2_CLK,IO_DIV4_CLK,SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_fwmode.u_tx_fifo.fifo_rptr_gray_q[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_sram_clk_scan.gen_generic.u_impl_generic.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o") && (MultiClockDomains == "SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK::SPI_DEV_OUT_CLK,SPI_DEV_PASSTHRU_OUT_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.outclk_p2s_byte_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockDomains == "") && (FromClockSignal == "top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o") && (MultiClockDomains == "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::SPI_CSB_CLK,SPI_DEV_PASSTHRU_CSB_CLK") && (SampleRxSignal == "top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[0]") && (SampleTxSignal == "top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[0]") && (ToClockSignal == "top_earlgrey.u_spi_device.u_clk_csb_buf.clk_o")' did not match any (non-Waived) violations for rule MULTCLK_CROSSINGS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"IO*") && (ReceivingFlop=~"*u_i2c*.*.u_sync_1*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal =~ "u_ast.u_ast_clks_byp.*u_impl_generic.q_o*") && (ReconSignal=~"top_earlgrey.*.u_reg*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ControlSignal =~ "*u_pinmux_aon.u_reg.u_wkup_detector*cdc.u_src_to_dst_req*.u_sync1.*u_impl_generic.q_o*") && (ReconSignal=~"top_earlgrey.*.u_reg*")' did not match any (non-Waived) violations for rule W_RECON_GROUPS. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Driver =~ "*u_pinmux_aon.dio_pad_attr_q*")' did not match any (non-Waived) violations for rule W_FANOUT. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_HOST_*")' did not match any (non-Waived) violations for rule W_DATA. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(MultiClockDomains =~ "*::SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_HOST_*")' did not match any (non-Waived) violations for rule W_MASYNC. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"*u_pinmux_aon.dio_pad_attr_*")' did not match any (non-Waived) violations for rule W_CNTL. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockTreeSignal=~"u_ast.u_ast_clks_byp.*") && (DrivenFlop =~ "u_ast.u_ast_clks_byp.*")' did not match any (non-Waived) violations for rule S_GENCLK. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(ClockTreeSignal=~"IOC*") && (DrivenFlop =~ "u_ast.u_ast_clks_byp.*")' did not match any (non-Waived) violations for rule S_GENCLK. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"IO*") && (ReceivingFlop=~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"SPI_HOST*") && (ReceivingFlop=~ "top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.*_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
WARN [#124001] : DEBUG CLI: Expression '(Signal=~"top_earlgrey.*.u_reg.*_q*") && (ReceivingFlop=~ "top_earlgrey.u_pinmux_aon.mio_out_retreg_q*")' did not match any (non-Waived) violations for rule W_INTERFACE. Skipping...
Warning: License will expire in 26 days.
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o IO_DIV2_CLK,SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK::IO_DIV4_CLK top_earlgrey.u_spi_device.u_spid_csb_sync.csb_toggle top_earlgrey.u_spi_device.u_spid_csb_sync.u_count_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] txclockpath13.dbg,smultclkcrossings13.dbg,rxclockpath13.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o IO_DIV2_CLK,SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_csb_sync.csb_toggle top_earlgrey.u_spi_device.u_spid_csb_sync.sck_toggle txclockpath14.dbg,smultclkcrossings14.dbg,rxclockpath14.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o top_earlgrey.u_lc_ctrl.u_prim_clock_mux2.gen_generic.u_impl_generic.clk_o IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK u_ast.dft_scan_md_o[3] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[0] txclockpath15.dbg,smultclkcrossings15.dbg,rxclockpath15.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o IO_DIV4_CLK::IO_DIV2_CLK,SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spid_csb_sync.csb_toggle txclockpath16.dbg,smultclkcrossings16.dbg,rxclockpath16.dbg New New
MULTCLK_CROSSINGS: top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o top_earlgrey.u_spi_device.u_clk_csb_mux.gen_generic.u_impl_generic.clk_o SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV2_CLK,SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK top_earlgrey.u_spi_device.u_spid_csb_sync.sck_toggle top_earlgrey.u_spi_device.u_spid_csb_sync.csb_toggle txclockpath17.dbg,smultclkcrossings17.dbg,rxclockpath17.dbg New New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:155 Auto-operator New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:156 Auto-operator New
BLACK_BOX: ibex_multdiv_fast-3 (operator) ibex_multdiv_fast.sv:157 Auto-operator New
BLACK_BOX: prim_generic_ram_1p-39-32h8000-39 mem prim_generic_ram_1p.sv:48 Auto-large-array New
BLACK_BOX: otbn_mac_bignum (operator) otbn_mac_bignum.sv:103 Auto-operator New
BLACK_BOX: prim_generic_ram_1p-32h4c-32h10000-32h4c mem prim_generic_ram_1p.sv:48 Auto-large-array New
BLACK_BOX: prim_packer_fifo-36-9 (operator) prim_packer_fifo.sv:136 Auto-operator New
BLACK_BOX: prim_generic_ram_2p top_earlgrey.u_spi_device.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic prim_ram_2p.sv:48 User-defined-module New
CLK_GROUPS: RI_SYNC_GRP_1 USB_CLK 19.76 19.76 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_TPM_CLK 40 40 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_HOST_SLOW_PASS_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_SLOW_PASS_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_SLOW_PASS_CLK 40 40 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_SLOW_PASS_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_HOST_CLK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_SLOW_PASS_CSB_CLK 80 80 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_HC_CLK 40 40 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 RV_JTAG_TCK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_HC_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_DIV4_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_DIV2_CLK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 LC_JTAG_TCK 19.7904 19.7904 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_FAST_PASS_CSB_CLK 50 50 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 IO_CLK 9.8952 9.8952 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_TPM_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_HOST_FAST_PASS_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 AST_EXT_CLK 19.7904 19.7904 - - - New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_HC_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 MAIN_CLK 8.5 8.5 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_TPM_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_HC_CSB_CLK 80 80 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_CLK 20 20 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 JTAG_TCK 31.635 31.635 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 AST_EXT_CLK_gated 19.7904 19.7904 - - - New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_FAST_PASS_IN_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_FAST_PASS_OUT_CLK 39.5808 39.5808 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 SPI_DEV_FAST_PASS_CLK 25 25 - - - chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK USB_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_FAST_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_FAST_PASS_CSB_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_FAST_PASS_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_FAST_PASS_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_HC_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_HC_CSB_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_HC_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_HC_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_SLOW_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_SLOW_PASS_CSB_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_SLOW_PASS_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_DEV_SLOW_PASS_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_HOST_FAST_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_HOST_SLOW_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_TPM_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_TPM_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_TPM_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - MAIN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_FAST_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_FAST_PASS_CSB_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_FAST_PASS_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_FAST_PASS_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_HC_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_HC_CSB_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_HC_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_HC_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_SLOW_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_SLOW_PASS_CSB_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_SLOW_PASS_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_DEV_SLOW_PASS_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_HOST_FAST_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_HOST_SLOW_PASS_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_TPM_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_TPM_IN_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_TPM_OUT_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - USB_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CSB_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CSB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CSB_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CSB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CSB_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CSB_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_FAST_PASS_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_FAST_PASS_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_SLOW_PASS_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_SLOW_PASS_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK IO_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK SPI_HOST_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CSB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CSB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CSB_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_FAST_PASS_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_SLOW_PASS_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CSB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CSB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CSB_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_FAST_PASS_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_SLOW_PASS_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CSB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CSB_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_CSB_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_IN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_IN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_OUT_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_FAST_PASS_OUT_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CSB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CSB_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_CSB_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_IN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_IN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_OUT_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_HC_OUT_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CSB_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CSB_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_CSB_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_IN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_IN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_OUT_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_DEV_SLOW_PASS_OUT_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_FAST_PASS_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_FAST_PASS_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_FAST_PASS_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_SLOW_PASS_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_SLOW_PASS_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_SLOW_PASS_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_IN_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_TPM_OUT_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK IO_DIV2_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - SPI_HOST_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK IO_DIV4_CLK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV2_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV4_CLK JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV4_CLK LC_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_SYNC_GRP_1 - IO_DIV4_CLK RV_JTAG_TCK Async chip_earlgrey_asic.sdc:1029 New New
CLK_GROUPS: RI_WAVEFORM_ASYNC_0 RI_WAVEFORM_ASYNC_0 8.5 8.5 - - - New New
CLK_GROUPS: RI_WAVEFORM_ASYNC_1 RI_WAVEFORM_ASYNC_1 8.5 8.5 - - - New New
S_MISSING_SPEC: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV4_CLK AST_EXT_CLK constraints.sdc.env:179 prim_clock_div-32h4 New
S_MISSING_SPEC: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV2_CLK AST_EXT_CLK constraints.sdc.env:175 prim_clock_div New
S_MISSING_SPEC: top_earlgrey.u_spi_device.u_clk_spi_in_buf.clk_o prim_clock_buf.sv:49 IO_DIV2_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK create_clock waveform=SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK IO_DIV2_CLK constraints.sdc.env:191,constraints.sdc.env:199,constraints.sdc.env:207,constraints.sdc.env:227 prim_clock_buf-1=1h1 New
S_MISSING_SPEC: top_earlgrey.u_spi_device.u_clk_spi_out_buf.clk_o prim_clock_buf.sv:49 IO_DIV2_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK create_clock waveform=SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK IO_DIV2_CLK constraints.sdc.env:195,constraints.sdc.env:203,constraints.sdc.env:211,constraints.sdc.env:231 prim_clock_buf-1=1h1 New
S_CONF_ENV: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV4_CLK AST_EXT_CLK,IO_CLK IO_DIV4_CLK constraints.sdc.env:179 PostResetPhase prim_clock_div-32h4 New
S_CONF_ENV: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.clk_o prim_clock_div.sv:42 AST_EXT_CLK,IO_CLK create_clock waveform=IO_DIV2_CLK AST_EXT_CLK,IO_CLK IO_DIV2_CLK constraints.sdc.env:175 PostResetPhase,sconfenv19.dbg prim_clock_div New
S_INPUT_NO_WAVE: SPI_HOST_CS_L top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup.u_prim_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK_gated prim_generic_flop.sv:21 sinputnowave24.dbg New Flat-to-Flat
W_REDUNDANT_SYNC: IOR8 IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_prim_flop_2sync_input.u_sync_1.gen_generic.u_impl_generic.q_o[1] 2 top_earlgrey.u_sysrst_ctrl_aon.u_prim_flop_2sync_input.u_sync_2.gen_generic.u_impl_generic.q_o[1] chip_earlgrey_asic New
W_REDUNDANT_SYNC: IOR9 IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_prim_flop_2sync_input.u_sync_1.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey.u_sysrst_ctrl_aon.u_prim_flop_2sync_input.u_sync_2.gen_generic.u_impl_generic.q_o[0] chip_earlgrey_asic New
W_REDUNDANT_SYNC: IOA0 IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_sysrst_ctrl_aon.u_prim_flop_2sync_input.u_sync_1.gen_generic.u_impl_generic.q_o[7:2] 2 top_earlgrey.u_sysrst_ctrl_aon.u_prim_flop_2sync_input.u_sync_2.gen_generic.u_impl_generic.q_o[7:2] chip_earlgrey_asic New
W_REDUNDANT_SYNC: IOA0 IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_sense.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] chip_earlgrey_asic New
W_REDUNDANT_SYNC: IOB2 IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV2_CLK,IO_DIV4_CLK prim_generic_flop.sv:21 top_earlgrey.u_pwrmgr_aon.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] 2 top_earlgrey.u_pwrmgr_aon.u_cdc.u_ast_sync.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] chip_earlgrey_asic New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[2] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rv_dm-1=32h10001cdf New
RST_SYNC: top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rv_dm-1=32h10001cdf New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:2] spid_status.sv:183 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:2] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_passthrough.opcode[6] spi_passthrough.sv:336 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_passthrough.opcode[7] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:58 PDT
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_read_pipe_stg1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK top_earlgrey.u_spi_device.u_read_pipe_stg2.gen_generic.u_impl_generic.q_o[3:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_read_en_pipe_stg1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK top_earlgrey.u_spi_device.u_read_en_pipe_stg2.gen_generic.u_impl_generic.q_o[3:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_read_intercept_pipe_stg1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK top_earlgrey.u_spi_device.u_read_intercept_pipe_stg2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic.q_o[3:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_oe_stg1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_oe_stg2.gen_generic.u_impl_generic.q_o[3:0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_daon_sys_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_daon_sys_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_daon_sys_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_daon_sys_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_lc_src.u_aon_rst.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc_usb.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,USB_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_usb.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rstmgr New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_lc_src.u_aon_rst.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rstmgr New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_lc_src.u_aon_rst.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rstmgr New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_lc_src.u_aon_rst.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc_io_div2.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::IO_DIV2_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_io_div2.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rstmgr New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_lc_src.u_aon_rst.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc_io.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,IO_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_io.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rstmgr New
RST_SYNC: top_earlgrey.u_rstmgr_aon.u_sys_src.gen_rst_pd_n[0].u_pd_rst.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 rstmgr New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:2] spid_status.sv:183 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:2] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_passthrough.opcode[6] spi_passthrough.sv:336 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_passthrough.opcode[7] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_intr_prog_empty.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[156] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_intr_prog_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[157] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_intr_rd_full.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[158] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_intr_rd_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[159] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[160] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_intr_corr_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[161] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[169] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[170] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_entropy_req.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[171] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_hw_inst_exc.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[172] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[173] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_entropy_valid.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[174] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_health_test_failed.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[175] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_observe_fifo_ready.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[176] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[177] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[178] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[179] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[180] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[181] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[155:1] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[155:1] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[168:162] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[168:162] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.u_lc_escalate_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_lc_escalate_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.u_lc_rma_req_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_lc_rma_req_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.u_otbn_scramble_ctrl.u_otp_key_req_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_otbn_scramble_ctrl.u_otp_key_req_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.lookup_index_ic1[7:0] ibex_icache.sv:473 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.ecc_correction_index_q[7:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_prim_rst_shadow_set_flop.gen_generic.u_impl_generic.q_o[3:1] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_prim_enable_cmp_flop.gen_generic.u_impl_generic.q_o[3:1] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_shadow_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.lookup_index_ic1[7:0] ibex_icache.sv:473 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_shadow_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.ecc_correction_index_q[7:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].fetch_enable[3:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].fetch_enable[3:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].rf_rdata_b_ecc[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].rf_rdata_b_ecc[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].rf_rdata_a_ecc[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].rf_rdata_a_ecc[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_rdata[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_rdata[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_rdata[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_rdata[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_tag_rdata_q[1][1:0][27:0] ibex_lockstep.sv:250 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_tag_rdata_q[0][1:0][27:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_data_rdata_q[1][1:0][77:0] ibex_lockstep.sv:251 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_data_rdata_q[0][1:0][77:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_41.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_41.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].ic_scr_key_valid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].ic_scr_key_valid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].debug_req ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].debug_req 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_nm ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_nm 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_external ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_external 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_timer ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_timer 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_software ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_software 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_err ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_err 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_rvalid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_rvalid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_gnt ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_gnt 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_err ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_err 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_rvalid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_rvalid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_gnt ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_gnt 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[0] top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:2] spid_status.sv:183 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:2] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_passthrough.opcode[6] spi_passthrough.sv:336 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_passthrough.opcode[7] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_intr_prog_empty.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[156] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_intr_prog_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[157] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_intr_rd_full.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[158] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_intr_rd_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[159] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[160] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_intr_corr_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[161] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[169] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[170] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_entropy_req.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[171] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_hw_inst_exc.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[172] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[173] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_entropy_valid.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[174] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_health_test_failed.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[175] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_observe_fifo_ready.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[176] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[177] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[178] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[179] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[180] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[181] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[155:1] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[155:1] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[168:162] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[168:162] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.u_lc_escalate_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_lc_escalate_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.u_lc_rma_req_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_lc_rma_req_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.u_otbn_scramble_ctrl.u_otp_key_req_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_otbn_scramble_ctrl.u_otp_key_req_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.lookup_index_ic1[7:0] ibex_icache.sv:473 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.ecc_correction_index_q[7:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_prim_rst_shadow_set_flop.gen_generic.u_impl_generic.q_o[3:1] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_prim_enable_cmp_flop.gen_generic.u_impl_generic.q_o[3:1] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_shadow_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.lookup_index_ic1[7:0] ibex_icache.sv:473 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_shadow_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.ecc_correction_index_q[7:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].fetch_enable[3:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].fetch_enable[3:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].rf_rdata_b_ecc[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].rf_rdata_b_ecc[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].rf_rdata_a_ecc[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].rf_rdata_a_ecc[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_rdata[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_rdata[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_rdata[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_rdata[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_tag_rdata_q[1][1:0][27:0] ibex_lockstep.sv:250 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_tag_rdata_q[0][1:0][27:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_data_rdata_q[1][1:0][77:0] ibex_lockstep.sv:251 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_data_rdata_q[0][1:0][77:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_41.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_41.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].ic_scr_key_valid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].ic_scr_key_valid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].debug_req ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].debug_req 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_nm ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_nm 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_external ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_external 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_timer ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_timer 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_software ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_software 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_err ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_err 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_rvalid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_rvalid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_gnt ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_gnt 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_err ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_err 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_rvalid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_rvalid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_gnt ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_gnt 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[1] top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:2] spid_status.sv:183 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:2] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_passthrough.opcode[6] spi_passthrough.sv:336 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_passthrough.opcode[7] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_intr_prog_empty.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[156] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_intr_prog_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[157] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_intr_rd_full.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[158] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_intr_rd_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[159] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[160] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_intr_corr_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[161] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[169] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[170] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_entropy_req.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[171] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_hw_inst_exc.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[172] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[173] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_entropy_valid.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[174] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_health_test_failed.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[175] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_observe_fifo_ready.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[176] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[177] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[178] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[179] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[180] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[181] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[155:1] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[155:1] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[168:162] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[168:162] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_hmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.u_lc_escalate_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_lc_escalate_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.u_lc_rma_req_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_lc_rma_req_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.u_otbn_scramble_ctrl.u_otp_key_req_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_otbn_scramble_ctrl.u_otp_key_req_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_rnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otbn.u_prim_edn_urnd_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_lc_keymgr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_ctrl.u_key_valid_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_fault_alert.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_op_err_alert.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_csrng.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_over.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.u_entropy_src_core.u_prim_mubi8_sync_es_fw_read.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_entropy_src.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn0.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_edn1.gen_alert_tx[1].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_alert_sender_parity.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_wdog_nmi_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.lookup_index_ic1[7:0] ibex_icache.sv:473 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.u_ibex_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.ecc_correction_index_q[7:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_prim_rst_shadow_set_flop.gen_generic.u_impl_generic.q_o[3:1] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_prim_enable_cmp_flop.gen_generic.u_impl_generic.q_o[3:1] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_shadow_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.lookup_index_ic1[7:0] ibex_icache.sv:473 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.u_shadow_core.if_stage_i.gen_icache.icache_i.gen_data_ecc_checking.ecc_correction_index_q[7:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].fetch_enable[3:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].fetch_enable[3:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].rf_rdata_b_ecc[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].rf_rdata_b_ecc[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].rf_rdata_a_ecc[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].rf_rdata_a_ecc[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_rdata[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_rdata[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_rdata[38:0] ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_rdata[38:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_tag_rdata_q[1][1:0][27:0] ibex_lockstep.sv:250 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_tag_rdata_q[0][1:0][27:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_data_rdata_q[1][1:0][77:0] ibex_lockstep.sv:251 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_data_rdata_q[0][1:0][77:0] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_37.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_37.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_37.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_39.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_39.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_39.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_41.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_41.reqfifo.fifo_rptr_sync_q[0] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_xbar_main.u_asf_41.rspfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_aes.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_kmac.gen_entropy.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_keymgr.u_reseed_ctrl.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].ic_scr_key_valid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].ic_scr_key_valid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].debug_req ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].debug_req 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_nm ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_nm 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_external ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_external 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_timer ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_timer 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].irq_software ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].irq_software 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_err ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_err 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_rvalid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_rvalid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].data_gnt ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].data_gnt 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_err ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_err 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_rvalid ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_rvalid 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[1].instr_gnt ibex_lockstep.sv:249 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_core.gen_lockstep.u_ibex_lockstep.shadow_inputs_q[0].instr_gnt 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.src_req_q prim_sync_reqack.sv:309 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[2] top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.dst_ack_q prim_sync_reqack.sv:318 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 3 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spid_status.sck_status_staged[23:2] spid_status.sv:183 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:2] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic.q_o[4:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_passthrough.opcode[6] spi_passthrough.sv:336 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_passthrough.opcode[7] 2 chip_earlgrey_asic New
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[1:0] prim_generic_flop.sv:19 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic.q_o[1:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_otp_ctrl.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_lc_ctrl.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_alert_handler.u_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_por.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.u_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rstmgr_aon.u_d0_sys.gen_rst_chk.u_rst_chk.u_child_handshake.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_flash_init.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_addr_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_flash_hw_if.u_data_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[0].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[1].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[2].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[3].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.gen_alert_senders[4].u_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_intr_prog_empty.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[156] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_intr_prog_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[157] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_intr_rd_full.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[158] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_intr_rd_lvl.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[159] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[160] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_intr_corr_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[161] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_flash_ctrl.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[7:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_assert.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.u_prim_flop_2sync_lc_rst_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_keymgr.u_intr_op_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[169] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[170] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_entropy_req.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[171] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_hw_inst_exc.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[172] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_csrng.u_csrng_core.u_intr_hw_cs_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[173] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_entropy_valid.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[174] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_health_test_failed.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[175] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_observe_fifo_ready.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[176] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_entropy_src.u_entropy_src_core.u_intr_hw_es_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[177] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[178] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_edn0.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[179] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_cmd_req_done.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[180] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_edn1.u_edn_core.u_intr_hw_edn_fatal_err.intr_o[0] prim_intr_hw.sv:96 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[181] 3 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[155:1] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[155:1] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[168:162] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[168:162] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_p.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
RST_SYNC: u_ast.dft_scan_md_o[3] top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] prim_generic_flop.sv:19 IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender.u_decode_ack.gen_async.i_sync_n.u_sync_2.gen_generic.u_impl_generic.q_o[0] 2 chip_earlgrey_asic Waived Reviewed : reset source to reset synchronizer; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:57 PDT
Note: 32015 more messages have been suppressed (max_msg_count = 1000)
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[38].input_disable IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.lc_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:323 Non-Clock,wgclkglitch115134.dbg chip_earlgrey_asic New
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[38].invert IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.lc_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:323 Non-Clock,wgclkglitch115135.dbg chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.lc_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:323 Non-Clock,wgclkglitch115136.dbg chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.lc_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:323 Non-Clock,wgclkglitch115138.dbg chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.lc_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:323 Non-Clock chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[38].input_disable IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.rv_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:329 Non-Clock,wgclkglitch115140.dbg chip_earlgrey_asic New
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[38].invert IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.rv_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:329 Non-Clock,wgclkglitch115141.dbg chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.rv_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:329 Non-Clock,wgclkglitch115142.dbg chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.rv_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:329 Non-Clock,wgclkglitch115144.dbg chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] IO_DIV4_CLK top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.rv_jtag_req.tck JTAG_TCK ASYNC_INPUT pinmux_strap_sampling.sv:329 Non-Clock chip_earlgrey_asic Waived W_G_CLK_GLITCH issues in JTAG; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:22 PDT
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[12].input_disable IO_DIV4_CLK u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.in_raw_o SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK ASYNC_INPUT prim_generic_pad_wrapper.sv:64 top_earlgrey.u_spi_device.u_passthrough.u_pt_sck_cg.gen_generic.u_impl_generic.clk_o Non-Clock,wgclkglitch115222.dbg chip_earlgrey_asic New
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[13].input_disable IO_DIV4_CLK u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.in_raw_o SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK ASYNC_INPUT prim_generic_pad_wrapper.sv:64 top_earlgrey.u_spi_device.u_csb_buf.in_i[0] Non-Clock,wgclkglitch115225.dbg chip_earlgrey_asic New
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[38].input_disable IO_DIV4_CLK u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_raw_o JTAG_TCK ASYNC_INPUT prim_generic_pad_wrapper.sv:78 top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.in_core_o[38] Non-Clock,wgclkglitch115232.dbg chip_earlgrey_asic New
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] IO_DIV4_CLK u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_raw_o JTAG_TCK ASYNC_INPUT prim_generic_pad_wrapper.sv:78 top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.in_core_o[38] Non-Clock,wgclkglitch115233.dbg chip_earlgrey_asic New
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] IO_DIV4_CLK u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_raw_o JTAG_TCK ASYNC_INPUT prim_generic_pad_wrapper.sv:78 top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.in_core_o[38] Non-Clock,wgclkglitch115235.dbg chip_earlgrey_asic New
W_G_CLK_GLITCH: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] IO_DIV4_CLK u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.in_raw_o JTAG_TCK ASYNC_INPUT prim_generic_pad_wrapper.sv:78 top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.in_core_o[38] Non-Clock chip_earlgrey_asic New
W_RECON_GROUPS: top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q[0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceReconButGlobalCntlDrivers,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.sck_st_d[0] spi_tpm.sv:1097 1 New New
W_RECON_GROUPS: top_earlgrey.u_spi_device.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q[0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceReconButGlobalCntlDrivers,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.sck_st_d[0] spi_tpm.sv:1097 2 New Waived reconvergence caused by unrecognized qualification in async fifo; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:05 PDT
W_RECON_GROUPS: top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceReconButGlobalCntlDrivers,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.sck_st_d[0] spi_tpm.sv:1097 3 New Waived reconvergence caused by unrecognized qualification in async fifo; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:05 PDT
W_RECON_GROUPS: top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceReconButGlobalCntlDrivers,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.u_spi_tpm.sck_st_d[0] spi_tpm.sv:1097 3 New Waived reconvergence caused by unrecognized qualification in async fifo; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:04 PDT
W_RECON_GROUPS: top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4] top_earlgrey.u_spi_device.u_spid_dpram.gen_ram2p.u_memory_2p.b_rvalid_sram_q IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceRecon,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.mem_b_l2m.req prim_ram_2p_async_adv.sv:146 1 New Waived reconvergence caused by unrecognized qualification in async fifo; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:05 PDT
W_RECON_GROUPS: top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4] top_earlgrey.u_spi_device.u_spid_dpram.gen_ram2p.u_memory_2p.b_rvalid_sram_q IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceRecon,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.mem_b_l2m.req prim_ram_2p_async_adv.sv:146 1 New Waived reconvergence caused by unrecognized qualification in async fifo; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:05 PDT
W_RECON_GROUPS: top_earlgrey.u_spi_device.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_dpram.gen_ram2p.u_memory_2p.b_rvalid_sram_q IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceRecon,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.mem_b_l2m.req prim_ram_2p_async_adv.sv:146 1 New New
W_RECON_GROUPS: top_earlgrey.u_clkmgr_aon.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_dpram.gen_ram2p.u_memory_2p.b_rvalid_sram_q IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceRecon,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.mem_b_l2m.req prim_ram_2p_async_adv.sv:146 3 New Waived reconvergence caused by unrecognized qualification in async fifo; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:05 PDT
W_RECON_GROUPS: top_earlgrey.u_xbar_main.u_asf_35.rspfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_spi_device.u_spid_dpram.gen_ram2p.u_memory_2p.b_rvalid_sram_q IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK Flat-To-Flat DATA_RECON_POINT,InterfaceRecon,SubsetDrivers top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 prim_generic_flop.sv:21 top_earlgrey.u_spi_device.mem_b_l2m.req prim_ram_2p_async_adv.sv:146 3 New Waived reconvergence caused by unrecognized qualification in async fifo; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:04 PDT
W_FANOUT: top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[120] top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_FANOUT: top_earlgrey.u_rv_core_ibex.u_intr_timer_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_rv_timer.gen_harts[0].u_intr_hw.intr_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived Independent fanout in different clock domains; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:28 PDT
W_FANOUT: top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.dout_locked_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_FANOUT: top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.dout_locked_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_FANOUT: top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.dout_locked_q[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_FANOUT: top_earlgrey.u_rv_dm.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_FANOUT: top_earlgrey.u_csrng.u_csrng_core.u_prim_lc_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_FANOUT: top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_lc_ctrl.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 1 top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108002.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:13 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9:6].invert top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108003.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9:6].input_disable top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108004.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108005.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_valid_0.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108006.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_opcode_0.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108007.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_valid_1.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108008.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_opcode_1.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108009.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_valid_2.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108010.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_opcode_2.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108011.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_valid_3.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108012.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_opcode_3.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108013.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_valid_4.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108014.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_opcode_4.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108015.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_valid_5.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108016.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_opcode_5.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108017.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_valid_6.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108018.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_opcode_6.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108019.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_valid_7.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108020.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_opcode_7.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108021.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_valid_8.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108022.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_opcode_8.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108023.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_valid_9.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108024.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_opcode_9.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108025.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_valid_10.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108026.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_opcode_10.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108027.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_valid_11.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108028.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_opcode_11.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108029.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_valid_12.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108030.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_opcode_12.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108031.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_valid_13.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108032.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_opcode_13.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108033.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_valid_14.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108034.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_opcode_14.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108035.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_valid_15.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108036.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_opcode_15.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108037.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_valid_16.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108038.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_opcode_16.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108039.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_valid_17.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108040.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_opcode_17.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108041.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_valid_18.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108042.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_opcode_18.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108043.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_valid_19.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108044.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_opcode_19.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108045.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_valid_20.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108046.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_opcode_20.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108047.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_valid_21.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108048.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_opcode_21.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108049.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_valid_22.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108050.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_opcode_22.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108051.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_valid_23.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108052.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_opcode_23.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108053.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_valid.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108054.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108055.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_valid.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108056.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108057.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_valid.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108058.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_opcode.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108059.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_valid.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108060.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_opcode.q[7:0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108061.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_upload_0.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108062.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_upload_1.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108063.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_upload_2.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108064.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_upload_3.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface108001.dbg,winterface108065.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_upload_4.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109002.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_upload_5.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109003.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_upload_6.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109004.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_upload_7.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109005.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_upload_8.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109006.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_upload_9.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109007.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_upload_10.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109008.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_upload_11.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109009.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_upload_12.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109010.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_upload_13.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109011.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_upload_14.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109012.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_upload_15.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109013.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_upload_16.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109014.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_upload_17.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109015.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_upload_18.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109016.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_upload_19.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109017.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_upload_20.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109018.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_upload_21.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109019.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_upload_22.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109020.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_upload_23.q[0] top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109021.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.csb_toggle top_earlgrey.u_spi_device.u_upload.u_sys_cmdfifo_set.sck_toggle IO_DIV2_CLK,SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_csb_sync.sv:36 Load-Cntl,winterface109001.dbg,winterface109022.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_INTERFACE: CNTL top_earlgrey.u_spi_device.u_upload.u_cmdfifo.r_rptr_gray_q[4:0] top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 Depth=1,winterface109023.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: CNTL top_earlgrey.u_spi_device.u_upload.u_addrfifo.r_rptr_gray_q[4:0] top_earlgrey.u_spi_device.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic.q_o[4:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 Depth=1,winterface109024.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109026.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109027.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109028.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109029.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109030.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109031.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.data_q[1:0] top_earlgrey.u_rv_dm.dap.dr_q[40] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109032.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR2 top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 Load-Cntl,winterface109025.dbg,winterface109033.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: CNTL top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK prim_generic_flop.sv:21 Depth=1,winterface109034.dbg chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.csb_q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109036.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.wptr_wrap_cnt_q[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109037.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.u_fifo_cnt.rptr_wrap_cnt_q[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109038.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.under_rst top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109039.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_control_sw_rst.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109040.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_control_spien.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109041.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_cmdbusy.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109042.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_overflow.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109043.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_underflow.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109044.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_cmdinval.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109045.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_csidinval.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109046.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_reg.u_error_status_accessinval.q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109047.dbg chip_earlgrey_asic New Waived W_INTERFACE issues from u_reg to pinmux; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:11 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.clk_cntr_q[15:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109048.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.state_q[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109049.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.bit_cntr_q[2:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109050.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.byte_cntr_cpha0_q[8:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109051.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.csaat_q top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109052.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.wait_cntr_q[3:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109053.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.cmd_speed_q[1:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109054.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.speed_cpha1[1:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109055.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_shift_reg.sr_q[7:4] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109056.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.u_sck_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109057.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA u_ast.ast2padmux_o[4:0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109058.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][45] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109059.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.csid_q[0] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface109035.dbg,winterface109060.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_cmd_queue.cmd_fifo.gen_normal_fifo.storage[3:0][1] top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110002.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC top_earlgrey.u_spi_host1.u_spi_core.u_fsm.cpha_q top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110003.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110004.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110005.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110006.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110007.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110008.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110009.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA6 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110010.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110011.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOA8 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110012.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110013.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110014.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110015.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110016.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110017.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110018.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB6 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110019.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110020.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB8 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110021.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB9 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110022.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB10 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110023.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB11 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110024.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB12 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110025.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110026.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110027.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110028.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110029.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110030.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110031.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110032.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC8 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110033.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC9 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110034.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC10 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110035.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC11 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110036.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC12 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110037.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR0 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110038.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR1 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110039.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR2 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110040.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR3 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] JTAG_TCK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110041.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR4 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110042.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR5 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110043.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR6 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110044.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR7 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110045.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR10 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110046.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR11 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110047.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR12 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110048.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOR13 top_earlgrey.u_pinmux_aon.mio_out_retreg_q[46:0] IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK pinmux.sv:435 Fifo-Cntl,winterface110001.dbg,winterface110049.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: CNTL top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_wptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,MAIN_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2,winterface110050.dbg chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.src_level top_earlgrey.u_clkmgr_aon.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_aes_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_hmac_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:26 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_kmac_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:26 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_otbn_hint.q[0] top_earlgrey.u_clkmgr_aon.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:26 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[0][23:16] top_earlgrey.u_rv_dm.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_i2c0.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[83] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_i2c1.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[98] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_i2c2.i2c_core.intr_hw_tx_stretch.intr_o[0] top_earlgrey.u_rv_plic.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[113] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[0][15:8] top_earlgrey.u_csrng.u_csrng_core.u_prim_mubi8_sync_sw_app_read.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.dout_locked_q[7:0] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_otp_ctrl.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[0][7:0] top_earlgrey.u_sram_ctrl_main.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[7:0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_classes[3:0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[9:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_classes[3:0].u_accu.u_prim_count.gen_cnts[1:0].u_cnt_flop.gen_generic.u_impl_generic.q_o[15:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_classes[3:0].u_esc_timer.u_prim_count.gen_cnts[1:0].u_cnt_flop.gen_generic.u_impl_generic.q_o[31:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_ping_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o[8:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_ping_timer.u_prim_count_esc_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic.q_o[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0.committed_reg.q[0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0.committed_reg.q[1:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.esc_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_alert_handler.gen_esc_sev[0].u_esc_sender.ping_req_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_decode_esc.level_q top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.state_q[2:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver.u_prim_count.gen_cnts[1:0].u_cnt_flop.gen_generic.u_impl_generic.q_o[21:0] top_earlgrey.u_rv_core_ibex.u_alert_nmi_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_gray_q[0] top_earlgrey.u_xbar_main.u_asf_35.reqfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:25 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3:2].input_disable top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111017.dbg,winterface111018.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3:2].invert top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111017.dbg,winterface111019.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D0 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[0] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111017.dbg,winterface111020.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D1 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[1:0] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111017.dbg,winterface111021.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5:3].input_disable top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[3:1] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111022.dbg,winterface111023.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5:3].invert top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[3:1] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111022.dbg,winterface111024.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D2 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[2] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111025.dbg,winterface111026.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D3 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.rx_buf_q[3] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:109 Load-Cntl,winterface111027.dbg,winterface111028.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: CNTL top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 Depth=1,winterface111029.dbg chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: CNTL top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_io_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 Depth=1,winterface111030.dbg chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_alert_handler.gen_alerts[19].u_alert_receiver.u_decode_alert.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_alert_handler.gen_alerts[19].u_alert_receiver.u_decode_alert.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=1 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5:2].input_disable top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sd_i_q[3:0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:106 Load-Cntl,winterface111031.dbg,winterface111032.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5:2].invert top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sd_i_q[3:0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:106 Load-Cntl,winterface111031.dbg,winterface111033.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D0 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sd_i_q[0] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:106 Load-Cntl,winterface112001.dbg,winterface112002.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D1 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sd_i_q[1] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:106 Load-Cntl,winterface112003.dbg,winterface112004.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D2 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sd_i_q[2] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:106 Load-Cntl,winterface112005.dbg,winterface112006.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D3 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sd_i_q[3] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:106 Load-Cntl,winterface112007.dbg,winterface112008.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: CNTL top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 Depth=1,winterface112009.dbg chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: CNTL top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_io_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 Depth=1,winterface112010.dbg chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_alert_handler.gen_alerts[19].u_alert_receiver.u_decode_alert.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_alert_handler.gen_alerts[19].u_alert_receiver.u_decode_alert.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=1 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3:2].input_disable top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112011.dbg,winterface112012.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[3:2].invert top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112011.dbg,winterface112013.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D0 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[0] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112011.dbg,winterface112014.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D1 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[1:0] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112011.dbg,winterface112015.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5:3].input_disable top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[3:1] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112016.dbg,winterface112017.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.dio_pad_attr_q[5:3].invert top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[3:1] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112016.dbg,winterface112018.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D2 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[2] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112019.dbg,winterface112020.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC SPI_HOST_D3 top_earlgrey.u_spi_host0.u_spi_core.u_shift_reg.sr_q[3] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::AST_EXT_CLK,IO_CLK spi_host_shift_register.sv:107 Load-Cntl,winterface112021.dbg,winterface112022.dbg chip_earlgrey_asic New Waived waiving W_INTERFACE issues from PAD; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:24 PDT
W_INTERFACE: CNTL top_earlgrey.u_pwrmgr_aon.u_fsm.ip_clk_en_q top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 Depth=1,winterface112009.dbg chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: CNTL top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_io_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_io_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,IO_CLK prim_generic_flop.sv:21 Depth=1,winterface112010.dbg chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_alert_handler.gen_alerts[19].u_alert_receiver.u_decode_alert.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_spi_host0.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_alert_handler.gen_alerts[19].u_alert_receiver.u_decode_alert.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=1 chip_earlgrey_asic New Waived Handled by CDC handshaking. included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:27 PDT
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].input_disable u_ast.padmux2ast_i[4] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK chip_earlgrey_asic.sv:861 Load-Cntl,winterface115042.dbg,winterface115043.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOB2 u_ast.padmux2ast_i[4] IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,USB_CLK chip_earlgrey_asic.sv:861 Load-Cntl,winterface115042.dbg,winterface115044.dbg chip_earlgrey_asic New New
W_INTERFACE: CNTL top_earlgrey.u_pwrmgr_aon.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_usb_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 Depth=1,winterface115045.dbg chip_earlgrey_asic New New
W_INTERFACE: CNTL top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_usb_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_usb_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 Depth=1,winterface115046.dbg chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_usb_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_usbdev.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_alert_handler.gen_alerts[21].u_alert_receiver.u_decode_alert.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_usbdev.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_alert_handler.gen_alerts[21].u_alert_receiver.u_decode_alert.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_usb_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_usb_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=1 chip_earlgrey_asic New New
W_INTERFACE: DATA top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].input_disable u_ast.padmux2ast_i[7] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK chip_earlgrey_asic.sv:861 Load-Cntl,winterface115047.dbg,winterface115048.dbg chip_earlgrey_asic New New
W_INTERFACE: DATA Uncontrolled-Tx-MASYNC IOC3 u_ast.padmux2ast_i[7] IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,USB_CLK chip_earlgrey_asic.sv:861 Load-Cntl,winterface115047.dbg,winterface115049.dbg chip_earlgrey_asic New New
W_INTERFACE: CNTL top_earlgrey.u_pwrmgr_aon.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_usb_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 Depth=1,winterface115045.dbg chip_earlgrey_asic New New
W_INTERFACE: CNTL top_earlgrey.u_clkmgr_aon.u_reg.u_clk_enables_clk_usb_peri_en.q[0] top_earlgrey.u_clkmgr_aon.u_clk_usb_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] IO_DIV4_CLK::AST_EXT_CLK,USB_CLK prim_generic_flop.sv:21 Depth=1,winterface115046.dbg chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_prim_mubi4_sender_clk_usb_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_alert_handler.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[3:0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_usbdev.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_alert_handler.gen_alerts[21].u_alert_receiver.u_decode_alert.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_usbdev.gen_alert_tx[0].u_prim_alert_sender.u_prim_flop_alert.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[1] top_earlgrey.u_alert_handler.gen_alerts[21].u_alert_receiver.u_decode_alert.gen_async.i_sync_n.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=2 chip_earlgrey_asic New New
W_INTERFACE: FEEDBACK top_earlgrey.u_clkmgr_aon.u_usb_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic.q_o[0] top_earlgrey.u_clkmgr_aon.u_usb_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,USB_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 Depth=1 chip_earlgrey_asic New New
W_ASYNC_RST_FLOPS: top_earlgrey.u_spi_device.u_spid_status.status_fifo_clr_n top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.fifo_rptr_gray_q[1:0] prim_fifo_async.sv:102 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_status New New AsyncPathDriver,warf68537.dbg
W_ASYNC_RST_FLOPS: top_earlgrey.u_spi_device.u_spid_status.status_fifo_clr_n top_earlgrey.u_spi_device.u_spid_status.u_sw_status_update_sync.fifo_rptr_q[1:0] prim_fifo_async.sv:93 IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_status New New AsyncPathDriver,warf68538.dbg
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data97855.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_valid_15.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_valid_5.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_valid_2.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_valid_1.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_valid_7.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_valid_3.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_valid_21.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_valid_4.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_valid_6.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_valid_8.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_valid_9.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_valid_0.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_opcode_5.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_valid_17.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_valid_19.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_valid_13.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_valid_11.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_valid_14.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_opcode_9.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_valid_20.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_valid_18.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_valid_16.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_valid_10.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_valid_23.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_valid_22.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_valid_12.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_opcode_12.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_opcode_16.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_opcode_19.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_opcode_14.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_opcode_22.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_opcode_13.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_opcode_20.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_opcode_21.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_opcode_11.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_opcode_18.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_opcode_23.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:17 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_cc_cc.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:13 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_opcode_15.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_opcode_10.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_opcode_17.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].invert top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].invert top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].invert top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_opcode_8.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_opcode_4.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_opcode_7.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_opcode_3.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_opcode_2.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_opcode_6.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_opcode_0.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_opcode_1.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_valid_2.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data97856.dbg spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_opcode_15.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_valid_19.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_valid_13.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_valid_22.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_valid_16.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_valid_4.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_valid_8.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_valid_6.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_valid_5.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_valid_3.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_opcode_11.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_valid_1.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_valid_0.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_valid_9.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:17 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_id_id.q[15:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_opcode_19.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_opcode_22.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_opcode_23.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_valid_7.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_opcode_21.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_opcode_20.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_opcode_13.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_opcode_14.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_opcode_16.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_opcode_17.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_opcode_10.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_opcode_18.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_opcode_12.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_valid_14.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_opcode_5.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_opcode_1.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_opcode_7.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_opcode_8.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_opcode_6.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_opcode_3.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_opcode_9.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_opcode_4.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_opcode_0.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].invert top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].invert top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].invert top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:13 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_valid_10.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_valid_23.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_valid_20.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_valid_17.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_opcode_2.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_valid_18.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_valid_21.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_valid_12.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_valid_11.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_valid_15.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.device_id[15:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_opcode_18.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data97857.dbg spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_opcode_13.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_opcode_12.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_opcode_16.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_opcode_15.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_opcode_0.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_opcode_7.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_opcode_10.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_opcode_14.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_opcode_11.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].invert top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].invert top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].invert top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_valid_23.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:13 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_opcode_5.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_opcode_2.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_opcode_9.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_opcode_1.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_valid_9.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_valid_0.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_opcode_4.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_opcode_6.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_opcode_8.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_opcode_3.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_valid_16.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_valid_17.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_valid_15.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_valid_21.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_valid_20.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_valid_19.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_valid_18.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_valid_10.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_valid_4.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_opcode_23.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_opcode_22.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_opcode_17.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_opcode_19.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_opcode_20.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_valid_7.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_valid_6.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_valid_5.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_opcode_21.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_valid_3.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_valid_1.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_valid_2.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_valid_8.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:17 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_valid_22.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_id_mf.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_valid_12.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_valid_13.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_valid_14.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_valid_11.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.jedec_id[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat data97858.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_opcode_11.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_valid_10.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_rx_order.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:17 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_valid_5.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_valid_3.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_opcode_19.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_valid_9.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_valid_4.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_valid_0.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_valid_8.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_valid_7.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_valid_6.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_valid_1.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_valid_2.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].input_disable top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_opcode_13.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_opcode_12.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_10_opcode_10.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[8].invert top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_opcode_23.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_opcode_21.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_opcode_16.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:13 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_valid_14.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_opcode.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_14_opcode_14.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_opcode_15.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_opcode_20.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[9].invert top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_valid_22.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].invert top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_2_opcode_2.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_3_opcode_3.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_7_opcode_7.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_4_opcode_4.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_8_opcode_8.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_0_opcode_0.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_9_opcode_9.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_5_opcode_5.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_6_opcode_6.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_1_opcode_1.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_15_valid_15.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_13_valid_13.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_12_valid_12.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_11_valid_11.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_jedec_cc_num_cc.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_20_valid_20.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_19_valid_19.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_valid_18.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_valid_17.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_en4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_ex4b_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_18_opcode_18.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_17_opcode_17.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_22_opcode_22.q[7:0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_23_valid_23.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_21_valid_21.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_16_valid_16.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wrdi_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cmd_info_wren_valid.q[0] top_earlgrey.u_spi_device.u_jedec.jedec.num_cc[7:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spid_jedec.sv:73 None Flat-To-Flat -- spi_device New Waived CMD_INFO is pre-configured, static; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:14 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag.sv:97 None Flat-To-Flat data97968.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:32 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:32 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:32 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:32 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:308 None Flat-To-Flat data97969.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:33 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:33 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:33 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:33 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:109 None Flat-To-Flat data97970.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:34 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:34 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:34 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:34 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].input_disable top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:307 None Flat-To-Flat data97971.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:35 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:34 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:35 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::IO_DIV4_CLK,LC_JTAG_TCK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:34 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 None Flat-To-Flat data97973.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:35 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:36 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:35 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:35 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_rv_dm.dap.dr_q[40] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:294 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:97 None Flat-To-Flat data97974.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:36 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:36 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:36 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag.sv:97 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:36 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:308 None Flat-To-Flat data97975.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:36 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:37 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:37 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.idcode_q[31] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:308 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:37 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:109 None Flat-To-Flat data97976.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:37 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:38 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:38 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.jtag_ir_shift_q[4] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:109 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:37 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].input_disable top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:307 None Flat-To-Flat data97977.dbg top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:38 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:39 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:39 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.tap_state_q[3:0] IO_DIV4_CLK::AST_EXT_CLK,RV_JTAG_TCK,MAIN_CLK dmi_jtag_tap.sv:307 None Flat-To-Flat -- top_earlgrey-2=1-3=1-4=1-6=1h0-15=1h0-16=573h4c000000460000004e0000004a000000480000003c00000036000000500000005400000000000000020000007003690000000092400000092000000012480000002480000-25=1h1 New Waived included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:16:39 PDT
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_cfg.tpm_reg_chk_dis top_earlgrey.u_spi_device.u_spi_tpm.locality[3:0] IO_DIV4_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK spi_tpm.sv:805 None Flat-To-Flat data98074.dbg spi_tpm New New
W_DATA: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.step_down_nq top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[0] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 None Flat-To-Flat data98140.dbg clkmgr New New
W_DATA: top_earlgrey.u_clkmgr_aon.u_no_scan_io_div4_div.gen_generic.u_impl_generic.step_down_ack_o top_earlgrey.u_clkmgr_aon.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic.q_o[1] AST_EXT_CLK,IO_CLK::IO_DIV4_CLK prim_generic_flop.sv:21 None Flat-To-Flat data98141.dbg clkmgr New New
W_DATA: top_earlgrey.u_spi_device.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic.q_o[23:0] top_earlgrey.u_spi_device.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic.q_o[23:0] SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK::IO_DIV2_CLK,SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK prim_generic_flop.sv:21 None Flat-To-Flat data98146.dbg spid_status New New
W_DATA: SPI_HOST_D3 top_earlgrey.u_spi_device.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic.q_o[3] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D1 top_earlgrey.u_spi_device.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic.q_o[1] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D0 top_earlgrey.u_spi_device.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic.q_o[0] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D2 top_earlgrey.u_spi_device.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic.q_o[2] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_IN_CLK,SPI_DEV_HC_IN_CLK,SPI_DEV_SLOW_PASS_IN_CLK,SPI_TPM_IN_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D2 top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic.q_o[2] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D0 top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic.q_o[0] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D3 top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic.q_o[3] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D1 top_earlgrey.u_spi_device.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic.q_o[1] SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_FAST_PASS_OUT_CLK,SPI_DEV_HC_OUT_CLK,SPI_DEV_SLOW_PASS_OUT_CLK,SPI_TPM_OUT_CLK prim_generic_flop.sv:21 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D0 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98241.dbg chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D0 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98242.dbg chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D1 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D1 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98243.dbg chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D2 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D2 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB10 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98244.dbg chip_earlgrey_asic New New
W_DATA: IOC11 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR12 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR10 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR11 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR13 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB11 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC12 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB12 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC10 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC8 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB8 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB6 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB3 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB9 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA8 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA6 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA3 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOB7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR5 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC9 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR6 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC4 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC3 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC1 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOC0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOA7 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,SPI_TPM_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR0 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR2 SPI_DEV_D3 IO_DIV2_CLK,IO_DIV4_CLK,JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: IOR3 SPI_DEV_D3 JTAG_TCK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_DEV_D0 SPI_HOST_D0 SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK::SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98251.dbg chip_earlgrey_asic New New
W_DATA: SPI_DEV_D1 SPI_HOST_D1 SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK::SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98252.dbg chip_earlgrey_asic New New
W_DATA: SPI_DEV_D2 SPI_HOST_D2 SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK::SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98253.dbg chip_earlgrey_asic New New
W_DATA: SPI_DEV_D3 SPI_HOST_D3 SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK::SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98254.dbg chip_earlgrey_asic New New
W_DATA: SPI_HOST_D0 SPI_DEV_D0 SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D1 SPI_DEV_D1 SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D2 SPI_DEV_D2 SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_HOST_D3 SPI_DEV_D3 SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: SPI_DEV_CS_L SPI_HOST_CS_L SPI_DEV_FAST_PASS_CSB_CLK,SPI_DEV_HC_CSB_CLK,SPI_DEV_SLOW_PASS_CSB_CLK::SPI_HOST_CLK,SPI_HOST_FAST_PASS_CLK,SPI_HOST_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat data98255.dbg chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q[5:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].pull_select SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[6] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_tpm_cfg_en.q[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].virt_od_en SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].drive_strength[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[28].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[4].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[7].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[8].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[9].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[5].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[3].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[6].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[7].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[5].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[4].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[9].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[3].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:13 PDT
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_6.q[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[6].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[8].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[2].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[0].input_disable SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic.q_o[3:0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0] SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:17 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].invert SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[6].pull_en SPI_DEV_D0 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[24].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap_q[1:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[25].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46.q[5:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[28].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[30].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_oe_retreg_q[7] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.id[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.rid[7:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_active_locality[4:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[21].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[22].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[23].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.int_status[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.int_enable[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_7.q[0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.status[31:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.access[39:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_control_mode.q[1:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:13 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[36].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[42].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_spi_tpm.sys_clk_tpm_reg.int_vector[7:0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[46].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[12].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[41].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[29].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[13].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[20].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[26].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[19].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[16].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[45].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[10].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[11].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[18].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_spi_device.u_reg.u_cfg_tx_order.q[0] SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived IO mode control is changed in SPI Idle state; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:15:17 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[17].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.dio_pad_attr_q[7].pull_en SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New Waived PAD Attributes are static signals.; set_rule_status run by user default on host smart-4c81ede7-4981-4551-80bd-53cee1c0abdf at Tuesday, 21 May 2024 12:17:08 PDT
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[14].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[44].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[43].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[40].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[27].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[39].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[1].invert SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[31].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[32].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[15].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[33].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[34].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[35].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
W_DATA: top_earlgrey.u_pinmux_aon.mio_pad_attr_q[2].input_disable SPI_DEV_D1 IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_FAST_PASS_CLK,SPI_DEV_HC_CLK,SPI_DEV_SLOW_PASS_CLK,SPI_TPM_CLK chip_earlgrey_asic.sv:247 None Flat-To-Flat -- chip_earlgrey_asic New New
Note: 533 more messages have been suppressed (max_msg_count = 1000)