50278df8b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 15.212m | 5.456ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 15.212m | 5.456ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 16.093m | 5.271ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 15.264m | 5.531ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 17.406m | 5.699ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.189h | 22.304ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 41.712m | 13.090ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 35.751m | 23.828ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 7.625m | 4.459ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 7.625m | 4.459ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 7.625m | 4.459ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.227m | 2.626ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 1.951m | 2.415ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.578m | 2.883ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 3.759m | 2.814ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 30.764m | 9.021ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.179m | 5.513ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 10.171m | 5.609ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 51.008m | 27.984ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.671h | 65.225ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 6.863m | 8.515ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.671h | 65.225ms | 5 | 5 | 100.00 |
| chip_csr_rw | 10.171m | 5.609ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.050s | 287.896us | 100 | 100 | 100.00 |
| V1 | TOTAL | 223 | 223 | 100.00 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 7.099m | 3.751ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 2.640h | 60.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.235m | 6.819ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.974m | 4.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.002m | 3.368ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.695m | 2.589ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 10.229m | 3.639ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 8.681m | 4.114ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 10.004m | 4.405ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.867m | 4.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 25.486m | 7.524ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.765m | 4.330ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.765m | 4.330ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.416m | 3.014ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 5.638m | 4.506ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 4.385m | 3.608ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 32.517m | 16.897ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 11.716m | 8.111ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.226m | 6.645ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.712m | 12.323ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 29.734m | 8.307ms | 0 | 3 | 0.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 17.692m | 8.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 11.269m | 5.279ms | 4 | 6 | 66.67 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 11.269m | 5.279ms | 4 | 6 | 66.67 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 27.457m | 19.379ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 20.721m | 13.075ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.420m | 5.017ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.096m | 5.416ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 3.882m | 3.344ms | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 8.226m | 6.645ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 6.560m | 7.120ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.100m | 3.329ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.242m | 4.198ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 5.353m | 5.147ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.242m | 4.198ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 9.694m | 5.674ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 13.470m | 8.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 13.470m | 8.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.344m | 7.172ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 24.409m | 8.496ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.211m | 3.209ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 10.892m | 5.692ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.340m | 2.799ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.641m | 2.874ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.422m | 2.603ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 7.933m | 5.377ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 9.889m | 5.871ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.779m | 3.931ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.591m | 5.052ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 28.866m | 13.214ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 16.313m | 14.008ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.341m | 4.221ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.245m | 4.212ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.417m | 4.114ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.866m | 4.804ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.750m | 4.641ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.158m | 4.458ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 16.313m | 14.008ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.341m | 4.221ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.245m | 4.212ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.417m | 4.114ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.866m | 4.804ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.750m | 4.641ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.158m | 4.458ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.580m | 5.020ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.482m | 5.927ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.036h | 21.445ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 3.951m | 2.397ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 13.454m | 5.257ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.035m | 2.628ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 7.683m | 4.265ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.512m | 3.404ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 7.432m | 4.873ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.977m | 2.908ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.514m | 2.468ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 15.674m | 6.049ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 19.705m | 7.651ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.070h | 28.534ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.912m | 3.432ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.133m | 3.596ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 7.975m | 4.587ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.360m | 3.602ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 10.269m | 5.377ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 34.794m | 22.709ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 47.874m | 18.078ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 18.312m | 7.205ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.192m | 5.336ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.732m | 3.476ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.567m | 5.760ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 7.530m | 9.744ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 25.115m | 18.717ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.856m | 7.849ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 13.470m | 8.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 27.578m | 18.985ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 32.953m | 26.517ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 32.452m | 17.936ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 8.397m | 5.550ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 7.530m | 9.744ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 6.065m | 4.225ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 52.759m | 40.963ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.405m | 7.292ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 7.801m | 5.751ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 52.693m | 35.606ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 18.106m | 7.216ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 38.729m | 26.342ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.139m | 2.474ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.567m | 5.760ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 5.353m | 5.147ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.420m | 5.017ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 9.802m | 6.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.135m | 4.275ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 29.140m | 12.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 3.985m | 2.841ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.567m | 5.760ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.071m | 3.028ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.544m | 4.997ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.567m | 5.760ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 24.409m | 8.496ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 4.583m | 2.798ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 29.140m | 12.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 8.784m | 5.149ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.577m | 4.281ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 28.390m | 14.359ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 23.846m | 7.508ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 31.883m | 9.027ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.129h | 255.815ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.544m | 4.997ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 32.517m | 16.897ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 8.226m | 6.645ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.712m | 12.323ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.513m | 3.096ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 8.518m | 4.386ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.596m | 5.400ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.207h | 43.829ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.547m | 4.533ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 21.095m | 9.161ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.838m | 9.408ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.070m | 8.920ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.829m | 3.981ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 7.412m | 9.912ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 17.527m | 8.181ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 4.986m | 6.139ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 16.313m | 14.008ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.341m | 4.221ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.245m | 4.212ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.417m | 4.114ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.866m | 4.804ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.750m | 4.641ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.158m | 4.458ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 32.517m | 16.897ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.226m | 6.645ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.712m | 12.323ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 6.560m | 7.120ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 4.845m | 2.512ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 6.716m | 3.714ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.095m | 4.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 26.621m | 20.926ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 26.621m | 20.926ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 26.621m | 20.926ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 43.461m | 20.144ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 43.461m | 20.144ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 10.080m | 6.075ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 7.019m | 18.789ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 7.019m | 18.789ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 7.019m | 18.789ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.304m | 3.557ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 3.951m | 2.397ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.418m | 2.941ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.340m | 2.799ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 11.124m | 3.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.660m | 3.285ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.035m | 2.628ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.641m | 2.874ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.864m | 3.474ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 4.582m | 3.008ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.512m | 3.404ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 9.829m | 3.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.803m | 2.933ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.731m | 3.018ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.422m | 2.603ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.173m | 2.392ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 22.653m | 6.941ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 10.919m | 5.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.458m | 2.961ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 22.653m | 6.941ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.174m | 5.081ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 15.994m | 7.863ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 3.942m | 2.861ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 43.382m | 11.161ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 15.327m | 4.925ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 9.829m | 3.981ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 7.683m | 4.265ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 9.063m | 5.583ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 11.124m | 3.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 41.194m | 9.195ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 56.574m | 19.877ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.036h | 21.445ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 10.892m | 5.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 10.892m | 5.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 10.892m | 5.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 7.880m | 3.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 7.412m | 9.912ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 7.412m | 9.912ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 8.883m | 4.325ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 7.432m | 4.873ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 17.872m | 8.821ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 17.527m | 8.181ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.567m | 5.760ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 11.269m | 5.279ms | 4 | 6 | 66.67 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 31.505m | 16.527ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.880m | 3.830ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.829m | 3.981ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.883m | 4.325ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.839m | 2.833ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 31.505m | 16.527ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.880m | 3.830ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.829m | 3.981ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 8.883m | 4.325ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.839m | 2.833ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.472m | 4.844ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.513m | 3.096ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.547m | 4.533ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 21.095m | 9.161ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.838m | 9.408ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 20.070m | 8.920ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.241m | 10.030ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 4.986m | 6.139ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 4.986m | 6.139ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 31.505m | 16.527ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.216m | 5.475ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.482m | 5.927ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 14.448m | 4.960ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.580m | 5.020ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.207h | 43.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 31.505m | 16.527ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 5.948m | 3.380ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 9.829m | 3.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.596m | 5.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.207h | 43.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.596m | 5.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.596m | 5.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.596m | 5.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.596m | 5.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.567m | 5.760ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 4.986m | 6.139ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 17.198m | 6.293ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.306m | 5.899ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 18.312m | 7.205ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 13.764m | 12.085ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.580m | 5.020ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.482m | 5.927ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.036h | 21.445ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 3.951m | 2.397ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 13.454m | 5.257ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.035m | 2.628ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 7.683m | 4.265ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.512m | 3.404ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 7.432m | 4.873ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.977m | 2.908ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.715m | 3.241ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 22.061m | 12.851ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 22.061m | 12.851ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.137m | 5.059ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.700m | 3.405ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.137m | 5.059ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 12.502m | 5.037ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 13.013m | 5.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 5.719m | 3.524ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 3.839m | 2.833ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 9.802m | 6.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 9.802m | 6.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.072m | 2.841ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 4.153m | 2.906ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.789m | 2.485ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.355m | 2.912ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.102m | 3.000ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 6.225m | 2.820ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 3.645m | 3.405ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.454m | 2.601ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 4.534m | 2.487ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 35.044m | 10.067ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 5.071m | 2.841ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 5.353m | 5.147ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 6.606m | 5.713ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.950m | 2.599ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.766m | 3.043ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.528m | 3.534ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.342m | 2.551ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.372m | 3.339ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.306m | 5.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 30.764m | 9.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 2.640h | 60.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 30.354m | 7.760ms | 3 | 3 | 100.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.931m | 3.410ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.088m | 2.732ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.141m | 3.361ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 3.697m | 3.118ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 30.882m | 23.791ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 6.560m | 7.120ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.273h | 47.046ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.301h | 51.203ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 17.603m | 10.854ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.357h | 49.301ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 30.882m | 23.791ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 4.111m | 3.659ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 5.592m | 4.712ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 5.937m | 4.740ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.248h | 114.277ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.266m | 4.353ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.875m | 10.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.133h | 47.681ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 2.471h | 55.278ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 7.974m | 5.140ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 7.974m | 5.140ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.671h | 65.225ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 58.974m | 27.456ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.179m | 5.513ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.171m | 5.609ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.671h | 65.225ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 58.974m | 27.456ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.179m | 5.513ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.171m | 5.609ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.853m | 2.548ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.390s | 37.511us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.230m | 10.515ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.042m | 7.163ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 57.430s | 580.984us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 24.312m | 116.053ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.367m | 67.900ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.090m | 1.340ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 57.740s | 1.366ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.893m | 2.570ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 57.740s | 1.366ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.957m | 3.053ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 51.202m | 169.211ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.390m | 2.639ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 13.774m | 19.457ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 12.407m | 19.159ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 19.906m | 10.913ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 18.387m | 25.992ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 30.354m | 7.760ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 40.486m | 18.768ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 30.721m | 8.074ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.782h | 77.082ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 34.171m | 8.807ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 26.368m | 8.128ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 31.102m | 8.334ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 26.983m | 8.305ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.834h | 77.571ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 28.931m | 8.228ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 23.577m | 7.644ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 27.628m | 8.769ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 29.201m | 8.738ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 42.214m | 11.615ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 49.267m | 11.302ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 43.618m | 11.401ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 41.922m | 11.529ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.861h | 151.882ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 41.883m | 10.911ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 43.991m | 11.556ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 41.393m | 11.759ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 45.127m | 11.323ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.749h | 78.152ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 29.697m | 8.548ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 28.763m | 7.827ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 28.680m | 8.130ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 24.091m | 8.080ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.700h | 77.559ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 31.380m | 8.083ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 31.163m | 7.828ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 25.311m | 8.420ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 31.885m | 8.227ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 3.835h | 77.413ms | 3 | 3 | 100.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.706h | 77.354ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 24.300m | 8.551ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 31.374m | 8.321ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 28.859m | 8.058ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 32.281m | 8.347ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 33.848m | 8.764ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 29.653m | 8.231ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 29.559m | 7.924ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 32.476m | 8.147ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 4.344h | 77.189ms | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 32.024m | 8.463ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 27.570m | 8.086ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 33.164m | 7.988ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 27.816m | 7.578ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 31.170m | 8.232ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 29.368m | 7.829ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 26.207m | 8.525ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 36.511m | 9.761ms | 3 | 3 | 100.00 |
| V2 | TOTAL | 2627 | 2651 | 99.09 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.179m | 3.471ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 3.958m | 2.112ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 42.532m | 12.801ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 37.869m | 10.746ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 27.544m | 11.268ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 25.612m | 10.781ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.321m | 6.316ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.567m | 5.760ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 1.981m | 2.474ms | 0 | 3 | 0.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 11.108m | 4.976ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.230s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 37.858m | 9.555ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 37.869m | 10.746ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 27.544m | 11.268ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 25.612m | 10.781ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 51.553m | 32.282ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 33.979m | 32.800ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 44.830m | 43.126ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 14 | 18 | 77.78 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 12.360m | 5.007ms | 3 | 3 | 100.00 | |
| TOTAL | 2873 | 2901 | 99.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 19 | 100.00 |
| V2 | 270 | 270 | 261 | 96.67 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 26 | 12 | 10 | 38.46 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.58 | 95.50 | 93.90 | 98.05 | -- | 94.47 | 97.93 | 99.62 |
UVM_ERROR @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[*] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (* [*] vs * [*]) has 15 failures:
0.rom_e2e_asm_init_test_unlocked0.2545485711
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 77223.322470 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 77223.322470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_test_unlocked0.4166170114
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 77188.614230 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 77188.614230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_dev.285905963
Line 1102, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8462.538516 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8462.538516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_dev.3205073675
Line 1097, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8485.000160 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8485.000160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod.963779105
Line 1100, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 7677.785880 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 7677.785880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod.1727799983
Line 1090, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8002.043610 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8002.043610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod_end.1875816296
Line 1099, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 7987.686160 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 7987.686160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod_end.517741676
Line 1094, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8567.710320 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8567.710320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_rma.126582158
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 7915.438368 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 7915.438368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_rma.340290692
Line 1099, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8586.281700 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8586.281700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:254) virtual_sequencer [chip_sw_patt_ios_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:
0.chip_sw_pattgen_ios.3618489933
Line 1093, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest/run.log
UVM_ERROR @ 7127.505586 us: (chip_sw_base_vseq.sv:254) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_patt_ios_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 5000000 ns
UVM_INFO @ 7127.505586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pattgen_ios.2800688300
Line 1094, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pattgen_ios/latest/run.log
UVM_ERROR @ 8306.926667 us: (chip_sw_base_vseq.sv:254) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_patt_ios_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 5000000 ns
UVM_INFO @ 8306.926667 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. has 3 failures:
0.chip_sw_otp_ctrl_vendor_test_csr_access.410971079
Line 1073, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
UVM_ERROR @ 2438.928870 us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.
UVM_INFO @ 2438.928870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otp_ctrl_vendor_test_csr_access.2063327380
Line 1074, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
UVM_ERROR @ 2310.554400 us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.
UVM_INFO @ 2310.554400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * straight after write. has 3 failures:
0.chip_sw_rv_dm_access_after_wakeup.1263425728
Line 1070, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_ERROR @ 3343.675949 us: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 3056429537 [0xb62d69e1]) Regname: jtag_dmi_ral.progbuf_0 reset value: 0x0 straight after write.
UVM_INFO @ 3343.675949 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_dm_access_after_wakeup.2710382333
Line 1069, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_ERROR @ 3196.119419 us: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1872042401 [0x6f9519a1]) Regname: jtag_dmi_ral.progbuf_0 reset value: 0x0 straight after write.
UVM_INFO @ 3196.119419 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:523) [data_integrity_escalation_reset_test_prog_sim_dv(sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c:363)] CHECK-STATUS-fail: FLA:* = Unavailable has 2 failures:
4.chip_sw_data_integrity_escalation.4214631037
Line 1099, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest/run.log
UVM_ERROR @ 3704.177560 us: (sw_logger_if.sv:523) [data_integrity_escalation_reset_test_prog_sim_dv(sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c:363)] CHECK-STATUS-fail: FLA:209 = Unavailable
UVM_INFO @ 3704.177560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.chip_sw_data_integrity_escalation.536979262
Line 1100, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest/run.log
UVM_ERROR @ 2545.521360 us: (sw_logger_if.sv:523) [data_integrity_escalation_reset_test_prog_sim_dv(sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c:363)] CHECK-STATUS-fail: FLA:209 = Unavailable
UVM_INFO @ 2545.521360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.1538075712
Line 1046, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.715788721
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
Job ID: smart:013debec-d2f6-4c7c-875b-e4786226bb49