877a77116| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 16.851m | 5.405ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 16.851m | 5.405ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 15.918m | 6.113ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 15.768m | 5.284ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 15.787m | 5.336ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.032h | 23.448ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 36.892m | 13.109ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 33.339m | 23.076ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.058m | 3.755ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.058m | 3.755ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.058m | 3.755ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.693m | 2.627ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.313m | 2.418ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.753m | 3.066ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.665m | 3.158ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 31.470m | 8.941ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.791m | 6.683ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 9.415m | 5.383ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.036h | 39.208ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.635h | 57.764ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 7.042m | 5.509ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.635h | 57.764ms | 5 | 5 | 100.00 |
| chip_csr_rw | 9.415m | 5.383ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 10.540s | 255.796us | 100 | 100 | 100.00 |
| V1 | TOTAL | 223 | 223 | 100.00 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 7.250m | 3.384ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.239h | 71.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.268m | 8.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 38.654m | 12.735ms | 2 | 3 | 66.67 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.175m | 3.454ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.269m | 3.329ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 9.848m | 3.647ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 12.443m | 4.141ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 10.473m | 4.188ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 8.931m | 3.584ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 24.740m | 7.368ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.998m | 4.990ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.998m | 4.990ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.795m | 3.288ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 9.071m | 5.583ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.516m | 3.766ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 23.035m | 14.866ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 11.729m | 8.350ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 10.188m | 6.536ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 31.476m | 18.438ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.346m | 2.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 25.567m | 9.360ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.527m | 5.529ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.527m | 5.529ms | 6 | 6 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 36.540m | 19.938ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 23.535m | 13.185ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 6.819m | 3.642ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 6.162m | 3.369ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 6.882m | 5.058ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 10.188m | 6.536ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 8.885m | 12.578ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.283m | 3.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.689m | 3.624ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 7.285m | 5.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.689m | 3.624ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 8.648m | 3.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.177m | 7.802ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.177m | 7.802ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 7.179m | 7.289ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 27.911m | 8.239ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.362m | 2.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 9.706m | 6.154ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.032m | 2.334ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.069m | 2.659ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.650m | 2.263ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 7.475m | 4.407ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.627m | 4.979ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 6.472m | 3.816ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 7.234m | 5.235ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 23.090m | 10.363ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 14.912m | 9.432ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.158m | 4.046ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.834m | 4.465ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.007m | 4.425ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.895m | 4.531ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.345m | 4.052ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.383m | 5.376ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 14.912m | 9.432ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.158m | 4.046ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.834m | 4.465ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.007m | 4.425ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.895m | 4.531ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.345m | 4.052ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.383m | 5.376ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.926m | 5.192ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.485m | 6.375ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.345m | 21.556ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.103m | 2.535ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.615m | 5.426ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.932m | 3.312ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.827m | 5.075ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.821m | 2.945ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 7.565m | 4.908ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.772m | 3.010ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.546m | 2.468ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 16.206m | 6.472ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 20.560m | 7.480ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 58.819m | 28.277ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.804m | 3.058ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.210m | 2.902ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 7.220m | 4.063ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.051m | 3.056ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9.131m | 5.739ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 30.578m | 18.288ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 43.242m | 15.185ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 16.217m | 5.914ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 9.996m | 5.189ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.169m | 3.654ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.215m | 6.155ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 9.066m | 8.823ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 28.364m | 23.137ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.394m | 7.565ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 11.177m | 7.802ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 25.086m | 19.277ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 31.591m | 20.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 28.743m | 12.631ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 9.245m | 5.369ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 9.066m | 8.823ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 9.283m | 5.659ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 43.708m | 35.984ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 7.580m | 5.374ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 7.250m | 4.307ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 48.340m | 29.188ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 15.608m | 7.181ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 30.746m | 20.274ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.576m | 2.906ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.215m | 6.155ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 7.285m | 5.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 6.819m | 3.642ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 10.785m | 5.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 4.894m | 3.740ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 28.157m | 14.152ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.481m | 2.164ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.215m | 6.155ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 4.677m | 2.947ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.065m | 4.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.215m | 6.155ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 27.911m | 8.239ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.371m | 2.540ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 28.157m | 14.152ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 10.506m | 6.016ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.466m | 4.025ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 28.404m | 13.105ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 34.472m | 10.932ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 25.893m | 7.268ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.225h | 254.169ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.065m | 4.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 23.035m | 14.866ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 10.188m | 6.536ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 31.476m | 18.438ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.889m | 3.115ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 9.928m | 5.097ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 8.235m | 5.306ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.340h | 45.143ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.891m | 4.037ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 18.584m | 7.454ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 20.796m | 7.137ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 17.900m | 8.068ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.082m | 4.383ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.199m | 8.781ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 16.077m | 9.494ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 5.258m | 9.164ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 14.912m | 9.432ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.158m | 4.046ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.834m | 4.465ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.007m | 4.425ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.895m | 4.531ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.345m | 4.052ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.383m | 5.376ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 23.035m | 14.866ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 10.188m | 6.536ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 31.476m | 18.438ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 8.885m | 12.578ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.231m | 3.027ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 5.432m | 3.281ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 8.537m | 3.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 29.483m | 23.861ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 29.483m | 23.861ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 29.483m | 23.861ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 45.206m | 20.386ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 45.206m | 20.386ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 7.997m | 5.509ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 12.139m | 18.969ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 12.139m | 18.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 12.139m | 18.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.645m | 2.656ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.103m | 2.535ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.430m | 2.257ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.032m | 2.334ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 10.485m | 4.024ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.951m | 3.695ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.932m | 3.312ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.069m | 2.659ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.349m | 2.858ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.465m | 3.369ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.821m | 2.945ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 9.082m | 4.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.596m | 3.238ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.786m | 2.987ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.650m | 2.263ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.394m | 3.314ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 25.325m | 7.913ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 11.113m | 4.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.128m | 2.935ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 25.325m | 7.913ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.869m | 4.441ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.065m | 5.804ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.174m | 2.883ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 50.735m | 12.034ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 15.931m | 5.857ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 9.082m | 4.383ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 8.827m | 5.075ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 9.396m | 5.727ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 10.485m | 4.024ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 42.364m | 8.666ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 1.013h | 19.385ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.345m | 21.556ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 9.706m | 6.154ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 9.706m | 6.154ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 9.706m | 6.154ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 8.286m | 3.914ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.199m | 8.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.199m | 8.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 9.119m | 5.426ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 7.565m | 4.908ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 19.957m | 11.356ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 16.077m | 9.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.215m | 6.155ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 12.527m | 5.529ms | 6 | 6 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 35.206m | 24.457ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.286m | 3.914ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.082m | 4.383ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.119m | 5.426ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.965m | 3.067ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 35.206m | 24.457ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.286m | 3.914ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.082m | 4.383ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.119m | 5.426ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.965m | 3.067ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.167m | 4.716ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.889m | 3.115ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.891m | 4.037ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 18.584m | 7.454ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 20.796m | 7.137ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 17.900m | 8.068ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.391m | 10.970ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 5.258m | 9.164ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 5.258m | 9.164ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 35.206m | 24.457ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.295m | 5.191ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.485m | 6.375ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 15.460m | 5.289ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.926m | 5.192ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.340h | 45.143ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 35.206m | 24.457ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.171m | 3.450ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 9.082m | 4.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.235m | 5.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.340h | 45.143ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.235m | 5.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.235m | 5.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 8.235m | 5.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.235m | 5.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.215m | 6.155ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 5.258m | 9.164ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.005m | 5.620ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.796m | 6.306ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 16.217m | 5.914ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 10.905m | 10.673ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.926m | 5.192ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.485m | 6.375ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.345m | 21.556ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.103m | 2.535ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.615m | 5.426ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.932m | 3.312ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.827m | 5.075ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.821m | 2.945ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 7.565m | 4.908ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.772m | 3.010ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.276m | 3.351ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 21.181m | 7.948ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 21.181m | 7.948ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.604m | 4.612ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.410m | 2.999ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.604m | 4.612ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 13.722m | 5.369ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 17.823m | 5.246ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.920m | 2.900ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 3.965m | 3.067ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 10.785m | 5.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 10.785m | 5.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.590m | 2.804ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 4.140m | 2.791ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 4.971m | 2.881ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.986m | 2.565ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.907m | 2.737ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.117m | 3.055ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.926m | 2.559ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 5.086m | 2.690ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.035m | 3.254ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 27.213m | 8.428ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 5.275m | 3.245ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.285m | 5.377ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8.823m | 5.637ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.376m | 2.878ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.684m | 3.092ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 5.109m | 2.339ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 3.739m | 2.260ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.457m | 2.665ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 7.969m | 4.910ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 31.470m | 8.941ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.239h | 71.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 33.511m | 8.743ms | 3 | 3 | 100.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.484m | 3.334ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 1.281m | 1.501ms | 0 | 1 | 0.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.175m | 2.515ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.265m | 3.614ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 31.729m | 28.646ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 8.885m | 12.578ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.531h | 46.414ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.362h | 50.997ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 16.409m | 11.612ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.361h | 48.238ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 31.729m | 28.646ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 4.526m | 4.874ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 4.990m | 4.896ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 6.139m | 4.282ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.054h | 111.639ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 10.140m | 3.796ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 6.493m | 9.253ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.689h | 59.214ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.026h | 65.211ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 11.256m | 6.260ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 11.256m | 6.260ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.635h | 57.764ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 57.837m | 28.423ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.791m | 6.683ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 9.415m | 5.383ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.635h | 57.764ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 57.837m | 28.423ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.791m | 6.683ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 9.415m | 5.383ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.757m | 2.603ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 6.940s | 48.616us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.949m | 10.539ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.097m | 7.127ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 58.830s | 540.976us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 24.366m | 121.392ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 20.931m | 67.271ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.028m | 1.484ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.050m | 1.435ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.417m | 2.583ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.050m | 1.435ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.516m | 3.812ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 53.662m | 166.985ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.334m | 2.644ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 13.807m | 17.755ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 11.602m | 20.254ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 16.296m | 16.102ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 21.659m | 25.247ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 33.511m | 8.743ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 39.400m | 24.214ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 28.001m | 8.285ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.376h | 76.011ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 27.771m | 9.100ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 26.232m | 9.163ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 34.627m | 8.698ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 29.774m | 8.167ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.637h | 75.286ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 29.264m | 8.127ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 34.894m | 8.868ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 35.075m | 9.575ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 33.044m | 8.544ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 7.209h | 147.460ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 48.823m | 11.665ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 51.253m | 12.475ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 50.003m | 11.389ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 43.744m | 12.165ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.009h | 146.142ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 45.951m | 11.606ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 37.475m | 12.418ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 49.909m | 12.132ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 48.122m | 11.653ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.673h | 75.670ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 29.461m | 8.761ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 24.017m | 8.201ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 32.605m | 9.090ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 31.660m | 8.093ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.316h | 74.555ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 32.687m | 8.300ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 33.986m | 8.514ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 31.850m | 8.410ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 32.340m | 8.309ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 3.683h | 74.599ms | 3 | 3 | 100.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.729h | 73.743ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 31.055m | 8.610ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 32.320m | 8.759ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 30.021m | 8.558ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 29.771m | 9.044ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 32.977m | 8.691ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 31.392m | 8.694ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 32.436m | 8.700ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 33.127m | 8.782ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 3.854h | 75.419ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 32.421m | 8.507ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 35.051m | 8.710ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 33.677m | 8.422ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 35.734m | 9.005ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 37.347m | 9.026ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 32.926m | 8.797ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 33.686m | 9.314ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 43.048m | 11.159ms | 3 | 3 | 100.00 |
| V2 | TOTAL | 2649 | 2651 | 99.92 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.418m | 3.300ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 4.756m | 3.035ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 0 | 1 | 0.00 | ||
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 28.980m | 10.417ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 35.032m | 10.853ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 34.753m | 11.556ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 8.118m | 5.864ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.215m | 6.155ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.395m | 2.832ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 12.010m | 6.231ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.150s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 29.930m | 8.974ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 28.980m | 10.417ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 35.032m | 10.853ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 34.753m | 11.556ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 53.061m | 29.089ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 1.072h | 31.889ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 47.777m | 31.733ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 16 | 18 | 88.89 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 13.990m | 6.141ms | 3 | 3 | 100.00 | |
| TOTAL | 2897 | 2901 | 99.86 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 19 | 100.00 |
| V2 | 270 | 270 | 268 | 99.26 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 26 | 12 | 10 | 38.46 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.73 | 95.67 | 94.19 | 98.10 | -- | 94.87 | 97.93 | 99.65 |
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
0.chip_sw_usbdev_stream.1365760013
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest/run.log
Job ID: smart:b24a6aab-ef27-47f4-a382-0cc7f5befb9b
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:716) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *f* has 1 failures:
0.chip_sw_lc_ctrl_raw_to_scrap.1229280521
Line 1073, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log
UVM_ERROR @ 1500.528357 us: (chip_sw_base_vseq.sv:716) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (456704 [0x6f800] vs 0 [0x0]) Unexpected status error 6f800000
UVM_INFO @ 1500.528357 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.2238721161
Line 1045, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:405) [chip_sw_spi_passthrough_collision_vseq] timeout occurred! has 1 failures:
2.chip_sw_spi_device_pass_through_collision.2600557822
Line 1089, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_FATAL @ 12734.800033 us: (chip_sw_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] timeout occurred!
UVM_INFO @ 12734.800033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---