12e3b8572e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.277m | 2.797ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.620m | 3.013ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.414m | 2.611ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.284m | 2.582ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 5.842m | 5.713ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 12.629m | 6.361ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 57.860m | 30.966ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.950h | 64.530ms | 2 | 5 | 40.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 16.645m | 10.534ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.950h | 64.530ms | 2 | 5 | 40.00 |
| chip_csr_rw | 12.629m | 6.361ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 15.830s | 248.982us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 7.904m | 3.703ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 7.904m | 3.703ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 7.904m | 3.703ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 12.414m | 4.584ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 12.414m | 4.584ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 11.834m | 4.742ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 11.045m | 4.678ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 11.587m | 4.738ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 44.295m | 12.933ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 27.324m | 8.293ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 19.205m | 9.196ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 217 | 220 | 98.64 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.488m | 5.044ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.488m | 5.044ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.504m | 3.097ms | 2 | 3 | 66.67 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.138m | 6.596ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.513m | 3.709ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 22.298m | 10.514ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 10.513m | 6.596ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 12.415m | 7.121ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 24.209m | 13.949ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.142m | 2.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 21.701m | 9.811ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 14.255m | 6.167ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 14.255m | 6.167ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.848m | 7.192ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.169h | 25.321ms | 2 | 3 | 66.67 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.502m | 4.346ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.255m | 6.428ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.273h | 18.880ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.316m | 2.410ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.190m | 7.255ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.229m | 3.109ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 33.105m | 12.096ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.503m | 2.812ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.472m | 5.154ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.670m | 3.424ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.714m | 2.832ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 16.957m | 7.200ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.524m | 4.863ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.096m | 3.204ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.524m | 4.863ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.738m | 2.436ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.417m | 3.324ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.306m | 3.138ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 6.320m | 2.458ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.649m | 2.415ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.638m | 3.698ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 6.331m | 2.981ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.586m | 3.366ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.737m | 3.374ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 22.728m | 7.411ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.440m | 6.218ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 6.408m | 5.736ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.448m | 2.509ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.900m | 3.276ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 5.951m | 3.060ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 3.898m | 2.653ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.532m | 3.444ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.574m | 3.403ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.792m | 4.420ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 5.318h | 82.064ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.213h | 15.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.988m | 5.895ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.114m | 4.654ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.160m | 10.800ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.430h | 61.543ms | 1 | 3 | 33.33 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 4.574h | 67.957ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 9.133m | 4.966ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 9.133m | 4.966ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.950h | 64.530ms | 2 | 5 | 40.00 |
| chip_same_csr_outstanding | 1.202h | 29.395ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.842m | 5.713ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 12.629m | 6.361ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.950h | 64.530ms | 2 | 5 | 40.00 |
| chip_same_csr_outstanding | 1.202h | 29.395ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.842m | 5.713ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 12.629m | 6.361ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.684m | 2.555ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 10.650s | 58.186us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.557m | 9.913ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.094m | 5.849ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.201m | 592.725us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 11.528m | 52.442ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 10.970m | 33.261ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.307m | 1.380ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.096m | 1.450ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.920m | 2.444ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.096m | 1.450ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 3.109m | 3.264ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 21.375m | 89.132ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.633m | 2.528ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 12.715m | 20.722ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 13.134m | 23.052ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 18.360m | 24.863ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 19.914m | 29.196ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.213h | 15.252ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.218h | 25.508ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.101h | 14.090ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 51.595m | 11.332ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.234h | 15.571ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.321h | 16.320ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.194h | 15.020ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.243h | 15.273ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 51.517m | 11.407ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.283h | 15.519ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.225h | 15.011ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.175h | 15.954ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.113h | 15.470ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.686h | 18.933ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 2.091h | 24.150ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2.100h | 24.957ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 2.088h | 25.078ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 2.130h | 23.979ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.641h | 17.981ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.990h | 23.958ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 2.023h | 23.592ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 2.086h | 23.419ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 2.002h | 23.235ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 53.424m | 11.505ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.168h | 14.820ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.082h | 15.193ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.161h | 14.376ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.028h | 14.534ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 48.389m | 11.005ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.084h | 14.666ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.030h | 14.180ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.032h | 14.965ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.035h | 14.482ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 53.968m | 11.621ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.272h | 15.805ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.261h | 15.582ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.269h | 15.666ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.260h | 14.872ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.300h | 14.803ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.273h | 14.976ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.333h | 15.400ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.442h | 18.051ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.947m | 2.591ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.316m | 2.410ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.325m | 2.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.808m | 2.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 41.621m | 13.246ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.397m | 19.003ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.397m | 19.003ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.165m | 4.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 9.440m | 6.218ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.165m | 4.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.230m | 9.632ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.230m | 9.632ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 10.664m | 8.006ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 9.918m | 5.737ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 17.092m | 6.088ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.808m | 2.781ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.320m | 2.520ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.257m | 2.902ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.629m | 4.475ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 9.270m | 4.935ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.573m | 4.428ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.457m | 3.848ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 18.783m | 8.379ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.755m | 4.648ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.129m | 4.395ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.405m | 4.690ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.136m | 5.295ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.924m | 3.750ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.760m | 4.598ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 17.848m | 7.192ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 16.470m | 12.367ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.405m | 4.690ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.136m | 5.295ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.502m | 4.346ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.255m | 6.428ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.273h | 18.880ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.316m | 2.410ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.190m | 7.255ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.229m | 3.109ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 33.105m | 12.096ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.503m | 2.812ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.472m | 5.154ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.670m | 3.424ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.891m | 2.363ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 13.139m | 4.604ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 18.990m | 7.654ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.333h | 25.306ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.621m | 2.722ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.258m | 3.588ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 29.839m | 12.533ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.806m | 3.890ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9.675m | 4.155ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 32.746m | 18.779ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.887h | 34.728ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.848m | 7.192ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 11.987m | 4.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 9.733m | 4.102ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.404m | 5.953ms | 99 | 100 | 99.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 33.774m | 8.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 30.186m | 7.983ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.391m | 4.424ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.671m | 6.134ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.542m | 2.629ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 18.761m | 8.996ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 30.135m | 25.478ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 7.040m | 3.254ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.010m | 3.945ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.771m | 4.393ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.135m | 25.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.135m | 25.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.071h | 20.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.071h | 20.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 9.542m | 6.211ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.397m | 19.003ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 3.516h | 41.144ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.491m | 2.514ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 21.734m | 7.220ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.491m | 2.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 30.186m | 7.983ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.756m | 3.281ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 38.121m | 20.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 15.473m | 5.372ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.255m | 6.428ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 10.598m | 3.986ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 12.502m | 4.346ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.637h | 42.851ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 38.121m | 20.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.357m | 3.561ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 40.524m | 11.520ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.751m | 4.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.637h | 42.851ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.751m | 4.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.751m | 4.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 10.751m | 4.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.751m | 4.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.404m | 5.953ms | 99 | 100 | 99.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 4.130m | 6.012ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.370m | 5.339ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 10.648m | 5.818ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 10.648m | 5.818ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.052m | 3.154ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.229m | 3.109ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.320m | 2.520ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.427m | 2.888ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 32.545m | 8.538ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 14.211m | 4.534ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 13.454m | 5.268ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 13.201m | 5.134ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 9.123m | 4.439ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 40.524m | 11.520ms | 0 | 3 | 0.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 33.105m | 12.096ms | 0 | 3 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 28.393m | 9.583ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 41.621m | 13.246ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.423h | 16.227ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.635m | 2.513ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.539m | 3.078ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.503m | 2.812ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 40.524m | 11.520ms | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.268m | 2.540ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.763m | 2.712ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.257m | 2.902ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 9.043m | 5.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 22.298m | 10.514ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 12.415m | 7.121ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 24.209m | 13.949ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.585m | 3.426ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 35.909m | 11.390ms | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 10.751m | 4.929ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.637h | 42.851ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.093m | 4.860ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 21.142m | 9.883ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.111m | 7.072ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 21.546m | 7.431ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 40.524m | 11.520ms | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.860m | 9.274ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 13.395m | 9.796ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 4.130m | 6.012ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 16.470m | 12.367ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.755m | 4.648ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.129m | 4.395ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.405m | 4.690ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.136m | 5.295ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.924m | 3.750ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 9.760m | 4.598ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 22.298m | 10.514ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 12.415m | 7.121ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 24.209m | 13.949ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 15.982m | 20.691ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.480m | 3.760ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.228m | 3.299ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 3.573m | 4.072ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.432m | 3.170ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 43.411m | 25.672ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 15.982m | 20.691ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 2.003h | 46.929ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.711h | 46.893ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 18.393m | 11.265ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.867h | 46.070ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 43.411m | 25.672ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.386m | 1.963ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.672m | 2.273ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.754m | 2.463ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 38.121m | 20.598ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.809m | 3.674ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 40.524m | 11.520ms | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.685m | 5.486ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.745m | 3.109ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 38.121m | 20.598ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.809m | 3.674ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 40.524m | 11.520ms | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.685m | 5.486ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.745m | 3.109ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.750m | 4.707ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.585m | 3.426ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.093m | 4.860ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 21.142m | 9.883ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.111m | 7.072ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 21.546m | 7.431ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.221m | 10.110ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 4.130m | 6.012ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 4.130m | 6.012ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.489h | 27.243ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 8.603m | 7.156ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 28.851m | 21.499ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 8.188m | 8.044ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 11.746m | 9.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 10.776m | 6.591ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 36.756m | 23.372ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 26.772m | 14.490ms | 2 | 3 | 66.67 |
| chip_sw_aon_timer_wdog_bite_reset | 14.230m | 9.632ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 24.284m | 11.409ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 11.270m | 5.332ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 8.603m | 7.156ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 6.004m | 5.106ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 57.726m | 37.126ms | 1 | 3 | 33.33 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.255m | 7.660ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 5.199m | 2.923ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 46.783m | 21.983ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 18.761m | 8.996ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 27.429m | 10.975ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 53.162m | 22.801ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.249m | 3.002ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.404m | 5.953ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.860m | 9.274ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.860m | 9.274ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 27.429m | 10.975ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 46.783m | 21.983ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 11.270m | 5.332ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.440m | 6.218ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.604m | 5.363ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 10.308m | 6.394ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 9.923m | 5.060ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 34.044m | 12.526ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.106m | 3.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.404m | 5.953ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 24.930m | 7.620ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 19.074m | 6.887ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 10.290m | 3.707ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.078m | 4.631ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.607m | 2.730ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.347m | 3.013ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.213h | 15.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.011m | 7.797ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.515m | 4.974ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 8.676m | 3.636ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.716m | 2.979ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 12.685m | 5.486ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.472m | 5.154ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 13.538m | 8.994ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 13.405m | 7.664ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 13.395m | 9.796ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.404m | 5.953ms | 99 | 100 | 99.00 |
| chip_sw_data_integrity_escalation | 14.255m | 6.167ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.998m | 2.383ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.528m | 3.158ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 6.258m | 3.358ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 8.845m | 3.529ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 29.185m | 8.306ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.340h | 31.768ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 45.439m | 11.356ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.100m | 3.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 9.043m | 5.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.404m | 5.953ms | 99 | 100 | 99.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.847m | 3.468ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 34.044m | 12.526ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 7.036m | 3.784ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.344m | 3.684ms | 88 | 90 | 97.78 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 17.820m | 9.502ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 33.774m | 8.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 24.930m | 7.620ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 24.285m | 7.619ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.400h | 254.457ms | 1 | 3 | 33.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 18.629m | 11.769ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 24.200m | 13.212ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.604m | 5.363ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 7.074m | 4.175ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.665m | 7.210ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 12.415m | 7.121ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 15.982m | 20.691ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2617 | 2644 | 98.98 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.400m | 3.204ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 26.917m | 5.721ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 35.553m | 11.378ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 32.925m | 11.851ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 35.254m | 12.050ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.011h | 32.023ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 1.060h | 39.964ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 1.074h | 31.095ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 2.156h | 27.644ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.162m | 3.848ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 8.328m | 2.952ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 28.570m | 7.599ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 33.561m | 9.481ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.082m | 3.769ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 19.956m | 6.163ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 5.085m | 3.417ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 9.656m | 4.891ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 8.864m | 5.894ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 11.988m | 5.197ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 27.429m | 10.975ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.404m | 5.953ms | 99 | 100 | 99.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 5.701m | 3.933ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 12.414m | 4.584ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.204h | 18.425ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 35.553m | 11.378ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 32.925m | 11.851ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 35.254m | 12.050ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.316m | 4.811ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 47 | 51 | 92.16 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.200m | 3.375ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 11.582m | 5.773ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.748m | 3.295ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_descrambling | 9.249m | 4.180ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.206h | 17.079ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 17.414m | 5.779ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 13.906m | 4.393ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 6.958m | 3.671ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 6.529m | 6.204ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.888m | 2.542ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 3.762m | 2.606ms | 1 | 3 | 33.33 | ||
| chip_sw_flash_ctrl_write_clear | 5.720m | 3.384ms | 3 | 3 | 100.00 | ||
| TOTAL | 2918 | 2954 | 98.78 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 12 | 12 | 11 | 91.67 |
| V1 | 18 | 18 | 17 | 94.44 |
| V2 | 285 | 270 | 257 | 90.18 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 21 | 23.33 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.95 | 95.51 | 93.50 | 95.41 | -- | 94.18 | 97.57 | 99.53 |
Offending '$stable(key_data_i)' has 12 failures:
0.chip_sw_keymgr_key_derivation.3113643184369093583679399800426852774675945877230554336945835923542671201882
Line 446, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 7761.859150 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 7761.859150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation.12058158611102368724225096030271513167018455891421541912155410388279199556745
Line 465, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 10392.377244 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 10392.377244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_key_derivation_prod.56535498752463846177104036857762572679593258610069678531516978711030968816902
Line 454, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 11389.694502 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 11389.694502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation_prod.49731997290085139070142643638375010115398458892523319521309231009723031495075
Line 453, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 9436.635940 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 9436.635940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_key_derivation_jitter_en.96398158238811209078760313719133164424584698193481652160597215723661619824207
Line 449, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 6024.542380 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6024.542380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation_jitter_en.95527579044730380548127693909005614199849802557220018223757811102815315678544
Line 450, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 8432.232954 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 8432.232954 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.109947663602301679577287330349082215605485378618569742437714504674152543918738
Line 483, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 12532.522173 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 12532.522173 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.112457217704082815483936258025839752935730634440592036396174560139242829615269
Line 460, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 8451.783025 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 8451.783025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 11 failures:
Test chip_sw_exit_test_unlocked_bootstrap has 2 failures.
0.chip_sw_exit_test_unlocked_bootstrap.109077436304173827496244919082461902439434966114641311619368910226286133650878
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
1.chip_sw_exit_test_unlocked_bootstrap.21575543937468984491315682654102842587131953715666986534325181704318895644147
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.83325991584148147802668873431862911981223845762159347439752969082868118514234
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
1.chip_sw_rv_timer_systick_test.101473889734360845502419120020296942231994757277038979647618460491372273579860
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 2 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.107575505414166906847277134780869672045048490345667986417171246128537638929482
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.69685560099775959191584921014352981277239838517389728721476141333682601816014
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.85904629958128888773345987293126494191395196432579697891575857383130327392459
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job timed out after 300 minutes
Test chip_csr_aliasing has 3 failures.
1.chip_csr_aliasing.83731903659477543369273537672119626324530837405261630250912120195706484460980
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
3.chip_csr_aliasing.60807781552689483622069194091007756352145826145522362759622503378088636066393
Log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
... and 1 more failures.
UVM_ERROR @ * us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A has 5 failures:
0.chip_sw_pwrmgr_sleep_power_glitch_reset.51297825544843621109225124649278886318388928162920146559078652453292486865193
Line 454, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 3678.288480 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 3678.288480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sleep_power_glitch_reset.85049858740024298087961094592282791540154851959688534250070849190770963727452
Line 443, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 2922.726910 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 2922.726910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.8933598265604472074275819139450020396076876176664540592322479055962703807463
Line 515, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 24768.366263 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 24768.366263 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.98693523464566508555149147324275494681616645610865442827020881590626645890621
Line 447, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 10322.618720 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 10322.618720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.107493546597864321224341702196883871314538420000895738859299610583295778249878
Line 432, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2775.354472 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2775.354472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_lockstep_glitch.97132298125651402030984039315832573855197439509677813626043365911336725160756
Line 440, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2694.287684 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2694.287684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
32.chip_sw_alert_handler_lpg_sleep_mode_alerts.103719469637355184517309333842995232387902659059541770686560119959071065312492
Line 430, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4405.355666 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 4405.355666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
87.chip_sw_alert_handler_lpg_sleep_mode_alerts.34510585730371996823893909719096497619972996695534105434015734245807170169534
Line 451, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3518.175448 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3518.175448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:126)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
1.chip_sw_ast_clk_rst_inputs.10456976057852455100155234439349897568600228572020247375610024906144854716739
Line 457, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
UVM_ERROR @ 22617.892048 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:126)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 22617.892048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
2.chip_sw_sleep_pin_mio_dio_val.7199194922343131574360977148501492938907321465683275211904464753657099235936
Line 550, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest/run.log
UVM_ERROR @ 2764.016000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 2764.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.80496379565309972817821908546932808995597343166709813651777563972652502424319
Line 441, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 10532.698632 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 10532.698632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
11.chip_sw_all_escalation_resets.49239288456815953851892665567013933227259472367760864112977776860457622491913
Line 428, in log /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3078.081832 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3078.081832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---