9f20940d49| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| crypto_lib_hash_stress | crypto_lib_hash_stress | 0 | 0 | -- | |||
| crypto_lib_ecc_stress | crypto_lib_ecc_stress | 0 | 0 | -- | |||
| crypto_lib_rsa_key_gen_stress | crypto_lib_rsa_key_gen_stress | 0 | 0 | -- | |||
| crypto_lib_rsa_stress | crypto_lib_rsa_stress | 0 | 0 | -- | |||
| crypto_lib_aes_stress | crypto_lib_aes_stress | 0 | 0 | -- | |||
| crypto_lib_symmetric_keygen | crypto_lib_symmetric_keygen | 0 | 0 | -- | |||
| crypto_lib_entropy | crypto_lib_entropy | 0 | 0 | -- | |||
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.926m | 2.753ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 3.174m | 2.977ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 6.236m | 3.459ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.412m | 3.687ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 8.278m | 8.056ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 15.950m | 6.152ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.645h | 59.186ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.957h | 61.106ms | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 18.442m | 13.369ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.957h | 61.106ms | 3 | 5 | 60.00 |
| chip_csr_rw | 15.950m | 6.152ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 15.220s | 252.207us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 10.601m | 4.102ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 10.601m | 4.102ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 10.601m | 4.102ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 13.797m | 4.208ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 13.797m | 4.208ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 13.890m | 4.206ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 11.351m | 3.827ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 13.690m | 4.449ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 50.667m | 13.218ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 53.863m | 13.179ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 28.322m | 13.063ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 218 | 220 | 99.09 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.720m | 5.576ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.720m | 5.576ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.234m | 3.524ms | 2 | 3 | 66.67 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 5.037m | 3.606ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.055m | 3.524ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 29.992m | 15.698ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 11.792m | 6.419ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 23.544m | 11.852ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 33.759m | 14.901ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 6.325m | 3.371ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 25.867m | 8.625ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 17.123m | 6.751ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 17.123m | 6.751ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.971m | 7.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.120h | 22.114ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.962m | 4.135ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.005m | 5.685ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.382h | 18.484ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.785m | 2.855ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 21.704m | 6.461ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.001m | 2.969ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 38.942m | 12.821ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.246m | 2.987ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.115m | 5.347ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.552m | 3.120ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.581m | 3.686ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 17.901m | 6.737ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.733m | 5.012ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.823m | 3.260ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.733m | 5.012ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.116m | 2.523ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.755m | 3.584ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.728m | 3.459ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 6.456m | 2.815ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 5.529m | 2.709ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 10.923m | 3.882ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.753m | 2.189ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.494m | 3.761ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 7.916m | 3.185ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 22.489m | 6.352ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.475m | 5.530ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 9.412m | 6.920ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 6.340m | 2.713ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.684m | 3.592ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.338m | 2.664ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.371m | 2.849ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 6.234m | 3.172ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.830m | 3.271ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 13.498m | 4.459ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 5.823h | 82.791ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.343h | 15.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 6.262m | 6.825ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.994m | 4.566ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 11.897m | 10.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 4.167h | 68.305ms | 1 | 3 | 33.33 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 7.482m | 4.102ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 7.482m | 4.102ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.957h | 61.106ms | 3 | 5 | 60.00 |
| chip_same_csr_outstanding | 1.199h | 30.421ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.278m | 8.056ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 15.950m | 6.152ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.957h | 61.106ms | 3 | 5 | 60.00 |
| chip_same_csr_outstanding | 1.199h | 30.421ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.278m | 8.056ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 15.950m | 6.152ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.879m | 2.194ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 10.410s | 57.875us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.725m | 11.211ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.417m | 6.147ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.189m | 617.739us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.743m | 95.055ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 21.311m | 61.115ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.407m | 1.518ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.197m | 1.431ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 2.152m | 2.372ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.197m | 1.431ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 3.393m | 3.635ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 48.049m | 175.069ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.720m | 2.648ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 16.124m | 19.767ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 9.949m | 18.587ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 19.224m | 27.096ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 14.468m | 16.368ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.343h | 15.182ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.516h | 27.122ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.325h | 14.774ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 1.006h | 11.986ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.348h | 15.534ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.272h | 15.755ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.363h | 15.928ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.330h | 15.403ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 57.552m | 11.326ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.410h | 15.874ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.308h | 15.605ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.362h | 15.748ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.372h | 14.951ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.945h | 19.296ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 2.383h | 24.251ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2.330h | 24.764ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 2.361h | 24.832ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 2.165h | 23.882ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.609h | 18.008ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 2.191h | 23.663ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 2.153h | 23.576ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 2.265h | 23.843ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 2.244h | 22.873ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 55.049m | 11.458ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.205h | 14.852ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.243h | 15.293ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.253h | 14.797ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.248h | 14.143ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 58.718m | 11.507ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.279h | 15.265ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.218h | 14.361ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.250h | 15.293ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.410h | 14.173ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 1.054h | 12.135ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.384h | 15.386ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.567h | 15.453ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.418h | 15.985ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.283h | 14.619ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 2.750h | 29.567ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 2.674h | 29.262ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 2.714h | 28.796ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.609h | 17.837ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 15.790m | 19.786ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 15.790m | 19.786ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.269m | 3.735ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.785m | 2.855ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 6.196m | 3.008ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 6.193m | 2.988ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 48.195m | 13.544ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.788m | 3.442ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 12.486m | 5.349ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 15.607m | 5.880ms | 99 | 100 | 99.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs_0 | 24.704m | 6.382ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.375m | 4.113ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.851m | 5.047ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.998m | 3.602ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 37.582m | 12.957ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.276m | 4.586ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.164m | 4.029ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | ||
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 38.275m | 9.316ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 37.167m | 8.695ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 25.864m | 7.353ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 10.240m | 3.821ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 9.475m | 5.530ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 10.240m | 3.821ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.733m | 10.204ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.733m | 10.204ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 12.427m | 6.357ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 9.583m | 4.645ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 16.547m | 5.446ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 6.193m | 2.988ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.924m | 3.355ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.717m | 2.474ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 12.194m | 5.986ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.612m | 5.811ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 11.287m | 5.179ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 9.572m | 4.903ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 26.019m | 11.575ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.521m | 4.149ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.861m | 4.485ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.370m | 4.452ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.007m | 4.622ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.146m | 4.170ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.113m | 4.561ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 17.971m | 7.829ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 18.138m | 12.896ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.370m | 4.452ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.007m | 4.622ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.962m | 4.135ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.005m | 5.685ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.382h | 18.484ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.785m | 2.855ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 21.704m | 6.461ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.001m | 2.969ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 38.942m | 12.821ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.246m | 2.987ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.115m | 5.347ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.552m | 3.120ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.549m | 3.221ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 12.657m | 5.121ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 21.780m | 7.730ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.489h | 25.012ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.941m | 3.097ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.658m | 2.685ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 35.259m | 12.562ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.900m | 3.248ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9.581m | 4.110ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 45.337m | 26.365ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 5.988h | 147.709ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.971m | 7.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 13.651m | 5.267ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.644m | 3.850ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 15.607m | 5.880ms | 99 | 100 | 99.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 38.275m | 9.316ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 32.348m | 8.761ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 10.133m | 4.048ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 12.775m | 5.281ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.944m | 3.143ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.458h | 37.646ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 5.619m | 3.535ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 22.620m | 7.183ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.619m | 3.535ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 32.348m | 8.761ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.856m | 2.617ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 42.987m | 23.192ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.658m | 5.587ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.005m | 5.685ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 13.345m | 3.723ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 11.962m | 4.135ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 2.178h | 45.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 42.987m | 23.192ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.102m | 3.675ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 36.572m | 10.176ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.747m | 4.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 2.178h | 45.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.747m | 4.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.747m | 4.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.747m | 4.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.747m | 4.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 15.607m | 5.880ms | 99 | 100 | 99.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 6.951m | 7.690ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.846m | 5.715ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 13.722m | 6.208ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 13.722m | 6.208ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.533m | 3.410ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.001m | 2.969ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.924m | 3.355ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.533m | 2.986ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 35.099m | 8.407ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 15.631m | 5.421ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 14.012m | 5.727ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 16.298m | 4.555ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 12.053m | 4.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 36.572m | 10.176ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 38.942m | 12.821ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 34.470m | 10.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 48.195m | 13.544ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.328h | 16.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.740m | 2.470ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.142m | 3.234ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.246m | 2.987ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 36.572m | 10.176ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.622m | 2.877ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 37.371m | 9.212ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.717m | 2.474ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 12.486m | 5.349ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 29.992m | 15.698ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 23.544m | 11.852ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 33.759m | 14.901ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.654m | 3.262ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 35.145m | 9.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.747m | 4.273ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 2.178h | 45.399ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.660m | 4.275ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 24.392m | 9.070ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.355m | 9.260ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 23.535m | 8.790ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.572m | 10.176ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 9.774m | 9.663ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 19.268m | 10.774ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 6.951m | 7.690ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 18.138m | 12.896ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.521m | 4.149ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.861m | 4.485ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.370m | 4.452ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.007m | 4.622ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.146m | 4.170ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.113m | 4.561ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 29.992m | 15.698ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 23.544m | 11.852ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 33.759m | 14.901ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 12.032m | 16.842ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.987m | 3.131ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.633m | 3.132ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.480m | 3.146ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.854m | 3.102ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 40.148m | 25.885ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 12.032m | 16.842ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 2.117h | 48.822ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 2.168h | 47.871ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 23.661m | 10.524ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 2.088h | 47.719ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 40.148m | 25.885ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 3.506m | 2.732ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.909m | 2.158ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.171m | 2.245ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_isa | chip_sw_otbn_isa | 0 | 0 | -- | ||
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 1.380h | 17.215ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.382h | 18.484ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 16.547m | 5.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 16.547m | 5.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 16.547m | 5.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 9.407m | 3.152ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_keymgr | chip_sw_otbn_keymgr | 0 | 0 | -- | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 42.987m | 23.192ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.407m | 3.152ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.572m | 10.176ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.284m | 4.762ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.723m | 2.183ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 42.987m | 23.192ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.407m | 3.152ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.572m | 10.176ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.284m | 4.762ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.723m | 2.183ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 10.860m | 5.028ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.654m | 3.262ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.660m | 4.275ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 24.392m | 9.070ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.355m | 9.260ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 23.535m | 8.790ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.862m | 8.971ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 6.951m | 7.690ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 6.951m | 7.690ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.954h | 28.430ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.514m | 6.319ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 37.989m | 23.684ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 9.061m | 7.448ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 14.793m | 10.657ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 13.860m | 7.570ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 34.682m | 21.233ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 25.391m | 16.726ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 15.733m | 10.204ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 28.184m | 13.470ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 11.055m | 4.586ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.514m | 6.319ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.475m | 3.872ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.067h | 40.341ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.160m | 6.263ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.945m | 5.990ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 45.390m | 25.382ms | 2 | 3 | 66.67 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 22.221m | 7.396ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 32.909m | 10.935ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 42.807m | 21.676ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.337m | 3.432ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 15.607m | 5.880ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.774m | 9.663ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.774m | 9.663ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 32.909m | 10.935ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 45.390m | 25.382ms | 2 | 3 | 66.67 | ||
| chip_sw_pwrmgr_wdog_reset | 11.055m | 4.586ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.475m | 5.530ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.368m | 5.076ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 16.844m | 7.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.737m | 4.333ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 37.582m | 12.957ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.082m | 3.189ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 15.607m | 5.880ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 37.167m | 8.695ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 17.323m | 4.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 17.328m | 5.522ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.627m | 2.856ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 4.723m | 2.183ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 16.844m | 7.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 16.844m | 7.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_smoke | chip_sw_rv_core_ibex_smoke | 0 | 0 | -- | ||
| V2 | chip_sw_rv_core_ibex_epmp_smoke | chip_sw_rv_core_ibex_epmp_smoke | 0 | 0 | -- | ||
| V2 | chip_sw_rv_core_ibex_mem_smoke | chip_sw_rv_core_ibex_mem_smoke | 0 | 0 | -- | ||
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 25.189m | 12.154ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 29.526m | 14.231ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.368m | 5.076ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.559m | 4.978ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.644m | 6.333ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 23.544m | 11.852ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 12.032m | 16.842ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 24.704m | 6.382ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.375m | 4.113ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.851m | 5.047ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 6.822m | 3.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 6.306m | 3.537ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.343h | 15.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 16.192m | 8.151ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 11.531m | 4.994ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 8.292m | 3.640ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 6.377m | 3.075ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 11.284m | 4.762ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.115m | 5.347ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 12.023m | 6.733ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 15.524m | 7.590ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 19.268m | 10.774ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 15.607m | 5.880ms | 99 | 100 | 99.00 |
| chip_sw_data_integrity_escalation | 17.123m | 6.751ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 22.221m | 7.396ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 33.427m | 22.423ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.704m | 2.493ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 9.621m | 3.941ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 14.019m | 4.925ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 33.427m | 22.423ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 33.427m | 22.423ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.234h | 20.535ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.234h | 20.535ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 9.854m | 7.231ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 15.790m | 19.786ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 4.912m | 2.951ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 5.502m | 3.007ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 6.946m | 3.675ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.088m | 4.206ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 27.990m | 7.591ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.427h | 31.589ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 50.899m | 11.533ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 3.684m | 2.588ms | 1 | 1 | 100.00 |
| V2 | TOTAL | 2642 | 2657 | 99.44 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.201m | 3.683ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 3.895m | 2.748ms | 2 | 3 | 66.67 |
| V2S | TOTAL | 5 | 6 | 83.33 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 26.867m | 5.909ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.618m | 11.561ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 38.231m | 11.117ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 44.517m | 11.754ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.041h | 32.571ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 46.367m | 32.657ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 1.062h | 40.664ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 2.311h | 27.203ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_aes_stall_test | chip_sw_aes_stall_test | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 15.498m | 4.969ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 8.754m | 3.074ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 25.099m | 5.817ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 41.110m | 10.695ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 13.168m | 3.771ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 21.179m | 6.211ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.916m | 2.687ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 9.174m | 5.370ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_pwm_smoketest | chip_sw_pwm_smoketest | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 10.051m | 7.071ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 9.629m | 4.614ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 32.909m | 10.935ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.618m | 11.561ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 38.231m | 11.117ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 44.517m | 11.754ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 26.096s | 0 | 3 | 0.00 | |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 15.607m | 5.880ms | 99 | 100 | 99.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 6.952m | 3.131ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | chip_sw_spi_host_pass_through | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 13.797m | 4.208ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.235h | 18.631ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | TOTAL | 44 | 51 | 86.27 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.728m | 3.391ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 10.020m | 5.108ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_rot_auth_config | 0 | 1 | 0.00 | ||||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.065m | 2.732ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_descrambling | 12.388m | 3.982ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 8.443m | 3.548ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 9.831m | 6.791ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 6.899m | 3.361ms | 3 | 3 | 100.00 | ||
| TOTAL | 2930 | 2956 | 99.12 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 15 | 8 | 7 | 46.67 |
| V1 | 18 | 18 | 17 | 94.44 |
| V2 | 294 | 275 | 267 | 90.82 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 93 | 23 | 20 | 21.51 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.96 | 95.39 | 93.47 | 95.36 | -- | 94.22 | 97.71 | 99.60 |
Job timed out after * minutes has 18 failures:
Test chip_sw_inject_scramble_seed has 2 failures.
0.chip_sw_inject_scramble_seed.27458187709621827725996591542938519769058474714882201797535549643861437876439
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log
Job timed out after 300 minutes
1.chip_sw_inject_scramble_seed.61221928730040738705835824777064329406596770434819540252470639883948416955199
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest/run.log
Job timed out after 300 minutes
Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
0.chip_sw_exit_test_unlocked_bootstrap.94003650569483262374134989596350056947744629144183769283091709927539159989293
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
1.chip_sw_exit_test_unlocked_bootstrap.96378258333270322797611196585851632173411015452496292866638828167077562884302
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
... and 1 more failures.
Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
0.chip_sw_otp_ctrl_rot_auth_config.106090634061529762570409712822143975253885250983293409807133029624038982085238
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
Job timed out after 240 minutes
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.54714494876412088481916269169180211395183786898715198969749743805570110680213
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
1.chip_sw_rv_timer_systick_test.22128020004676187476925882739409365877199451527829410781009073987180754854952
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 3 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.98952500422589109915113310161996219677252612219133403751446257875220736152033
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.54736043621824100504527757500743547677393214785060999928068190865318363619403
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
... and 1 more failures.
... and 3 more tests.
Job returned non-zero exit code has 3 failures:
0.chip_sw_rv_dm_access_after_escalation_reset.221540139489449756552820237610396027422984030998575746467364598237007982814
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log
Loading:
Loading:
Loading: 0 packages loaded
ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspaces/repo/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
WARNING: Target pattern parsing failed.
ERROR: no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspaces/repo/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
INFO: Elapsed time: 0.318s
INFO: 0 processes.
FAILED: Build did NOT complete successfully (0 packages loaded)
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_rv_dm_access_after_escalation_reset.41718364098296281816721620557681983739842796204961504775181426218407109735909
Log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log
Loading:
Loading:
Loading: 0 packages loaded
ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspaces/repo/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
WARNING: Target pattern parsing failed.
ERROR: no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspaces/repo/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
INFO: Elapsed time: 0.327s
INFO: 0 processes.
FAILED: Build did NOT complete successfully (0 packages loaded)
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
0.chip_sw_sleep_pin_mio_dio_val.56270650938846639579511584361204237813456249840497618326930287256787540323521
Line 658, in log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
UVM_ERROR @ 2986.777500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 2986.777500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.46168829899692087758494622242859650223200638661054569916400119680987722768758
Line 500, in log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 16321.043628 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 16321.043628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
1.chip_sw_rv_core_ibex_lockstep_glitch.96240977549740112444289321971970815727883013243333826519472167102459174375978
Line 413, in log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2714.494628 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2714.494628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
61.chip_sw_all_escalation_resets.98180835216420254898046919847409929517040287698098092814120161993066260155326
Line 418, in log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3143.647780 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3143.647780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
83.chip_sw_alert_handler_lpg_sleep_mode_alerts.34798778295617911142115336810277280148779392501022499917999921739293508472934
Line 477, in log /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4088.350056 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 4088.350056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---