Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	5713400	1			T4	5030		T5	2220		T6	486
values[2]	1114700	1			T4	991		T6	924		T21	991
values[3]	197300	1			T4	87		T6	642		T21	87
values[4]	95000	1			T4	25		T6	373		T21	25
values[5]	56600	1			T4	13		T6	197		T21	13
values[6]	34000	1			T4	9		T6	112		T21	9
values[7]	23300	1			T4	7		T6	46		T21	7
values[8]	16300	1			T4	2		T6	22		T21	2
values[9]	17700	1			T4	2		T6	30		T21	2
values[10]	13700	1			T4	2		T6	21		T21	2
values[11]	12000	1			T4	2		T6	28		T21	2
values[12]	11600	1			T6	34		T46	3		T47	3
values[13]	12900	1			T6	32		T46	2		T47	2
values[14]	12400	1			T6	16		T46	2		T47	2
values[15]	11100	1			T6	10		T46	2		T47	2
values[16]	11400	1			T6	12		T51	53		T70	18
values[17]	13900	1			T6	25		T51	46		T70	18
values[18]	11300	1			T6	25		T51	24		T70	18
values[19]	9700	1			T6	15		T51	31		T70	18
values[20]	8400	1			T6	14		T51	27		T70	18
values[21]	7600	1			T6	17		T51	19		T70	18
values[22]	7600	1			T6	18		T51	17		T70	18
values[23]	7900	1			T6	8		T51	26		T70	18
values[24]	9800	1			T6	12		T51	27		T70	19
values[25]	10400	1			T6	15		T51	29		T70	19
values[26]	9200	1			T6	17		T51	22		T70	20
values[27]	8000	1			T6	14		T51	15		T70	18
values[28]	8100	1			T6	13		T51	24		T70	18
values[29]	9300	1			T6	15		T51	22		T70	18
values[30]	9600	1			T6	25		T51	30		T70	19
values[31]	8800	1			T6	20		T51	31		T70	18
values[32]	9700	1			T6	20		T51	29		T70	18
values[33]	9000	1			T6	16		T51	32		T70	18
values[34]	7800	1			T6	17		T51	18		T70	18
values[35]	7500	1			T6	18		T51	15		T70	18
values[36]	8300	1			T6	17		T51	26		T70	19
values[37]	9300	1			T6	11		T51	39		T70	18
values[38]	8300	1			T6	14		T51	22		T70	18
values[39]	7500	1			T6	16		T51	15		T70	18
values[40]	7300	1			T6	10		T51	26		T70	18
values[41]	9400	1			T6	11		T51	39		T70	18
values[42]	8700	1			T6	7		T51	26		T70	19
values[43]	7700	1			T6	18		T51	15		T70	18
values[44]	10000	1			T6	18		T51	22		T70	18
values[45]	9400	1			T6	18		T51	17		T70	19
values[46]	7700	1			T6	19		T51	19		T70	18
values[47]	8200	1			T6	12		T51	25		T70	18
values[48]	7900	1			T6	13		T51	22		T70	18
values[49]	7100	1			T6	12		T51	19		T70	19
values[50]	6700	1			T6	20		T51	14		T70	18
values[51]	6800	1			T6	9		T51	21		T70	18
values[52]	8800	1			T6	17		T51	30		T70	18
values[53]	7800	1			T6	14		T51	30		T70	18
values[54]	7500	1			T6	16		T51	25		T70	18
values[55]	8400	1			T6	15		T51	24		T70	20
values[56]	5900	1			T6	8		T51	17		T70	18
values[57]	9700	1			T6	21		T51	32		T70	19
values[58]	7800	1			T6	12		T51	23		T70	18
values[59]	7700	1			T6	14		T51	26		T70	19
values[60]	8700	1			T6	14		T51	29		T70	18
values[61]	11200	1			T6	15		T51	30		T70	18
values[62]	26700	1			T6	46		T51	84		T70	18
values[63]	105700	1			T6	185		T51	322		T70	192
values[64]	414900	1			T6	215		T51	401		T70	3160

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	7051100	1			T4	6690		T5	2278		T6	2936
values[2]	1278000	1			T4	1132		T6	788		T21	1132
values[3]	203800	1			T4	130		T6	115		T21	130
values[4]	32900	1			T4	7		T6	7		T21	7
values[5]	16600	1			T6	1		T51	57		T58	11
values[6]	13500	1			T6	1		T51	76		T58	1
values[7]	11400	1			T6	1		T51	57		T58	1
values[8]	7200	1			T6	3		T51	34		T70	1
values[9]	5200	1			T6	2		T51	19		T70	1
values[10]	4300	1			T6	1		T51	25		T70	1
values[11]	3200	1			T6	1		T51	25		T70	1
values[12]	3400	1			T6	2		T51	26		T70	1
values[13]	3300	1			T6	2		T51	21		T70	1
values[14]	3600	1			T6	1		T51	21		T70	1
values[15]	3800	1			T6	1		T51	19		T70	1
values[16]	2800	1			T6	1		T51	14		T70	1
values[17]	1900	1			T6	2		T51	7		T70	1
values[18]	1900	1			T6	3		T51	3		T70	2
values[19]	2600	1			T6	2		T51	5		T70	1
values[20]	2500	1			T6	1		T51	6		T70	1
values[21]	1700	1			T6	1		T51	3		T70	1
values[22]	1800	1			T6	1		T51	2		T70	1
values[23]	1800	1			T6	2		T51	6		T70	1
values[24]	1100	1			T6	2		T51	3		T70	1
values[25]	800	1			T6	1		T51	3		T70	1
values[26]	1000	1			T6	2		T51	2		T70	1
values[27]	900	1			T6	2		T51	4		T70	1
values[28]	900	1			T6	1		T51	3		T70	1
values[29]	1300	1			T6	2		T51	5		T70	1
values[30]	1000	1			T6	3		T51	4		T70	1
values[31]	800	1			T6	3		T51	2		T70	1
values[32]	600	1			T6	1		T51	2		T70	1
values[33]	800	1			T6	1		T51	2		T70	1
values[34]	1300	1			T6	2		T51	3		T70	1
values[35]	1700	1			T6	5		T51	2		T70	1
values[36]	1000	1			T6	1		T51	2		T70	1
values[37]	1100	1			T6	1		T51	4		T70	1
values[38]	1100	1			T6	5		T51	2		T70	1
values[39]	700	1			T6	2		T51	2		T70	1
values[40]	1000	1			T6	2		T51	4		T70	1
values[41]	800	1			T6	1		T51	3		T70	1
values[42]	1200	1			T6	1		T51	2		T70	1
values[43]	900	1			T6	2		T51	2		T70	1
values[44]	800	1			T6	1		T51	2		T70	1
values[45]	800	1			T6	1		T51	2		T70	1
values[46]	900	1			T6	1		T51	5		T70	1
values[47]	800	1			T6	1		T51	3		T70	1
values[48]	900	1			T6	2		T51	2		T70	1
values[49]	600	1			T6	1		T51	2		T70	1
values[50]	700	1			T6	1		T51	2		T70	1
values[51]	800	1			T6	1		T51	2		T70	1
values[52]	1300	1			T6	2		T51	5		T70	1
values[53]	1900	1			T6	2		T51	9		T70	1
values[54]	1200	1			T6	1		T51	2		T70	1
values[55]	1000	1			T6	1		T51	3		T70	1
values[56]	900	1			T6	2		T51	2		T70	1
values[57]	1200	1			T6	3		T51	5		T70	1
values[58]	1100	1			T6	2		T51	3		T70	1
values[59]	800	1			T6	2		T51	2		T70	1
values[60]	1100	1			T6	2		T51	5		T70	1
values[61]	1300	1			T6	3		T51	5		T70	1
values[62]	3000	1			T6	8		T51	11		T70	1
values[63]	15000	1			T6	40		T51	61		T70	1
values[64]	70100	1			T6	125		T51	191		T70	213

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	918800	1			T4	733		T5	2327		T6	20
values[2]	4635400	1			T4	4404		T6	390		T21	4404
values[3]	1186000	1			T4	937		T6	932		T21	937
values[4]	208700	1			T4	100		T6	547		T21	100
values[5]	127900	1			T4	43		T6	425		T21	43
values[6]	78800	1			T4	14		T6	265		T21	14
values[7]	57900	1			T4	5		T6	128		T21	5
values[8]	44300	1			T4	3		T6	104		T21	3
values[9]	29600	1			T4	5		T6	82		T21	5
values[10]	24100	1			T4	6		T6	74		T21	6
values[11]	16100	1			T4	4		T6	29		T21	4
values[12]	15800	1			T4	2		T6	23		T21	2
values[13]	13400	1			T4	1		T6	19		T21	1
values[14]	10900	1			T4	4		T6	20		T21	4
values[15]	9100	1			T4	5		T6	23		T21	5
values[16]	7500	1			T4	5		T6	15		T21	5
values[17]	9400	1			T4	1		T6	19		T21	1
values[18]	10300	1			T6	25		T51	45		T70	18
values[19]	8800	1			T6	23		T51	29		T70	18
values[20]	8600	1			T6	24		T51	18		T70	18
values[21]	8800	1			T6	22		T51	19		T70	18
values[22]	6200	1			T6	13		T51	13		T70	18
values[23]	7600	1			T6	20		T51	14		T70	18
values[24]	5800	1			T6	13		T51	11		T70	18
values[25]	5900	1			T6	10		T51	17		T70	18
values[26]	8500	1			T6	16		T51	28		T70	18
values[27]	9000	1			T6	18		T51	27		T70	18
values[28]	8700	1			T6	18		T51	27		T70	18
values[29]	8100	1			T6	12		T51	34		T70	18
values[30]	7300	1			T6	11		T51	25		T70	19
values[31]	6900	1			T6	13		T51	19		T70	18
values[32]	8900	1			T6	19		T51	20		T70	18
values[33]	7600	1			T6	16		T51	17		T70	18
values[34]	7700	1			T6	11		T51	23		T70	18
values[35]	7800	1			T6	10		T51	20		T70	18
values[36]	7400	1			T6	10		T51	18		T70	18
values[37]	7900	1			T6	14		T51	23		T70	18
values[38]	9600	1			T6	15		T51	26		T70	18
values[39]	5800	1			T6	13		T51	12		T70	18
values[40]	7300	1			T6	20		T51	16		T70	18
values[41]	7700	1			T6	15		T51	22		T70	20
values[42]	7600	1			T6	8		T51	25		T70	18
values[43]	7400	1			T6	10		T51	26		T70	19
values[44]	7000	1			T6	10		T51	26		T70	18
values[45]	7300	1			T6	13		T51	21		T70	18
values[46]	8400	1			T6	22		T51	26		T70	18
values[47]	7700	1			T6	16		T51	23		T70	18
values[48]	7700	1			T6	10		T51	29		T70	19
values[49]	7500	1			T6	18		T51	23		T70	18
values[50]	9600	1			T6	32		T51	28		T70	18
values[51]	7800	1			T6	23		T51	21		T70	18
values[52]	8100	1			T6	26		T51	22		T70	18
values[53]	7700	1			T6	11		T51	26		T70	19
values[54]	7500	1			T6	19		T51	19		T70	19
values[55]	9400	1			T6	27		T51	22		T70	18
values[56]	6800	1			T6	13		T51	19		T70	18
values[57]	8800	1			T6	15		T51	34		T70	18
values[58]	7400	1			T6	18		T51	25		T70	19
values[59]	7500	1			T6	19		T51	25		T70	18
values[60]	6500	1			T6	11		T51	20		T70	19
values[61]	10100	1			T6	16		T51	31		T70	18
values[62]	25500	1			T6	51		T51	110		T70	18
values[63]	123400	1			T6	194		T51	324		T70	391
values[64]	421100	1			T6	296		T51	432		T70	3024