Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1346670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2300380

1

T1

62

T2

3958

T3

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2842746	1			T1	9		T2	5897		T3	9
values[0x0]	393200	1			T1	59		T2	2302		T3	59
values[0x1]	411104	1			T1	740		T2	2279		T3	740

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	995840	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2651210

1

T1

564

T2

5719

T3

564

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55792	1			T1	14		T2	195		T3	14
valid_sources[0x01]	56408	1			T1	14		T2	154		T3	14
valid_sources[0x02]	59622	1			T1	18		T2	149		T3	18
valid_sources[0x03]	58957	1			T1	20		T2	169		T3	20
valid_sources[0x04]	57165	1			T1	8		T2	138		T3	8
valid_sources[0x05]	56805	1			T1	15		T2	140		T3	15
valid_sources[0x06]	58516	1			T1	13		T2	183		T3	13
valid_sources[0x07]	53843	1			T1	10		T2	162		T3	10
valid_sources[0x08]	56134	1			T1	16		T2	150		T3	16
valid_sources[0x09]	57552	1			T1	20		T2	156		T3	20
valid_sources[0x0a]	55609	1			T1	21		T2	159		T3	21
valid_sources[0x0b]	56683	1			T1	10		T2	132		T3	10
valid_sources[0x0c]	54129	1			T1	12		T2	167		T3	12
valid_sources[0x0d]	55146	1			T1	15		T2	190		T3	15
valid_sources[0x0e]	57647	1			T1	15		T2	129		T3	15
valid_sources[0x0f]	59684	1			T1	13		T2	148		T3	13
valid_sources[0x10]	58032	1			T1	17		T2	216		T3	17
valid_sources[0x11]	59041	1			T1	12		T2	177		T3	12
valid_sources[0x12]	60463	1			T1	7		T2	220		T3	7
valid_sources[0x13]	57662	1			T1	17		T2	161		T3	17
valid_sources[0x14]	55576	1			T1	15		T2	148		T3	15
valid_sources[0x15]	54563	1			T1	6		T2	142		T3	6
valid_sources[0x16]	56357	1			T1	6		T2	142		T3	6
valid_sources[0x17]	57899	1			T1	8		T2	214		T3	8
valid_sources[0x18]	55488	1			T1	22		T2	142		T3	22
valid_sources[0x19]	60411	1			T1	11		T2	154		T3	11
valid_sources[0x1a]	57697	1			T1	14		T2	181		T3	14
valid_sources[0x1b]	56400	1			T1	17		T2	220		T3	17
valid_sources[0x1c]	55604	1			T1	7		T2	146		T3	7
valid_sources[0x1d]	52847	1			T1	10		T2	147		T3	10
valid_sources[0x1e]	57038	1			T1	10		T2	154		T3	10
valid_sources[0x1f]	57540	1			T1	7		T2	145		T3	7
valid_sources[0x20]	56166	1			T1	14		T2	124		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1643711

1

T1

5

T2

1444

T3

5

values[0x0]

all_enables

biggest_size

338435

1

T1

31

T2

1399

T3

31

values[0x1]

all_enables

biggest_size

318234

1

T1

26

T2

1115

T3

26

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4532800	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

709100

1

T4

880

T5

316

T6

560

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1760300	1			T4	2017		T5	730		T6	1371
values[0x0]	1703200	1			T4	2032		T5	745		T6	1387
values[0x1]	1778400	1			T4	2103		T5	745		T6	1368

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3492100	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1749800

1

T4

2072

T5

736

T6

1356

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	85800	1			T4	112		T5	26		T6	87
valid_sources[0x01]	93100	1			T4	61		T5	28		T6	63
valid_sources[0x02]	91100	1			T4	128		T5	18		T6	80
valid_sources[0x03]	85500	1			T4	85		T5	31		T6	110
valid_sources[0x04]	69800	1			T4	73		T5	31		T6	56
valid_sources[0x05]	79800	1			T4	126		T5	49		T6	58
valid_sources[0x06]	93600	1			T4	126		T5	30		T6	58
valid_sources[0x07]	54600	1			T4	84		T6	37		T21	84
valid_sources[0x08]	90500	1			T4	67		T5	26		T6	62
valid_sources[0x09]	62900	1			T4	57		T5	14		T6	46
valid_sources[0x0a]	77700	1			T4	43		T5	38		T6	79
valid_sources[0x0b]	91000	1			T4	146		T5	138		T6	60
valid_sources[0x0c]	75700	1			T4	37		T5	41		T6	46
valid_sources[0x0d]	81000	1			T4	30		T5	28		T6	75
valid_sources[0x0e]	87300	1			T4	96		T5	74		T6	68
valid_sources[0x0f]	63000	1			T4	84		T5	87		T6	67
valid_sources[0x10]	88000	1			T4	144		T5	48		T6	68
valid_sources[0x11]	65100	1			T4	117		T5	16		T6	51
valid_sources[0x12]	79600	1			T4	60		T6	58		T21	60
valid_sources[0x13]	93300	1			T4	168		T5	52		T6	54
valid_sources[0x14]	71000	1			T4	60		T5	30		T6	57
valid_sources[0x15]	75000	1			T4	137		T6	27		T21	137
valid_sources[0x16]	88800	1			T4	69		T5	33		T6	61
valid_sources[0x17]	69900	1			T4	37		T5	52		T6	72
valid_sources[0x18]	79900	1			T4	116		T5	33		T6	58
valid_sources[0x19]	91900	1			T4	79		T5	7		T6	61
valid_sources[0x1a]	81000	1			T4	99		T5	41		T6	69
valid_sources[0x1b]	83900	1			T4	151		T5	87		T6	62
valid_sources[0x1c]	86800	1			T4	168		T5	53		T6	57
valid_sources[0x1d]	88300	1			T4	74		T5	76		T6	77
valid_sources[0x1e]	86400	1			T4	137		T5	35		T6	58
valid_sources[0x1f]	78700	1			T4	81		T5	40		T6	84
valid_sources[0x20]	83000	1			T4	110		T5	35		T6	92

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79000

1

T4

89

T5

45

T6

67

values[0x0]

all_enables

biggest_size

545800

1

T4

698

T5

230

T6

430

values[0x1]

all_enables

biggest_size

84300

1

T4

93

T5

41

T6

63

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4699900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

779600

1

T4

1137

T5

341

T6

592

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1909700	1			T4	2681		T5	801		T6	1420
values[0x0]	1739500	1			T4	2620		T5	726		T6	1323
values[0x1]	1830300	1			T4	2651		T5	751		T6	1374

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3638000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1841500

1

T4

2659

T5

784

T6

1374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	85500	1			T4	108		T5	19		T6	42
valid_sources[0x01]	88300	1			T4	139		T5	19		T6	73
valid_sources[0x02]	84300	1			T4	165		T5	15		T6	45
valid_sources[0x03]	78400	1			T4	123		T5	36		T6	61
valid_sources[0x04]	82400	1			T4	111		T5	49		T6	45
valid_sources[0x05]	79900	1			T4	91		T5	31		T6	78
valid_sources[0x06]	88100	1			T4	124		T5	31		T6	58
valid_sources[0x07]	73400	1			T4	117		T6	52		T21	117
valid_sources[0x08]	87700	1			T4	178		T5	38		T6	77
valid_sources[0x09]	80000	1			T4	97		T5	13		T6	67
valid_sources[0x0a]	91500	1			T4	101		T5	39		T6	72
valid_sources[0x0b]	110500	1			T4	157		T5	148		T6	71
valid_sources[0x0c]	79800	1			T4	101		T5	40		T6	59
valid_sources[0x0d]	89100	1			T4	140		T5	34		T6	73
valid_sources[0x0e]	84900	1			T4	147		T5	57		T6	74
valid_sources[0x0f]	72500	1			T4	86		T5	69		T6	32
valid_sources[0x10]	82300	1			T4	114		T5	38		T6	55
valid_sources[0x11]	87100	1			T4	147		T5	29		T6	49
valid_sources[0x12]	77500	1			T4	81		T6	65		T21	81
valid_sources[0x13]	87400	1			T4	78		T5	53		T6	68
valid_sources[0x14]	77700	1			T4	118		T5	21		T6	70
valid_sources[0x15]	75400	1			T4	119		T6	57		T21	119
valid_sources[0x16]	77200	1			T4	161		T5	40		T6	78
valid_sources[0x17]	85000	1			T4	139		T5	35		T6	47
valid_sources[0x18]	93700	1			T4	138		T5	44		T6	72
valid_sources[0x19]	70300	1			T4	102		T5	16		T6	37
valid_sources[0x1a]	88700	1			T4	109		T5	35		T6	81
valid_sources[0x1b]	74500	1			T4	101		T5	77		T6	68
valid_sources[0x1c]	86600	1			T4	158		T5	54		T6	61
valid_sources[0x1d]	102300	1			T4	154		T5	71		T6	70
valid_sources[0x1e]	89700	1			T4	101		T5	29		T6	63
valid_sources[0x1f]	84200	1			T4	111		T5	56		T6	68
valid_sources[0x20]	88700	1			T4	86		T5	45		T6	77

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88700

1

T4

114

T5

45

T6

66

values[0x0]

all_enables

biggest_size

606600

1

T4

906

T5

258

T6

460

values[0x1]

all_enables

biggest_size

84300

1

T4

117

T5

38

T6

66

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4547000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

720600

1

T4

818

T5

336

T6

591

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1797600	1			T4	2066		T5	775		T6	1473
values[0x0]	1681800	1			T4	2044		T5	775		T6	1440
values[0x1]	1788200	1			T4	2134		T5	777		T6	1461

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3513600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1754000

1

T4

2016

T5

779

T6

1451

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	77300	1			T4	103		T5	19		T6	75
valid_sources[0x01]	86600	1			T4	103		T5	11		T6	72
valid_sources[0x02]	79700	1			T4	125		T5	10		T6	82
valid_sources[0x03]	89000	1			T4	109		T5	22		T6	73
valid_sources[0x04]	82900	1			T4	89		T5	30		T6	58
valid_sources[0x05]	79600	1			T4	101		T5	52		T6	55
valid_sources[0x06]	87500	1			T4	93		T5	34		T6	67
valid_sources[0x07]	82500	1			T4	99		T6	83		T21	99
valid_sources[0x08]	83900	1			T4	91		T5	41		T6	67
valid_sources[0x09]	81500	1			T4	87		T5	10		T6	57
valid_sources[0x0a]	83400	1			T4	90		T5	40		T6	57
valid_sources[0x0b]	87600	1			T4	123		T5	120		T6	42
valid_sources[0x0c]	86400	1			T4	85		T5	63		T6	65
valid_sources[0x0d]	79900	1			T4	86		T5	44		T6	72
valid_sources[0x0e]	84200	1			T4	74		T5	52		T6	72
valid_sources[0x0f]	79000	1			T4	79		T5	78		T6	59
valid_sources[0x10]	76500	1			T4	89		T5	49		T6	75
valid_sources[0x11]	72700	1			T4	100		T5	17		T6	65
valid_sources[0x12]	77200	1			T4	82		T6	65		T21	82
valid_sources[0x13]	89000	1			T4	94		T5	63		T6	67
valid_sources[0x14]	78700	1			T4	81		T5	30		T6	63
valid_sources[0x15]	77100	1			T4	108		T6	76		T21	108
valid_sources[0x16]	76400	1			T4	77		T5	44		T6	67
valid_sources[0x17]	83000	1			T4	80		T5	50		T6	80
valid_sources[0x18]	80900	1			T4	111		T5	35		T6	59
valid_sources[0x19]	84600	1			T4	108		T5	17		T6	53
valid_sources[0x1a]	84000	1			T4	82		T5	40		T6	68
valid_sources[0x1b]	82800	1			T4	105		T5	63		T6	75
valid_sources[0x1c]	85700	1			T4	121		T5	79		T6	68
valid_sources[0x1d]	83100	1			T4	89		T5	82		T6	71
valid_sources[0x1e]	77900	1			T4	70		T5	32		T6	48
valid_sources[0x1f]	81900	1			T4	94		T5	45		T6	80
valid_sources[0x20]	81900	1			T4	94		T5	55		T6	81

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73700

1

T4

93

T5

29

T6

48

values[0x0]

all_enables

biggest_size

574000

1

T4

640

T5

275

T6

493

values[0x1]

all_enables

biggest_size

72900

1

T4

85

T5

32

T6

50