Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.95			96.95

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c2	93.25			93.25
tb.dut.top_earlgrey.u_i2c1	93.87			93.87
tb.dut.top_earlgrey.u_i2c0	95.06			95.06

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.25			93.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.25			93.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.70	68.10		83.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.87			93.87

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.87			93.87

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.70	68.10		83.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.06			95.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.06			95.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.70	68.10		83.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	43	89.58
Total Bits	328	318	96.95
Total Bits 0->1	164	159	96.95
Total Bits 1->0	164	159	96.95

Ports	48	43	89.58
Port Bits	328	318	96.95
Port Bits 0->1	164	159	96.95
Port Bits 1->0	164	159	96.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
cio_scl_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
cio_sda_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T25,T26,T28	Yes	T25,T26,T28	OUTPUT
intr_rx_threshold_o	No	No		No		OUTPUT
intr_fmt_overflow_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_rx_overflow_o	No	No		No		OUTPUT
intr_nak_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_scl_interference_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_sda_interference_o	Yes	Yes	T22,T7,T23	Yes	T22,T7,T23	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_sda_unstable_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_cmd_complete_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_tx_stretch_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_tx_overflow_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_acq_full_o	No	No		No		OUTPUT
intr_unexp_stop_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_host_timeout_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	37	77.08
Total Bits	326	304	93.25
Total Bits 0->1	163	152	93.25
Total Bits 1->0	163	152	93.25

Ports	48	37	77.08
Port Bits	326	304	93.25
Port Bits 0->1	163	152	93.25
Port Bits 1->0	163	152	93.25

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
cio_scl_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
cio_sda_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T25,T26,T28	Yes	T25,T26,T28	OUTPUT
intr_rx_threshold_o	No	No		No		OUTPUT
intr_fmt_overflow_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_rx_overflow_o	No	No		No		OUTPUT
intr_nak_o	No	No		No		OUTPUT
intr_scl_interference_o	No	No		No		OUTPUT
intr_sda_interference_o	Yes	Yes	T22,T23,T25	Yes	T22,T23,T25	OUTPUT
intr_stretch_timeout_o	No	No		No		OUTPUT
intr_sda_unstable_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_cmd_complete_o	No	No		No		OUTPUT
intr_tx_stretch_o	No	No		No		OUTPUT
intr_tx_overflow_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_acq_full_o	No	No		No		OUTPUT
intr_unexp_stop_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_host_timeout_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	38	79.17
Total Bits	326	306	93.87
Total Bits 0->1	163	153	93.87
Total Bits 1->0	163	153	93.87

Ports	48	38	79.17
Port Bits	326	306	93.87
Port Bits 0->1	163	153	93.87
Port Bits 1->0	163	153	93.87

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
cio_scl_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T22,T7,T23	Yes	T22,T7,T23	OUTPUT
cio_sda_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T22,T23,T25	Yes	T22,T23,T25	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T25,T26,T28	Yes	T25,T26,T28	OUTPUT
intr_rx_threshold_o	No	No		No		OUTPUT
intr_fmt_overflow_o	No	No		No		OUTPUT
intr_rx_overflow_o	No	No		No		OUTPUT
intr_nak_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_scl_interference_o	No	No		No		OUTPUT
intr_sda_interference_o	Yes	Yes	T7,T27,T25	Yes	T7,T27,T25	OUTPUT
intr_stretch_timeout_o	No	No		No		OUTPUT
intr_sda_unstable_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_cmd_complete_o	No	No		No		OUTPUT
intr_tx_stretch_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_tx_overflow_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_acq_full_o	No	No		No		OUTPUT
intr_unexp_stop_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_host_timeout_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	324	308	95.06
Total Bits 0->1	162	154	95.06
Total Bits 1->0	162	154	95.06

Ports	48	40	83.33
Port Bits	324	308	95.06
Port Bits 0->1	162	154	95.06
Port Bits 1->0	162	154	95.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
cio_scl_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
cio_sda_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T25,T26,T28	Yes	T25,T26,T28	OUTPUT
intr_rx_threshold_o	No	No		No		OUTPUT
intr_fmt_overflow_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_rx_overflow_o	No	No		No		OUTPUT
intr_nak_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_scl_interference_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_sda_interference_o	Yes	Yes	T25,T26,T28	Yes	T25,T26,T28	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_sda_unstable_o	No	No		No		OUTPUT
intr_cmd_complete_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_tx_stretch_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_tx_overflow_o	No	No		No		OUTPUT
intr_acq_full_o	No	No		No		OUTPUT
intr_unexp_stop_o	No	No		No		OUTPUT
intr_host_timeout_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

*Tests covering at least one bit in the range