Unified Coverage Report :: Module Instance :: tb.dut.u_ast.u_reg.u_rsp_intg_gen

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	99.16	91.61			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.47	100.00	93.88			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00	56.67	55.83			87.50	0.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	0.00	0.00
gen_rsp_intg.u_rsp_gen	0.00	0.00

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	0.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
57.68	55.26	32.61			42.86	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	99.94	92.11			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.37	100.00	93.48			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1927	1927	0	0
PayLoadWidthCheck	1927	1927	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1927	1927	0	0
PayLoadWidthCheck	1927	1927	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	25	1	0	0.00
ALWAYS	47	3	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
47	0	1
48	0	1
49	0	1
53	0	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	16	16	0	0
PayLoadWidthCheck	16	16	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	0	1
47	0	1
48	0	1
49	0	1
53	0	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	16	16	0	0
PayLoadWidthCheck	16	16	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1927	1927	0	0
PayLoadWidthCheck	1927	1927	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
43	0	1
47	1	1
48	1	1
49	1	1
53	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1927	1927	0	0
PayLoadWidthCheck	1927	1927	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0