Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : ast
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.25 66.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_ast_0.1/rtl/ast.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ast 73.44 73.44


Module Instance : tb.dut.u_ast

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.44 73.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.44 73.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.58 84.21 50.00 95.52 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : ast
TotalCoveredPercent
Totals 224 151 67.41
Total Bits 960 636 66.25
Total Bits 0->1 480 321 66.88
Total Bits 1->0 480 315 65.62

Ports 224 151 67.41
Port Bits 960 636 66.25
Port Bits 0->1 480 321 66.88
Port Bits 1->0 480 315 65.62

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[9:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[18:10] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_init_done_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
clk_ast_adc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_adc_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_alert_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_alert_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_es_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_es_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_rng_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_rng_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_tlul_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_tlul_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_usb_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_ext_i Yes Yes T13,T14,T15 Yes T13,T14,T15 INPUT
por_ni Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div2_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_timers Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_secure Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_secure Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div2_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_usb_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_otbn Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_kmac Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_hmac Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_aes Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c2_n[0] No No No INPUT
sns_rsts_i.rst_i2c2_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_i2c1_n[0] No No No INPUT
sns_rsts_i.rst_i2c1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_i2c0_n[0] No No No INPUT
sns_rsts_i.rst_i2c0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_usb_aon_n[0] No No No INPUT
sns_rsts_i.rst_usb_aon_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_usb_n[0] No No No INPUT
sns_rsts_i.rst_usb_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_spi_host1_n[0] No No No INPUT
sns_rsts_i.rst_spi_host1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_spi_host0_n[0] No No No INPUT
sns_rsts_i.rst_spi_host0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_spi_device_n[0] No No No INPUT
sns_rsts_i.rst_spi_device_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_sys_io_div4_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_sys_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_sys_n[0] No No No INPUT
sns_rsts_i.rst_sys_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_usb_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_div4_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_div2_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_aon_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_aon_n[1] No No No INPUT
sns_rsts_i.rst_lc_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_por_usb_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_usb_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div4_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div2_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div2_n[1] No No No INPUT
sns_rsts_i.rst_por_io_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_n[1] No No No INPUT
sns_rsts_i.rst_por_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_n[1] No No No INPUT
sns_rsts_i.rst_por_aon_n[1:0] Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
sns_spi_ext_clk_i Yes Yes T13,T14,T15 Yes T13,T14,T15 INPUT
vcc_supp_i Unreachable Unreachable Unreachable INPUT
vcaon_supp_i Unreachable Unreachable Unreachable INPUT
vcmain_supp_i Unreachable Unreachable Unreachable INPUT
vioa_supp_i Unreachable Unreachable Unreachable INPUT
viob_supp_i Unreachable Unreachable Unreachable INPUT
ast_pwst_o.io_pok[1:0] No No Yes T4,T5,T6 OUTPUT
ast_pwst_o.main_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
ast_pwst_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_o.aon_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.io_pok[1:0] No No Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.main_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.aon_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
main_pd_ni No No No INPUT
main_env_iso_en_i Yes Yes T4,T5,T6 Yes T4,T21,T46 INPUT
flash_power_down_h_o No Yes T4,T5,T6 No OUTPUT
flash_power_ready_h_o No No Yes T4,T5,T6 OUTPUT
otp_power_seq_i[1:0] No No No INPUT
otp_power_seq_h_o[0] No No No OUTPUT
otp_power_seq_h_o[1] No Yes T4,T5,T6 No OUTPUT
clk_src_sys_en_i Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
clk_src_sys_jen_i[0] Yes Yes *T25,*T26,*T28 Yes T25,T26,T28 INPUT
clk_src_sys_jen_i[2:1] No No No INPUT
clk_src_sys_jen_i[3] Yes Yes T25,T26,T28 Yes T25,T26,T28 INPUT
clk_src_sys_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_sys_val_o Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
clk_src_aon_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_aon_val_o No No Yes T4,T5,T6 OUTPUT
clk_src_io_en_i Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
clk_src_io_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_io_val_o Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
clk_src_io_48m_o[3:0] No No No OUTPUT
usb_ref_pulse_i No No No INPUT
usb_ref_val_i No No No INPUT
clk_src_usb_en_i Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
clk_src_usb_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_usb_val_o Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
usb_io_pu_cal_o[19:0] Unreachable Unreachable Unreachable OUTPUT
adc_pd_i Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
adc_a0_ai No No No INPUT
adc_a1_ai No No No INPUT
adc_chnsel_i[1:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
adc_d_o[9:0] No No No OUTPUT
adc_d_val_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
rng_en_i No No No INPUT
rng_fips_i No No No INPUT
rng_val_o No No No OUTPUT
rng_b_o[3:0] No No No OUTPUT
entropy_rsp_i.edn_bus[31:0] No No No INPUT
entropy_rsp_i.edn_fips No No No INPUT
entropy_rsp_i.edn_ack No No No INPUT
entropy_req_o.edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rsp_i.alerts_trig[0].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[0].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[1].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[1].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[2].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[2].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[3].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[3].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[4].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[4].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[5].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[5].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[6].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[6].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[7].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[7].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[8].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[8].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[9].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[9].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[10].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[10].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[0].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[0].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[1].n No No No INPUT
alert_rsp_i.alerts_ack[1].p No No No INPUT
alert_rsp_i.alerts_ack[2].n No No No INPUT
alert_rsp_i.alerts_ack[2].p No No No INPUT
alert_rsp_i.alerts_ack[3].n No No No INPUT
alert_rsp_i.alerts_ack[3].p No No No INPUT
alert_rsp_i.alerts_ack[4].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[4].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[5].n No No No INPUT
alert_rsp_i.alerts_ack[5].p No No No INPUT
alert_rsp_i.alerts_ack[6].n No No No INPUT
alert_rsp_i.alerts_ack[6].p No No No INPUT
alert_rsp_i.alerts_ack[7].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[7].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[8].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[8].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[9].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[9].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[10].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[10].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_req_o.alerts[0].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[0].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[1].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[1].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[2].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[2].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[3].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[3].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[4].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[4].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[5].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[5].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[6].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[6].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[7].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[7].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[8].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[8].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[9].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[9].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[10].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[10].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
dft_strap_test_i.straps[1:0] No No No INPUT
dft_strap_test_i.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
lc_dft_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
fla_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otp_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otm_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
usb_obs_i Yes Yes T2,T8,T9 Yes T2,T8,T9 INPUT
obs_ctrl_o.obmen[3:0] No No No OUTPUT
obs_ctrl_o.obmsl[3:0] No No No OUTPUT
obs_ctrl_o.obgsl[3:0] No No No OUTPUT
padmux2ast_i[7:0] Yes Yes T13,T14,T15 Yes T13,T14,T15 INPUT
padmux2ast_i[8] No No No INPUT
ast2padmux_o[8:0] Unreachable Unreachable Unreachable OUTPUT
ast2pad_t0_ao Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
ast2pad_t1_ao Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
ext_freq_is_96m_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
all_clk_byp_req_i[3:0] No No No INPUT
all_clk_byp_ack_o[3:0] No No No OUTPUT
io_clk_byp_req_i[3:0] No No No INPUT
io_clk_byp_ack_o[3:0] No No No OUTPUT
flash_bist_en_o[3:0] Unreachable Unreachable Unreachable OUTPUT
dpram_rmf_o.marg_b[3:0] No No No OUTPUT
dpram_rmf_o.marg_en_b No No No OUTPUT
dpram_rmf_o.marg_a[3:0] No No No OUTPUT
dpram_rmf_o.marg_en_a No No No OUTPUT
dpram_rml_o.marg_b[3:0] No No No OUTPUT
dpram_rml_o.marg_en_b No No No OUTPUT
dpram_rml_o.marg_a[3:0] No No No OUTPUT
dpram_rml_o.marg_en_a No No No OUTPUT
spram_rm_o.marg[3:0] No No No OUTPUT
spram_rm_o.marg_en No No No OUTPUT
sprgf_rm_o.marg[3:0] No No No OUTPUT
sprgf_rm_o.marg_en No No No OUTPUT
sprom_rm_o.marg[3:0] No No No OUTPUT
sprom_rm_o.marg_en No No No OUTPUT
dft_scan_md_o[3:0] Unreachable Unreachable Unreachable OUTPUT
scan_shift_en_o Unreachable Unreachable Unreachable OUTPUT
scan_reset_no Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ast
TotalCoveredPercent
Totals 207 151 72.95
Total Bits 866 636 73.44
Total Bits 0->1 433 321 74.13
Total Bits 1->0 433 315 72.75

Ports 207 151 72.95
Port Bits 866 636 73.44
Port Bits 0->1 433 321 74.13
Port Bits 1->0 433 315 72.75

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[9:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[18:10] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[5:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_init_done_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
clk_ast_adc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ast_adc_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_alert_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_alert_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_es_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_es_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_rng_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_rng_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_tlul_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_tlul_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ast_usb_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_ast_ext_i Yes Yes T13,T14,T15 Yes T13,T14,T15 INPUT
por_ni Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div2_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_peri Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_timers Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_secure Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_secure Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div2_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_usb_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_io_div4_infra Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_otbn Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_kmac Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_hmac Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_main_aes Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_clks_i.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_clks_i.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_i2c2_n[0] No No No INPUT
sns_rsts_i.rst_i2c2_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_i2c1_n[0] No No No INPUT
sns_rsts_i.rst_i2c1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_i2c0_n[0] No No No INPUT
sns_rsts_i.rst_i2c0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_usb_aon_n[0] No No No INPUT
sns_rsts_i.rst_usb_aon_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_usb_n[0] No No No INPUT
sns_rsts_i.rst_usb_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_spi_host1_n[0] No No No INPUT
sns_rsts_i.rst_spi_host1_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_spi_host0_n[0] No No No INPUT
sns_rsts_i.rst_spi_host0_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_spi_device_n[0] No No No INPUT
sns_rsts_i.rst_spi_device_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_sys_io_div4_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_sys_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_sys_n[0] No No No INPUT
sns_rsts_i.rst_sys_n[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_usb_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_div4_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_div2_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_io_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_aon_n[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_aon_n[1] No No No INPUT
sns_rsts_i.rst_lc_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_lc_shadowed_n[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sns_rsts_i.rst_por_usb_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_usb_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div4_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div4_n[1] No No No INPUT
sns_rsts_i.rst_por_io_div2_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_div2_n[1] No No No INPUT
sns_rsts_i.rst_por_io_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_io_n[1] No No No INPUT
sns_rsts_i.rst_por_n[0] Yes Yes *T4,*T21,*T46 Yes T4,T5,T6 INPUT
sns_rsts_i.rst_por_n[1] No No No INPUT
sns_rsts_i.rst_por_aon_n[1:0] Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
sns_spi_ext_clk_i Yes Yes T13,T14,T15 Yes T13,T14,T15 INPUT
vcc_supp_i Unreachable Unreachable Unreachable INPUT
vcaon_supp_i Unreachable Unreachable Unreachable INPUT
vcmain_supp_i Unreachable Unreachable Unreachable INPUT
vioa_supp_i Unreachable Unreachable Unreachable INPUT
viob_supp_i Unreachable Unreachable Unreachable INPUT
ast_pwst_o.io_pok[1:0] No No Yes T4,T5,T6 OUTPUT
ast_pwst_o.main_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
ast_pwst_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_o.aon_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.io_pok[1:0] No No Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.main_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.vcc_pok No No Yes T4,T5,T6 OUTPUT
ast_pwst_h_o.aon_pok Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
main_pd_ni No No No INPUT
main_env_iso_en_i Yes Yes T4,T5,T6 Yes T4,T21,T46 INPUT
flash_power_down_h_o No Yes T4,T5,T6 No OUTPUT
flash_power_ready_h_o No No Yes T4,T5,T6 OUTPUT
otp_power_seq_i[1:0] No No No INPUT
otp_power_seq_h_o[0] No No No OUTPUT
otp_power_seq_h_o[1] No Yes T4,T5,T6 No OUTPUT
clk_src_sys_en_i Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
clk_src_sys_jen_i[0] Yes Yes *T25,*T26,*T28 Yes T25,T26,T28 INPUT
clk_src_sys_jen_i[2:1] No No No INPUT
clk_src_sys_jen_i[3] Yes Yes T25,T26,T28 Yes T25,T26,T28 INPUT
clk_src_sys_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_sys_val_o Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
clk_src_aon_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_aon_val_o No No Yes T4,T5,T6 OUTPUT
clk_src_io_en_i Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
clk_src_io_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_io_val_o Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
clk_src_io_48m_o[3:0] No No No OUTPUT
usb_ref_pulse_i No No No INPUT
usb_ref_val_i No No No INPUT
clk_src_usb_en_i Yes Yes T4,T21,T46 Yes T4,T5,T6 INPUT
clk_src_usb_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clk_src_usb_val_o Yes Yes T4,T21,T46 Yes T4,T5,T6 OUTPUT
usb_io_pu_cal_o[19:0] Unreachable Unreachable Unreachable OUTPUT
adc_pd_i Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
adc_a0_ai No No No INPUT
adc_a1_ai No No No INPUT
adc_chnsel_i[1:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
adc_d_o[9:0] No No No OUTPUT
adc_d_val_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
rng_en_i No No No INPUT
rng_fips_i No No No INPUT
rng_val_o No No No OUTPUT
rng_b_o[3:0] No No No OUTPUT
entropy_rsp_i.edn_bus[31:0] No No No INPUT
entropy_rsp_i.edn_fips No No No INPUT
entropy_rsp_i.edn_ack No No No INPUT
entropy_req_o.edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rsp_i.alerts_trig[0].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[0].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[1].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[1].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[2].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[2].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[3].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[3].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[4].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[4].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[5].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[5].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[6].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[6].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[7].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[7].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[8].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[8].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[9].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[9].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[10].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_trig[10].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[0].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[0].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[1].n No No No INPUT
alert_rsp_i.alerts_ack[1].p No No No INPUT
alert_rsp_i.alerts_ack[2].n No No No INPUT
alert_rsp_i.alerts_ack[2].p No No No INPUT
alert_rsp_i.alerts_ack[3].n No No No INPUT
alert_rsp_i.alerts_ack[3].p No No No INPUT
alert_rsp_i.alerts_ack[4].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[4].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[5].n No No No INPUT
alert_rsp_i.alerts_ack[5].p No No No INPUT
alert_rsp_i.alerts_ack[6].n No No No INPUT
alert_rsp_i.alerts_ack[6].p No No No INPUT
alert_rsp_i.alerts_ack[7].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[7].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[8].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[8].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[9].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[9].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[10].n Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_rsp_i.alerts_ack[10].p Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
alert_req_o.alerts[0].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[0].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[1].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[1].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[2].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[2].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[3].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[3].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[4].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[4].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[5].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[5].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[6].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[6].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[7].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[7].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[8].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[8].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[9].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[9].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[10].n Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_req_o.alerts[10].p Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
dft_strap_test_i.straps[1:0] No No No INPUT
dft_strap_test_i.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
lc_dft_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
fla_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otp_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
otm_obs_i[7:0] Unreachable Unreachable Unreachable INPUT
usb_obs_i Yes Yes T2,T8,T9 Yes T2,T8,T9 INPUT
obs_ctrl_o.obmen[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_o.obmsl[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_o.obgsl[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
padmux2ast_i[7:0] Yes Yes T13,T14,T15 Yes T13,T14,T15 INPUT
padmux2ast_i[8] No No No INPUT
ast2padmux_o[8:0] Unreachable Unreachable Unreachable OUTPUT
ast2pad_t0_ao Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
ast2pad_t1_ao Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
ext_freq_is_96m_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
all_clk_byp_req_i[3:0] No No No INPUT
all_clk_byp_ack_o[3:0] No No No OUTPUT
io_clk_byp_req_i[3:0] No No No INPUT
io_clk_byp_ack_o[3:0] No No No OUTPUT
flash_bist_en_o[3:0] Unreachable Unreachable Unreachable OUTPUT
dpram_rmf_o.marg_b[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rmf_o.marg_en_b[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rmf_o.marg_a[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rmf_o.marg_en_a[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.marg_b[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.marg_en_b[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.marg_a[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dpram_rml_o.marg_en_a[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spram_rm_o.marg[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spram_rm_o.marg_en[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprgf_rm_o.marg[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprgf_rm_o.marg_en[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprom_rm_o.marg[3:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sprom_rm_o.marg_en[0:0] Excluded Excluded Excluded OUTPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
dft_scan_md_o[3:0] Unreachable Unreachable Unreachable OUTPUT
scan_shift_en_o Unreachable Unreachable Unreachable OUTPUT
scan_reset_no Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%