Unified Coverage Report :: Module :: pinmux

Module : pinmux

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.36	71.57	57.04	62.95		44.47	80.77

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon	73.88	91.65	57.04	95.46		44.47	80.77

Line Coverage for Module : pinmux

	Line No.	Total	Covered	Percent
TOTAL		1150	823	71.57
CONT_ASSIGN	128	1	1	100.00
ALWAYS	157	41	41	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	0	0.00
CONT_ASSIGN	246	1	0	0.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
ALWAYS	291	3	3	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
ALWAYS	409	15	11	73.33
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	0	0.00
CONT_ASSIGN	501	1	0	0.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	572	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
128	1	1
157	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
166	1	1
167	1	1
			MISSING_ELSE
169	1	1
170	1	1
			MISSING_ELSE
172	1	1
173	1	1
			MISSING_ELSE
175	1	1
176	1	1
			MISSING_ELSE
178	1	1
179	1	1
			MISSING_ELSE
181	1	1
182	1	1
			MISSING_ELSE
184	1	1
185	1	1
			MISSING_ELSE
187	1	1
188	1	1
			MISSING_ELSE
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
196	1	1
197	1	1
			MISSING_ELSE
199	1	1
200	1	1
			MISSING_ELSE
202	1	1
203	1	1
			MISSING_ELSE
205	1	1
206	1	1
			MISSING_ELSE
208	1	1
209	1	1
			MISSING_ELSE
211	1	1
212	1	1
			MISSING_ELSE
214	1	1
215	1	1
			MISSING_ELSE
217	1	1
218	1	1
			MISSING_ELSE
238	16	16
239	14	16
240	0	16
241	0	16
242	0	16
243	0	16
244	16	16
245	16	16
246	14	16
247	16	16
260	47	47
261	47	47
262	0	47
263	0	47
264	0	47
265	0	47
266	47	47
267	47	47
268	47	47
269	47	47
291	1	1
292	1	1
294	1	1
299	1	1
406	1	1
409	1	1
410	1	1
411	1	1
412	1	1
413	1	1
414	1	1
416	1	1
419	1	1
420	1	1
421	0	1
422	0	1
			MISSING_ELSE
427	1	1
428	1	1
429	0	1
430	0	1
			MISSING_ELSE
446	1	1
450	57	57
460	1	1
461	1	1
465	47	47
469	47	47
478	47	47
482	47	47
487	47	47
489	0	47
497	1	1
501	14	16
505	16	16
514	16	16
518	16	16
523	16	16
525	7	16
537	1	1
542	1	1
547	8	8
568	0	8
572	0	1

---

Cond Coverage for Module : pinmux

	Total	Covered	Percent
Conditions	1981	1130	57.04
Logical	1981	1130	57.04
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
128-478	53.91
478	61.73
478-482	59.29
482-505	50.61
505-518	58.70
518-547	64.58

---

Toggle Coverage for Module : pinmux

	Total	Covered	Percent
Totals	650	305	46.92
Total Bits	2942	1852	62.95
Total Bits 0->1	1471	926	62.95
Total Bits 1->0	1471	926	62.95

Ports	650	305	46.92
Port Bits	2942	1852	62.95
Port Bits 0->1	1471	926	62.95
Port Bits 1->0	1471	926	62.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_sys_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pin_wkup_req_o	No	No		No		OUTPUT
usb_wkup_req_o	No	No		No		OUTPUT
sleep_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
strap_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
strap_en_override_i	No	No		No		INPUT
lc_dft_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_check_byp_en_i[3:0]	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
pinmux_hw_debug_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dft_strap_test_o.straps[1:0]	No	No		No		OUTPUT
dft_strap_test_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
lc_jtag_o.tdi	No	No		No		OUTPUT
lc_jtag_o.trst_n	No	No		No		OUTPUT
lc_jtag_o.tms	No	No		No		OUTPUT
lc_jtag_o.tck	No	No		No		OUTPUT
lc_jtag_i.tdo_oe	No	No		No		INPUT
lc_jtag_i.tdo	No	No		No		INPUT
rv_jtag_o.tdi	Yes	Yes	T19,T20,T16	Yes	T19,T20,T16	OUTPUT
rv_jtag_o.trst_n	Yes	Yes	T19,T20,T16	Yes	T19,T20,T16	OUTPUT
rv_jtag_o.tms	Yes	Yes	T19,T20,T16	Yes	T19,T20,T16	OUTPUT
rv_jtag_o.tck	Yes	Yes	T19,T20,T16	Yes	T19,T20,T16	OUTPUT
rv_jtag_i.tdo_oe	Yes	Yes	T19,T20,T16	Yes	T19,T20,T16	INPUT
rv_jtag_i.tdo	Yes	Yes	T19,T20,T16	Yes	T19,T20,T16	INPUT
dft_jtag_o.tdi	No	No		No		OUTPUT
dft_jtag_o.trst_n	No	No		No		OUTPUT
dft_jtag_o.tms	No	No		No		OUTPUT
dft_jtag_o.tck	No	No		No		OUTPUT
dft_jtag_i.tdo_oe	No	No		No		INPUT
dft_jtag_i.tdo	No	No		No		INPUT
usbdev_dppullup_en_i	No	No		No		INPUT
usbdev_dnpullup_en_i	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
usb_dppullup_en_o	No	No		No		OUTPUT
usb_dnpullup_en_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
usbdev_suspend_req_i	No	No		No		INPUT
usbdev_wake_ack_i	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
usbdev_bus_reset_o	No	No		No		OUTPUT
usbdev_sense_lost_o	No	No		No		OUTPUT
usbdev_wake_detect_active_o	No	No		No		OUTPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[11:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
periph_to_mio_i[74:0]	Yes	Yes	T25,T26,T10	Yes	T25,T26,T10	INPUT
periph_to_mio_oe_i[74:0]	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
mio_to_periph_o[56:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
periph_to_dio_i[11:0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	INPUT
periph_to_dio_i[13:12]	No	No		No		INPUT
periph_to_dio_i[15:14]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
periph_to_dio_oe_i[15:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
dio_to_periph_o[15:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[0].keep_en	No	No		No		OUTPUT
mio_attr_o[0].schmitt_en	No	No		No		OUTPUT
mio_attr_o[0].od_en	No	No		No		OUTPUT
mio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[0].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[1].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[1].keep_en	No	No		No		OUTPUT
mio_attr_o[1].schmitt_en	No	No		No		OUTPUT
mio_attr_o[1].od_en	No	No		No		OUTPUT
mio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[1].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[2].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[2].keep_en	No	No		No		OUTPUT
mio_attr_o[2].schmitt_en	No	No		No		OUTPUT
mio_attr_o[2].od_en	No	No		No		OUTPUT
mio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[2].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[3].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[3].keep_en	No	No		No		OUTPUT
mio_attr_o[3].schmitt_en	No	No		No		OUTPUT
mio_attr_o[3].od_en	No	No		No		OUTPUT
mio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[3].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[4].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[4].keep_en	No	No		No		OUTPUT
mio_attr_o[4].schmitt_en	No	No		No		OUTPUT
mio_attr_o[4].od_en	No	No		No		OUTPUT
mio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[4].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[5].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[5].keep_en	No	No		No		OUTPUT
mio_attr_o[5].schmitt_en	No	No		No		OUTPUT
mio_attr_o[5].od_en	No	No		No		OUTPUT
mio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[5].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[6].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[6].keep_en	No	No		No		OUTPUT
mio_attr_o[6].schmitt_en	No	No		No		OUTPUT
mio_attr_o[6].od_en	No	No		No		OUTPUT
mio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[6].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[7].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[7].keep_en	No	No		No		OUTPUT
mio_attr_o[7].schmitt_en	No	No		No		OUTPUT
mio_attr_o[7].od_en	No	No		No		OUTPUT
mio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[7].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[8].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[8].keep_en	No	No		No		OUTPUT
mio_attr_o[8].schmitt_en	No	No		No		OUTPUT
mio_attr_o[8].od_en	No	No		No		OUTPUT
mio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[8].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[9].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[9].keep_en	No	No		No		OUTPUT
mio_attr_o[9].schmitt_en	No	No		No		OUTPUT
mio_attr_o[9].od_en	No	No		No		OUTPUT
mio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[9].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[10].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[10].keep_en	No	No		No		OUTPUT
mio_attr_o[10].schmitt_en	No	No		No		OUTPUT
mio_attr_o[10].od_en	No	No		No		OUTPUT
mio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[10].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[11].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[11].keep_en	No	No		No		OUTPUT
mio_attr_o[11].schmitt_en	No	No		No		OUTPUT
mio_attr_o[11].od_en	No	No		No		OUTPUT
mio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[11].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[12].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[12].keep_en	No	No		No		OUTPUT
mio_attr_o[12].schmitt_en	No	No		No		OUTPUT
mio_attr_o[12].od_en	No	No		No		OUTPUT
mio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[12].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[12].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[13].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[13].keep_en	No	No		No		OUTPUT
mio_attr_o[13].schmitt_en	No	No		No		OUTPUT
mio_attr_o[13].od_en	No	No		No		OUTPUT
mio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[13].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[13].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[14].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[14].keep_en	No	No		No		OUTPUT
mio_attr_o[14].schmitt_en	No	No		No		OUTPUT
mio_attr_o[14].od_en	No	No		No		OUTPUT
mio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[14].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[15].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[15].keep_en	No	No		No		OUTPUT
mio_attr_o[15].schmitt_en	No	No		No		OUTPUT
mio_attr_o[15].od_en	No	No		No		OUTPUT
mio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[15].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[16].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[16].keep_en	No	No		No		OUTPUT
mio_attr_o[16].schmitt_en	No	No		No		OUTPUT
mio_attr_o[16].od_en	No	No		No		OUTPUT
mio_attr_o[16].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[16].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[16].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[17].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[17].keep_en	No	No		No		OUTPUT
mio_attr_o[17].schmitt_en	No	No		No		OUTPUT
mio_attr_o[17].od_en	No	No		No		OUTPUT
mio_attr_o[17].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[17].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[17].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[18].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[18].keep_en	No	No		No		OUTPUT
mio_attr_o[18].schmitt_en	No	No		No		OUTPUT
mio_attr_o[18].od_en	No	No		No		OUTPUT
mio_attr_o[18].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[18].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[18].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[19].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[19].keep_en	No	No		No		OUTPUT
mio_attr_o[19].schmitt_en	No	No		No		OUTPUT
mio_attr_o[19].od_en	No	No		No		OUTPUT
mio_attr_o[19].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[19].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[19].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[20].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[20].keep_en	No	No		No		OUTPUT
mio_attr_o[20].schmitt_en	No	No		No		OUTPUT
mio_attr_o[20].od_en	No	No		No		OUTPUT
mio_attr_o[20].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[20].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[20].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[21].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[21].keep_en	No	No		No		OUTPUT
mio_attr_o[21].schmitt_en	No	No		No		OUTPUT
mio_attr_o[21].od_en	No	No		No		OUTPUT
mio_attr_o[21].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[21].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[21].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[22].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[22].keep_en	No	No		No		OUTPUT
mio_attr_o[22].schmitt_en	No	No		No		OUTPUT
mio_attr_o[22].od_en	No	No		No		OUTPUT
mio_attr_o[22].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[22].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[22].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[23].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[23].keep_en	No	No		No		OUTPUT
mio_attr_o[23].schmitt_en	No	No		No		OUTPUT
mio_attr_o[23].od_en	No	No		No		OUTPUT
mio_attr_o[23].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[23].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[23].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[24].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[24].keep_en	No	No		No		OUTPUT
mio_attr_o[24].schmitt_en	No	No		No		OUTPUT
mio_attr_o[24].od_en	No	No		No		OUTPUT
mio_attr_o[24].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[24].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[24].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[25].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[25].keep_en	No	No		No		OUTPUT
mio_attr_o[25].schmitt_en	No	No		No		OUTPUT
mio_attr_o[25].od_en	No	No		No		OUTPUT
mio_attr_o[25].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[25].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[25].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[26].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[26].keep_en	No	No		No		OUTPUT
mio_attr_o[26].schmitt_en	No	No		No		OUTPUT
mio_attr_o[26].od_en	No	No		No		OUTPUT
mio_attr_o[26].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[26].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[26].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[27].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[27].keep_en	No	No		No		OUTPUT
mio_attr_o[27].schmitt_en	No	No		No		OUTPUT
mio_attr_o[27].od_en	No	No		No		OUTPUT
mio_attr_o[27].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[27].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[27].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[28].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[28].keep_en	No	No		No		OUTPUT
mio_attr_o[28].schmitt_en	No	No		No		OUTPUT
mio_attr_o[28].od_en	No	No		No		OUTPUT
mio_attr_o[28].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[28].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[28].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[29].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[29].keep_en	No	No		No		OUTPUT
mio_attr_o[29].schmitt_en	No	No		No		OUTPUT
mio_attr_o[29].od_en	No	No		No		OUTPUT
mio_attr_o[29].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[29].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[29].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[30].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[30].keep_en	No	No		No		OUTPUT
mio_attr_o[30].schmitt_en	No	No		No		OUTPUT
mio_attr_o[30].od_en	No	No		No		OUTPUT
mio_attr_o[30].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[30].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[30].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[31].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[31].keep_en	No	No		No		OUTPUT
mio_attr_o[31].schmitt_en	No	No		No		OUTPUT
mio_attr_o[31].od_en	No	No		No		OUTPUT
mio_attr_o[31].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[31].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[31].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[32].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[32].keep_en	No	No		No		OUTPUT
mio_attr_o[32].schmitt_en	No	No		No		OUTPUT
mio_attr_o[32].od_en	No	No		No		OUTPUT
mio_attr_o[32].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[32].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[32].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[33].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[33].keep_en	No	No		No		OUTPUT
mio_attr_o[33].schmitt_en	No	No		No		OUTPUT
mio_attr_o[33].od_en	No	No		No		OUTPUT
mio_attr_o[33].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[33].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[33].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[34].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[34].keep_en	No	No		No		OUTPUT
mio_attr_o[34].schmitt_en	No	No		No		OUTPUT
mio_attr_o[34].od_en	No	No		No		OUTPUT
mio_attr_o[34].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[34].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[34].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[35].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[35].keep_en	No	No		No		OUTPUT
mio_attr_o[35].schmitt_en	No	No		No		OUTPUT
mio_attr_o[35].od_en	No	No		No		OUTPUT
mio_attr_o[35].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[35].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[35].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[36].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[36].keep_en	No	No		No		OUTPUT
mio_attr_o[36].schmitt_en	No	No		No		OUTPUT
mio_attr_o[36].od_en	No	No		No		OUTPUT
mio_attr_o[36].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[36].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[36].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[37].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[37].keep_en	No	No		No		OUTPUT
mio_attr_o[37].schmitt_en	No	No		No		OUTPUT
mio_attr_o[37].od_en	No	No		No		OUTPUT
mio_attr_o[37].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[37].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[37].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[38].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[38].keep_en	No	No		No		OUTPUT
mio_attr_o[38].schmitt_en	No	No		No		OUTPUT
mio_attr_o[38].od_en	No	No		No		OUTPUT
mio_attr_o[38].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[38].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[38].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[39].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[39].keep_en	No	No		No		OUTPUT
mio_attr_o[39].schmitt_en	No	No		No		OUTPUT
mio_attr_o[39].od_en	No	No		No		OUTPUT
mio_attr_o[39].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[39].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[39].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[40].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[40].keep_en	No	No		No		OUTPUT
mio_attr_o[40].schmitt_en	No	No		No		OUTPUT
mio_attr_o[40].od_en	No	No		No		OUTPUT
mio_attr_o[40].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[40].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[40].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[41].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[41].keep_en	No	No		No		OUTPUT
mio_attr_o[41].schmitt_en	No	No		No		OUTPUT
mio_attr_o[41].od_en	No	No		No		OUTPUT
mio_attr_o[41].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[41].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[41].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[42].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[42].keep_en	No	No		No		OUTPUT
mio_attr_o[42].schmitt_en	No	No		No		OUTPUT
mio_attr_o[42].od_en	No	No		No		OUTPUT
mio_attr_o[42].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[42].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[42].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[43].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[43].keep_en	No	No		No		OUTPUT
mio_attr_o[43].schmitt_en	No	No		No		OUTPUT
mio_attr_o[43].od_en	No	No		No		OUTPUT
mio_attr_o[43].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[43].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[43].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[44].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[44].keep_en	No	No		No		OUTPUT
mio_attr_o[44].schmitt_en	No	No		No		OUTPUT
mio_attr_o[44].od_en	No	No		No		OUTPUT
mio_attr_o[44].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[44].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[44].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[45].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[45].keep_en	No	No		No		OUTPUT
mio_attr_o[45].schmitt_en	No	No		No		OUTPUT
mio_attr_o[45].od_en	No	No		No		OUTPUT
mio_attr_o[45].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[45].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[45].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[46].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[46].keep_en	No	No		No		OUTPUT
mio_attr_o[46].schmitt_en	No	No		No		OUTPUT
mio_attr_o[46].od_en	No	No		No		OUTPUT
mio_attr_o[46].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[46].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
mio_attr_o[46].drive_strength[3:1]	No	No		No		OUTPUT
mio_out_o[46:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
mio_in_i[46:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
dio_attr_o[0].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[1].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[1].keep_en	No	No		No		OUTPUT
dio_attr_o[1].schmitt_en	No	No		No		OUTPUT
dio_attr_o[1].od_en	No	No		No		OUTPUT
dio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[1].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[2].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[2].keep_en	No	No		No		OUTPUT
dio_attr_o[2].schmitt_en	No	No		No		OUTPUT
dio_attr_o[2].od_en	No	No		No		OUTPUT
dio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[2].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[3].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[3].keep_en	No	No		No		OUTPUT
dio_attr_o[3].schmitt_en	No	No		No		OUTPUT
dio_attr_o[3].od_en	No	No		No		OUTPUT
dio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[3].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[4].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[4].keep_en	No	No		No		OUTPUT
dio_attr_o[4].schmitt_en	No	No		No		OUTPUT
dio_attr_o[4].od_en	No	No		No		OUTPUT
dio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[4].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[5].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[5].keep_en	No	No		No		OUTPUT
dio_attr_o[5].schmitt_en	No	No		No		OUTPUT
dio_attr_o[5].od_en	No	No		No		OUTPUT
dio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[5].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[6].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[6].keep_en	No	No		No		OUTPUT
dio_attr_o[6].schmitt_en	No	No		No		OUTPUT
dio_attr_o[6].od_en	No	No		No		OUTPUT
dio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[6].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[7].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[7].keep_en	No	No		No		OUTPUT
dio_attr_o[7].schmitt_en	No	No		No		OUTPUT
dio_attr_o[7].od_en	No	No		No		OUTPUT
dio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[7].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[8].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[8].keep_en	No	No		No		OUTPUT
dio_attr_o[8].schmitt_en	No	No		No		OUTPUT
dio_attr_o[8].od_en	No	No		No		OUTPUT
dio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[8].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[9].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[9].keep_en	No	No		No		OUTPUT
dio_attr_o[9].schmitt_en	No	No		No		OUTPUT
dio_attr_o[9].od_en	No	No		No		OUTPUT
dio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[9].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[10].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[10].keep_en	No	No		No		OUTPUT
dio_attr_o[10].schmitt_en	No	No		No		OUTPUT
dio_attr_o[10].od_en	No	No		No		OUTPUT
dio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[10].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[11].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[11].keep_en	No	No		No		OUTPUT
dio_attr_o[11].schmitt_en	No	No		No		OUTPUT
dio_attr_o[11].od_en	No	No		No		OUTPUT
dio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[11].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[12].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[12].virt_od_en	No	No		No		OUTPUT
dio_attr_o[12].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[12].keep_en	No	No		No		OUTPUT
dio_attr_o[12].schmitt_en	No	No		No		OUTPUT
dio_attr_o[12].od_en	No	No		No		OUTPUT
dio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[13].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[13].virt_od_en	No	No		No		OUTPUT
dio_attr_o[13].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[13].keep_en	No	No		No		OUTPUT
dio_attr_o[13].schmitt_en	No	No		No		OUTPUT
dio_attr_o[13].od_en	No	No		No		OUTPUT
dio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[14].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[14].keep_en	No	No		No		OUTPUT
dio_attr_o[14].schmitt_en	No	No		No		OUTPUT
dio_attr_o[14].od_en	No	No		No		OUTPUT
dio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[14].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[15].invert	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[15].keep_en	No	No		No		OUTPUT
dio_attr_o[15].schmitt_en	No	No		No		OUTPUT
dio_attr_o[15].od_en	No	No		No		OUTPUT
dio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[15].drive_strength[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	OUTPUT
dio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
dio_out_o[11:0]	Yes	Yes	*T2,*T7,*T8	Yes	T2,T7,T8	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
dio_in_i[15:0]	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : pinmux

	Line No.	Total	Covered	Percent
Branches		778	346	44.47
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	1	25.00
TERNARY	482	4	1	25.00
TERNARY	465	2	1	50.00
TERNARY	469	2	1	50.00
TERNARY	478	4	2	50.00
TERNARY	482	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	1	25.00
TERNARY	518	4	1	25.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	1	25.00
TERNARY	518	4	1	25.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	1	25.00
TERNARY	518	4	1	25.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	1	25.00
TERNARY	518	4	1	25.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	1	25.00
TERNARY	518	4	1	25.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	1	25.00
TERNARY	518	4	1	25.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	2	50.00
TERNARY	518	4	2	50.00
TERNARY	501	2	1	50.00
TERNARY	505	2	1	50.00
TERNARY	514	4	1	25.00
TERNARY	518	4	1	25.00
TERNARY	547	2	1	50.00
TERNARY	547	2	2	100.00
TERNARY	547	2	2	100.00
TERNARY	547	2	2	100.00
TERNARY	547	2	1	50.00
TERNARY	547	2	2	100.00
TERNARY	547	2	1	50.00
TERNARY	547	2	1	50.00
IF	157	2	2	100.00
IF	409	2	2	100.00
IF	291	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[16].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[16].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[17].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[17].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[18].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[18].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[19].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[19].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[20].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[20].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[21].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[21].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[22].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[22].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[23].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[23].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[24].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[24].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[25].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[25].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[26].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[26].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[27].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[27].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[28].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[28].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[29].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[29].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[30].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[30].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[31].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[31].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[32].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[32].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[33].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[33].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[34].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[34].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[35].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[35].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[36].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[36].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[37].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[37].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[38].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[38].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[39].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[39].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[40].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[40].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[41].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[41].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[42].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[42].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[43].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[43].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[44].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[44].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[45].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[45].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	465	(reg2hw.mio_pad_sleep_status[46].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[46].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	478	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	478	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	478	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T19,T20,T36
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T19,T20,T36
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	501	(reg2hw.dio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	514	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	514	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T13,T14,T15
0	0	0	Not Covered

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[0].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[1].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T36
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[2].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T36
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[3].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T36
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[4].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[5].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T36
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[6].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	547	(reg2hw.wkup_detector[7].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	157	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	409	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	291	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Module : pinmux

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	21	80.77
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	21	80.77

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	2198624	2180554	0	0
AonWkupReqKnownO_A	22125	18531	0	0
DftJtagTckKnown_A	2198624	2180554	0	0
DftJtagTmsKnown_A	2198624	2180554	0	0
DftJtagTrstKnown_A	2198624	2180554	0	0
DftStrapsKnown_A	2198624	2180554	0	0
DioKnownO_A	2198624	2180554	0	0
DioOeKnownO_A	2198624	2180554	0	0
FpvSecCmBusIntegrity_A	2198624	0	0	0
FpvSecCmRegWeOnehotCheck_A	2198624	0	0	0
LcJtagTckKnown_A	2198624	2180554	0	0
LcJtagTmsKnown_A	2198624	2180554	0	0
LcJtagTrstKnown_A	2198624	2180554	0	0
MioKnownO_A	2198624	2180554	0	0
MioOeKnownO_A	2198624	2180554	0	0
PinmuxWkupStable_A	22125	0	0	0
PwrMgrStrapSampleOnce0_A	2198624	16	0	0
PwrMgrStrapSampleOnce1_A	2198624	0	0	0
RvJtagTckKnown_A	2198624	2180554	0	0
RvJtagTmsKnown_A	2198624	2180554	0	0
RvJtagTrstKnown_A	2198624	2180554	0	0
TlAReadyKnownO_A	2198624	2180554	0	0
TlDValidKnownO_A	2198624	2180554	0	0
UsbWakeDetectActiveKnownO_A	22125	18531	0	0
UsbWkupReqKnownO_A	22125	18531	0	0
gen_strap_override.LcCtrlStrapSampleOverrideOnce_A	2198624	0	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

AonWkupReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125	18531	0	0
T13	327	102	0	0
T14	327	102	0	0
T15	327	102	0	0
T29	327	102	0	0
T30	327	102	0	0
T31	327	102	0	0
T32	327	102	0	0
T33	327	102	0	0
T34	327	102	0	0
T35	327	102	0	0

DftJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

DftJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

DftJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

DftStrapsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

DioKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

DioOeKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

FpvSecCmBusIntegrity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	0	0	0

LcJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

LcJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

LcJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

MioKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

MioOeKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

PinmuxWkupStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125	0	0	0

PwrMgrStrapSampleOnce0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	16	0	0
T13	10619	1	0	0
T14	10619	1	0	0
T15	10619	1	0	0
T29	10619	1	0	0
T30	10619	1	0	0
T31	10619	1	0	0
T32	10619	1	0	0
T33	10619	1	0	0
T34	10619	1	0	0
T35	10619	1	0	0

PwrMgrStrapSampleOnce1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	0	0	0

RvJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

RvJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

RvJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	2180554	0	0
T13	10619	9490	0	0
T14	10619	9490	0	0
T15	10619	9490	0	0
T29	10619	9490	0	0
T30	10619	9490	0	0
T31	10619	9490	0	0
T32	10619	9490	0	0
T33	10619	9490	0	0
T34	10619	9490	0	0
T35	10619	9490	0	0

UsbWakeDetectActiveKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125	18531	0	0
T13	327	102	0	0
T14	327	102	0	0
T15	327	102	0	0
T29	327	102	0	0
T30	327	102	0	0
T31	327	102	0	0
T32	327	102	0	0
T33	327	102	0	0
T34	327	102	0	0
T35	327	102	0	0

UsbWkupReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22125	18531	0	0
T13	327	102	0	0
T14	327	102	0	0
T15	327	102	0	0
T29	327	102	0	0
T30	327	102	0	0
T31	327	102	0	0
T32	327	102	0	0
T33	327	102	0	0
T34	327	102	0	0
T35	327	102	0	0

gen_strap_override.LcCtrlStrapSampleOverrideOnce_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2198624	0	0	0