Unified Coverage Report :: Module :: csrng

Module : csrng

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
18.18			18.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_csrng_0.1/rtl/csrng.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_csrng	18.18			18.18

---

Module Instance : tb.dut.top_earlgrey.u_csrng

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
18.18			18.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
18.18			18.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.70	68.10		83.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : csrng

	Total	Covered	Percent
Totals	65	35	53.85
Total Bits	1782	324	18.18
Total Bits 0->1	891	162	18.18
Total Bits 1->0	891	162	18.18

Ports	65	35	53.85
Port Bits	1782	324	18.18
Port Bits 0->1	891	162	18.18
Port Bits 1->0	891	162	18.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otp_en_csrng_sw_app_read_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_src_hw_if_o.es_req	No	No		No		OUTPUT
entropy_src_hw_if_i.es_fips	No	No		No		INPUT
entropy_src_hw_if_i.es_bits[383:0]	No	No		No		INPUT
entropy_src_hw_if_i.es_ack	No	No		No		INPUT
cs_aes_halt_i.cs_aes_halt_req	No	No		No		INPUT
cs_aes_halt_o.cs_aes_halt_ack	No	No		No		OUTPUT
csrng_cmd_i[0].genbits_ready	No	No		No		INPUT
csrng_cmd_i[0].csrng_req_bus[31:0]	No	No		No		INPUT
csrng_cmd_i[0].csrng_req_valid	No	No		No		INPUT
csrng_cmd_i[1].genbits_ready	No	No		No		INPUT
csrng_cmd_i[1].csrng_req_bus[31:0]	No	No		No		INPUT
csrng_cmd_i[1].csrng_req_valid	No	No		No		INPUT
csrng_cmd_o[0].genbits_bus[127:0]	No	No		No		OUTPUT
csrng_cmd_o[0].genbits_fips	No	No		No		OUTPUT
csrng_cmd_o[0].genbits_valid	No	No		No		OUTPUT
csrng_cmd_o[0].csrng_rsp_sts	No	No		No		OUTPUT
csrng_cmd_o[0].csrng_rsp_ack	No	No		No		OUTPUT
csrng_cmd_o[0].csrng_req_ready	No	No		No		OUTPUT
csrng_cmd_o[1].genbits_bus[127:0]	No	No		No		OUTPUT
csrng_cmd_o[1].genbits_fips	No	No		No		OUTPUT
csrng_cmd_o[1].genbits_valid	No	No		No		OUTPUT
csrng_cmd_o[1].csrng_rsp_sts	No	No		No		OUTPUT
csrng_cmd_o[1].csrng_rsp_ack	No	No		No		OUTPUT
csrng_cmd_o[1].csrng_req_ready	No	No		No		OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
intr_cs_cmd_req_done_o	No	No		No		OUTPUT
intr_cs_entropy_req_o	No	No		No		OUTPUT
intr_cs_hw_inst_exc_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_cs_fatal_err_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT

*Tests covering at least one bit in the range