Unified Coverage Report :: Module :: prim_lc_or

Module : prim_lc_or_hardened

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened	100.00	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	96.37	100.00			93.22	94.12	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_lc_sync_a	100.00	100.00					100.00
u_prim_lc_sync_b	100.00	100.00					100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_lc_or_hardened

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	60	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' or '../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	4	4
60	1	1

Cond Coverage for Module : prim_lc_or_hardened

	Total	Covered	Percent
Conditions	28	28	100.00
Logical	28	28	100.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((lc_en_a_copies[0] == ActVal) || (lc_en_b_copies[0] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T19,T20,T16
1	0	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[0] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[0] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

 LINE       56
 EXPRESSION ((lc_en_a_copies[1] == ActVal) || (lc_en_b_copies[1] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T19,T20,T16
1	0	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[1] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[1] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

 LINE       56
 EXPRESSION ((lc_en_a_copies[2] == ActVal) || (lc_en_b_copies[2] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T19,T20,T16
1	0	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[2] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[2] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

 LINE       56
 EXPRESSION ((lc_en_a_copies[3] == ActVal) || (lc_en_b_copies[3] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T19,T20,T16
1	0	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[3] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[3] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T19,T20,T16

Assert Coverage for Module : prim_lc_or_hardened

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FunctionCheck_A	2198624	2180554	0	0
OutputsKnown_A	2198624	2180554	0	0

FunctionCheck_A

Name	Attempts	Real Successes
Total	2198624	2180554
T13	10619	9490
T14	10619	9490
T15	10619	9490
T29	10619	9490
T30	10619	9490
T31	10619	9490
T32	10619	9490
T33	10619	9490
T34	10619	9490
T35	10619	9490

OutputsKnown_A

Name	Attempts	Real Successes
Total	2198624	2180554
T13	10619	9490
T14	10619	9490
T15	10619	9490
T29	10619	9490
T30	10619	9490
T31	10619	9490
T32	10619	9490
T33	10619	9490
T34	10619	9490
T35	10619	9490