Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.23			69.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_keymgr	69.23			69.23

---

Module Instance : tb.dut.top_earlgrey.u_keymgr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.23			69.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.23			69.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.70	68.10		83.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	67	46	68.66
Total Bits	8938	6188	69.23
Total Bits 0->1	4469	3094	69.23
Total Bits 1->0	4469	3094	69.23

Ports	67	46	68.66
Port Bits	8938	6188	69.23
Port Bits 0->1	4469	3094	69.23
Port Bits 1->0	4469	3094	69.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T21	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_address[7:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_address[17:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T21	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
aes_key_o.key[1:0][255:0]	Yes	Yes	T22,T7,T23	Yes	T22,T7,T23	OUTPUT
aes_key_o.valid	No	No		No		OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T22,T7,T23	Yes	T22,T7,T23	OUTPUT
kmac_key_o.valid	No	No		No		OUTPUT
otbn_key_o.key[1:0][383:0]	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
otbn_key_o.valid	No	No		No		OUTPUT
kmac_data_o.last	No	No		No		OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT
kmac_data_o.valid	No	No		No		OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	No	No		No		INPUT
kmac_data_i.digest_share0[383:0]	No	No		No		INPUT
kmac_data_i.done	No	No		No		INPUT
kmac_data_i.ready	No	No		No		INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[6:3]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[8:7]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[9]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	INPUT
lc_keymgr_div_i[10]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[19:11]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[20]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[26:21]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[27]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[37:28]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[38]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[39]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[40]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[41]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	INPUT
lc_keymgr_div_i[42]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[43]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[44]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[45]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[46]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[50:47]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[51]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[61:52]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[63:62]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[66:64]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	INPUT
lc_keymgr_div_i[68:67]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[72:69]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	INPUT
lc_keymgr_div_i[73]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[75:74]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
lc_keymgr_div_i[76]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[81:77]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[82]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[91:83]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	INPUT
lc_keymgr_div_i[92]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[97:93]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[98]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[99]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	INPUT
lc_keymgr_div_i[100]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[101]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[102]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[104]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[105]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[106]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[108:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[109]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[112:110]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[113]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[119:114]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[120]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[121]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[122]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[124:123]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[125]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[127:126]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_key_i.key_share1[255:0]	Yes	Yes	T22,T7,T42	Yes	T22,T7,T42	INPUT
otp_key_i.key_share0[255:0]	Yes	Yes	T1,T7,T42	Yes	T1,T7,T42	INPUT
otp_key_i.valid	No	No		No		INPUT
otp_device_id_i[255:0]	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	INPUT
flash_i.seeds[1:0][255:0]	No	No		No		INPUT
edn_o.edn_req	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
rom_digest_i.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[3:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[4]	No	No		No		INPUT
rom_digest_i.data[9:5]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[10]	No	No		No		INPUT
rom_digest_i.data[16:11]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[17]	No	No		No		INPUT
rom_digest_i.data[20:18]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[22:21]	No	No		No		INPUT
rom_digest_i.data[27:23]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[28]	No	No		No		INPUT
rom_digest_i.data[32:29]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[33]	No	No		No		INPUT
rom_digest_i.data[37:34]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[38]	No	No		No		INPUT
rom_digest_i.data[43:39]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[45:44]	No	No		No		INPUT
rom_digest_i.data[47:46]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[48]	No	No		No		INPUT
rom_digest_i.data[49]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[50]	No	No		No		INPUT
rom_digest_i.data[55:51]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[56]	No	No		No		INPUT
rom_digest_i.data[59:57]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[60]	No	No		No		INPUT
rom_digest_i.data[67:61]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[68]	No	No		No		INPUT
rom_digest_i.data[69]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[71:70]	No	No		No		INPUT
rom_digest_i.data[74:72]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[75]	No	No		No		INPUT
rom_digest_i.data[76]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[77]	No	No		No		INPUT
rom_digest_i.data[79:78]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[80]	No	No		No		INPUT
rom_digest_i.data[88:81]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[89]	No	No		No		INPUT
rom_digest_i.data[105:90]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[106]	No	No		No		INPUT
rom_digest_i.data[115:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[116]	No	No		No		INPUT
rom_digest_i.data[120:117]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[121]	No	No		No		INPUT
rom_digest_i.data[135:122]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[136]	No	No		No		INPUT
rom_digest_i.data[140:137]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[141]	No	No		No		INPUT
rom_digest_i.data[142]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[143]	No	No		No		INPUT
rom_digest_i.data[159:144]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[160]	No	No		No		INPUT
rom_digest_i.data[161]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[162]	No	No		No		INPUT
rom_digest_i.data[176:163]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[177]	No	No		No		INPUT
rom_digest_i.data[203:178]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[204]	No	No		No		INPUT
rom_digest_i.data[217:205]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[218]	No	No		No		INPUT
rom_digest_i.data[221:219]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[223:222]	No	No		No		INPUT
rom_digest_i.data[227:224]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
rom_digest_i.data[228]	No	No		No		INPUT
rom_digest_i.data[237:229]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[239:238]	No	No		No		INPUT
rom_digest_i.data[248:240]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[249]	No	No		No		INPUT
rom_digest_i.data[250]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[251]	No	No		No		INPUT
rom_digest_i.data[254:252]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[255]	No	No		No		INPUT
intr_op_done_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T22,T7,T23	Yes	T22,T7,T23	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T22,T7,T23	Yes	T22,T7,T23	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T22,T7	Yes	T2,T22,T7	OUTPUT

*Tests covering at least one bit in the range