Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_clkmgr_aon.u_io_div4_meas.u_err_sync

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	50.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	50.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
56.26	86.00	65.12			73.91	0.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
15.28	27.78	0.00			33.33	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
26.46	45.83	0.00			60.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00					0.00	u_prim_sync_reqack_data

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
38.19	69.44	33.33			50.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.10	77.08	33.33			70.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00					0.00	u_prim_sync_reqack_data

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T7,T8
EVEN	0	-	Covered	T2,T7,T8
ODD	-	1	Covered	T2,T7,T8
ODD	-	0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T7,T8
EVEN	0	-	Covered	T2,T7,T8
ODD	-	1	Covered	T2,T7,T8
ODD	-	0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	29769717	373	0	0
SyncReqAckHoldReq	296172	93	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	29769717	373	0	0
T2	98103	2	0	0
T7	170704	2	0	0
T8	98103	2	0	0
T9	98103	2	0	0
T25	690581	16	0	0
T26	690581	16	0	0
T27	170704	2	0	0
T28	0	16	0	0
T42	49070	0	0	0
T44	49070	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	29579	0	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	296172	93	0	0
T2	1055	2	0	0
T7	14462	2	0	0
T8	1055	2	0	0
T9	1055	2	0	0
T25	5991	2	0	0
T26	5991	2	0	0
T27	14462	2	0	0
T28	0	2	0	0
T42	1317	0	0	0
T44	1317	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	484	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		36	10	27.78
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	195	1	0	0.00
ALWAYS	219	12	0	0.00
ALWAYS	263	12	0	0.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	0	1
195	0	1
219	0	1
222	0	1
223	0	1
225	0	1
229	0	1
230	0	1
233	0	1
234	0	1
			==> MISSING_ELSE
241	0	1
242	0	1
245	0	1
246	0	1
			==> MISSING_ELSE
263	0	1
266	0	1
267	0	1
269	0	1
273	0	1
274	0	1
277	0	1
278	0	1
			==> MISSING_ELSE
285	0	1
286	0	1
289	0	1
290	0	1
			==> MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	4	33.33
CASE	225	4	0	0.00
CASE	269	4	0	0.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Not Covered
EVEN	0	-	Not Covered
ODD	-	1	Not Covered
ODD	-	0	Not Covered

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Not Covered
EVEN	0	-	Not Covered
ODD	-	1	Not Covered
ODD	-	0	Not Covered

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	0	0.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	0	0.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	2470686	0	0	0
SyncReqAckHoldReq	10255138	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	2470686	0	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		36	25	69.44
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	7	58.33
ALWAYS	263	12	7	58.33
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	0	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	0	1
			MISSING_ELSE
241	0	1
242	0	1
245	0	1
246	0	1
			==> MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	0	1
			MISSING_ELSE
285	0	1
286	0	1
289	0	1
290	0	1
			==> MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack

	Total	Covered	Percent
Conditions	6	2	33.33
Logical	6	2	33.33
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T15
1	1	Not Covered

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T15
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	6	50.00
CASE	225	4	1	25.00
CASE	269	4	1	25.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Not Covered
EVEN	0	-	Covered	T13,T14,T15
ODD	-	1	Not Covered
ODD	-	0	Not Covered

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Not Covered
EVEN	0	-	Covered	T13,T14,T15
ODD	-	1	Not Covered
ODD	-	0	Not Covered

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	0	0.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	0	0.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	10255138	0	0	0
SyncReqAckHoldReq	10255138	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0