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LINE 66
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 78
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 85
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T4,T5,T6 |
| 0 | 0 | 1 | Not Covered | |
| 0 | 1 | 0 | Covered | T46,T47,T51 |
| 1 | 0 | 0 | Not Covered | |
LINE 133
EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[128:159]}) ? 1'b0 : 1'b1)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 171
EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
-----------1---------- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T4,T5,T6 |
| 0 | 0 | 1 | Covered | T46,T47,T51 |
| 0 | 1 | 0 | Covered | T4,T5,T21 |
| 1 | 0 | 0 | Covered | T4,T5,T21 |
LINE 171
SUB-EXPRESSION (devmode_i & addrmiss)
----1---- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 450
EXPRESSION (ibus_addr_en_0_we & ibus_regwen_0_qs)
--------1-------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T7,T8 |
| 1 | 1 | Covered | T4,T21,T2 |
LINE 482
EXPRESSION (ibus_addr_en_1_we & ibus_regwen_1_qs)
--------1-------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T8,T9 |
| 1 | 1 | Covered | T59,T60,T68 |
LINE 514
EXPRESSION (ibus_addr_matching_0_we & ibus_regwen_0_qs)
-----------1----------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T7,T8 |
| 1 | 1 | Covered | T5,T49,T50 |
LINE 546
EXPRESSION (ibus_addr_matching_1_we & ibus_regwen_1_qs)
-----------1----------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T8,T9 |
| 1 | 1 | Covered | T4,T21,T63 |
LINE 578
EXPRESSION (ibus_remap_addr_0_we & ibus_regwen_0_qs)
----------1--------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T8,T9 |
| 1 | 1 | Covered | T2,T59,T60 |
LINE 610
EXPRESSION (ibus_remap_addr_1_we & ibus_regwen_1_qs)
----------1--------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T8,T9 |
| 1 | 1 | Covered | T59,T60,T68 |
LINE 700
EXPRESSION (dbus_addr_en_0_we & dbus_regwen_0_qs)
--------1-------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T7,T8 |
| 1 | 1 | Covered | T50,T57,T58 |
LINE 732
EXPRESSION (dbus_addr_en_1_we & dbus_regwen_1_qs)
--------1-------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T7,T8 |
| 1 | 1 | Covered | T4,T21,T57 |
LINE 764
EXPRESSION (dbus_addr_matching_0_we & dbus_regwen_0_qs)
-----------1----------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T7,T8 |
| 1 | 1 | Covered | T4,T21,T63 |
LINE 796
EXPRESSION (dbus_addr_matching_1_we & dbus_regwen_1_qs)
-----------1----------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T25,T26,T28 |
| 1 | 1 | Covered | T50,T57,T62 |
LINE 828
EXPRESSION (dbus_remap_addr_0_we & dbus_regwen_0_qs)
----------1--------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T7,T8 |
| 1 | 1 | Covered | T59,T60,T68 |
LINE 860
EXPRESSION (dbus_remap_addr_1_we & dbus_regwen_1_qs)
----------1--------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T2,T7,T8 |
| 1 | 1 | Covered | T2,T59,T60 |
LINE 1178
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ALERT_TEST_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T21 |
| 1 | Covered | T4,T5,T6 |
LINE 1179
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_RECOV_ERR_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1180
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_FATAL_ERR_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1181
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1182
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1183
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1184
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1185
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET)
--------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1186
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET)
--------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T21,T46 |
LINE 1187
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET)
------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1188
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET)
------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T21,T46 |
LINE 1189
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T21,T46 |
LINE 1190
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1191
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1192
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T21,T46 |
LINE 1193
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET)
--------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1194
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET)
--------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T21,T46 |
LINE 1195
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET)
------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1196
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET)
------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T49,T46 |
LINE 1197
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_ENABLE_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1198
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_STATE_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1199
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ERR_STATUS_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T49,T46 |
LINE 1200
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_DATA_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1201
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_STATUS_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T21,T46 |
LINE 1202
EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_FPGA_INFO_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1205
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T21 |
LINE 1205
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | Covered | T4,T5,T21 |
LINE 1209
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1111 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|
| ALL ZEROS | Covered | T4,T5,T21 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T4,T5,T21 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T4,T21,T46 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T4,T5,T21 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T5,T49,T46 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T5,T49,T46 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T4,T21,T46 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T5,T49,T46 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T4,T5,T21 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T4,T21,T46 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T5,T49,T46 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T4,T21,T46 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T4,T5,T21 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T4,T5,T21 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T4,T21,T46 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T4,T21,T46 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T4,T5,T21 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T4,T21,T46 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T4,T21,T46 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T4,T5,T21 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T4,T5,T21 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T4,T5,T21 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T4,T21,T46 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T4,T5,T21 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T4,T5,T21 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T4,T5,T6 |
LINE 1209
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 1209
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T21,T51 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T21,T46 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T47,T51 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T5,T49,T50 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T21,T46 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T51,T2,T72 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T51,T2,T59 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T47,T51 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T21,T46 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T50,T47 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T21,T46 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T21,T51 |
| 1 | 1 | Covered | T5,T49,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T50,T47 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T47,T51 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T46,T47,T51 |
| 1 | 1 | Covered | T5,T49,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T21 |
| 1 | 1 | Covered | T5,T49,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[21] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T51,T2,T59 |
| 1 | 1 | Covered | T5,T49,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T51,T2,T72 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1209
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T21,T46 |
| 1 | 1 | Covered | T4,T21,T46 |
LINE 1209
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T5,T49,T51 |
| 1 | 1 | Covered | T4,T5,T21 |
LINE 1238
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T5,T49,T50 |
| 1 | 1 | 1 | Covered | T4,T5,T21 |
LINE 1247
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T59,T60,T68 |
| 1 | 1 | 1 | Covered | T4,T5,T21 |
LINE 1250
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T1,T3,T59 |
| 1 | 1 | 1 | Covered | T4,T21,T63 |
LINE 1253
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T21,T1 |
| 1 | 1 | 0 | Covered | T4,T21,T63 |
| 1 | 1 | 1 | Covered | T4,T5,T21 |
LINE 1256
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T5,T49,T69 |
| 1 | 1 | 1 | Covered | T4,T21,T50 |
LINE 1259
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T59,T60,T68 |
| 1 | 1 | 1 | Covered | T4,T21,T2 |
LINE 1262
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T4,T21,T57 |
| 1 | 1 | 1 | Covered | T2,T59,T60 |
LINE 1265
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T21,T1 |
| 1 | 1 | 0 | Covered | T59,T60,T68 |
| 1 | 1 | 1 | Covered | T5,T49,T50 |
LINE 1268
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T21,T1 |
| 1 | 1 | 0 | Covered | T4,T21,T63 |
| 1 | 1 | 1 | Covered | T4,T21,T2 |
LINE 1271
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T5,T49,T69 |
| 1 | 1 | 1 | Covered | T2,T59,T60 |
LINE 1274
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T21,T50 |
| 1 | 1 | 0 | Covered | T4,T21,T1 |
| 1 | 1 | 1 | Covered | T2,T59,T60 |
LINE 1277
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T21,T50 |
| 1 | 1 | 0 | Covered | T59,T60,T68 |
| 1 | 1 | 1 | Covered | T2,T59,T60 |
LINE 1280
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T59,T60,T68 |
| 1 | 1 | 1 | Covered | T4,T21,T2 |
LINE 1283
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T59,T60,T68 |
| 1 | 1 | 1 | Covered | T50,T57,T58 |
LINE 1286
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T21,T1 |
| 1 | 1 | 0 | Covered | T4,T21,T63 |
| 1 | 1 | 1 | Covered | T4,T21,T57 |
LINE 1289
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T5,T49,T50 |
| 1 | 1 | 0 | Covered | T5,T49,T1 |
| 1 | 1 | 1 | Covered | T4,T21,T2 |
LINE 1292
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T21,T50 |
| 1 | 1 | 0 | Covered | T4,T21,T1 |
| 1 | 1 | 1 | Covered | T50,T57,T62 |
LINE 1295
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T21 |
| 1 | 0 | 1 | Covered | T4,T5,T21 |
| 1 | 1 | 0 | Covered | T59,T60,T68 |
| 1 | 1 | 1 | Covered | T2,T59,T60 |