Unified Coverage Report :: Module :: rv_core_ibex_cfg_reg_top

Module : rv_core_ibex_cfg_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.45	98.88	97.76			97.14	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg	98.45	98.88	97.76			97.14	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.45	98.88	97.76			97.14	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	95.90	96.09			98.74	95.45

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
57.89	58.82	46.43	61.85		75.00	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_hw_err	100.00	100.00
u_alert_test_fatal_sw_err	100.00	100.00
u_alert_test_recov_hw_err	100.00	100.00
u_alert_test_recov_sw_err	100.00	100.00
u_chk	100.00	100.00					100.00
u_dbus_addr_en_0	100.00	100.00	100.00			100.00
u_dbus_addr_en_1	100.00	100.00	100.00			100.00
u_dbus_addr_matching_0	100.00	100.00	100.00			100.00
u_dbus_addr_matching_1	100.00	100.00	100.00			100.00
u_dbus_regwen_0	100.00	100.00	100.00			100.00
u_dbus_regwen_1	100.00	100.00	100.00			100.00
u_dbus_remap_addr_0	100.00	100.00	100.00			100.00
u_dbus_remap_addr_1	100.00	100.00	100.00			100.00
u_err_status_fatal_core_err	85.19	88.89	66.67			100.00
u_err_status_fatal_intg_err	96.30	88.89	100.00			100.00
u_err_status_recov_core_err	85.19	88.89	66.67			100.00
u_err_status_reg_intg_err	93.52	88.89	91.67			100.00
u_fpga_info	33.33	33.33
u_ibus_addr_en_0	100.00	100.00	100.00			100.00
u_ibus_addr_en_1	100.00	100.00	100.00			100.00
u_ibus_addr_matching_0	100.00	100.00	100.00			100.00
u_ibus_addr_matching_1	100.00	100.00	100.00			100.00
u_ibus_regwen_0	100.00	100.00	100.00			100.00
u_ibus_regwen_1	100.00	100.00	100.00			100.00
u_ibus_remap_addr_0	100.00	100.00	100.00			100.00
u_ibus_remap_addr_1	100.00	100.00	100.00			100.00
u_nmi_enable_alert_en	100.00	100.00	100.00			100.00
u_nmi_enable_wdog_en	100.00	100.00	100.00			100.00
u_nmi_state_alert	85.19	88.89	66.67			100.00
u_nmi_state_wdog	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rnd_data	33.33	33.33
u_rnd_status_rnd_data_fips	33.33	33.33
u_rnd_status_rnd_data_valid	33.33	33.33
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	91.71	90.00	91.07			92.00	93.75
u_sw_fatal_err	100.00	100.00	100.00			100.00
u_sw_recov_err	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_core_ibex_cfg_reg_top

	Line No.	Total	Covered	Percent
TOTAL		178	176	98.88
ALWAYS	76	4	3	75.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	0	0.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	828	1	1	100.00
CONT_ASSIGN	860	1	1	100.00
ALWAYS	1177	26	26	100.00
CONT_ASSIGN	1205	1	1	100.00
ALWAYS	1209	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1315	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1321	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
ALWAYS	1326	26	26	100.00
ALWAYS	1356	36	36	100.00
CONT_ASSIGN	1478	0	0
CONT_ASSIGN	1486	1	1	100.00
CONT_ASSIGN	1487	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
78	1	1
79	0	1
			MISSING_ELSE
85	1	1
103	1	1
104	1	1
106	1	1
107	0	1
133	1	1
139	1	1
140	1	1
			MISSING_ELSE
170	1	1
171	1	1
266	1	1
281	1	1
297	1	1
313	1	1
329	1	1
450	1	1
482	1	1
514	1	1
546	1	1
578	1	1
610	1	1
700	1	1
732	1	1
764	1	1
796	1	1
828	1	1
860	1	1
1177	1	1
1178	1	1
1179	1	1
1180	1	1
1181	1	1
1182	1	1
1183	1	1
1184	1	1
1185	1	1
1186	1	1
1187	1	1
1188	1	1
1189	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1195	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1200	1	1
1201	1	1
1202	1	1
1205	1	1
1209	1	1
1238	1	1
1240	1	1
1242	1	1
1244	1	1
1246	1	1
1247	1	1
1249	1	1
1250	1	1
1252	1	1
1253	1	1
1255	1	1
1256	1	1
1258	1	1
1259	1	1
1261	1	1
1262	1	1
1264	1	1
1265	1	1
1267	1	1
1268	1	1
1270	1	1
1271	1	1
1273	1	1
1274	1	1
1276	1	1
1277	1	1
1279	1	1
1280	1	1
1282	1	1
1283	1	1
1285	1	1
1286	1	1
1288	1	1
1289	1	1
1291	1	1
1292	1	1
1294	1	1
1295	1	1
1297	1	1
1298	1	1
1300	1	1
1301	1	1
1303	1	1
1305	1	1
1306	1	1
1308	1	1
1310	1	1
1311	1	1
1313	1	1
1315	1	1
1317	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1334	1	1
1335	1	1
1336	1	1
1337	1	1
1338	1	1
1339	1	1
1340	1	1
1341	1	1
1342	1	1
1343	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1356	1	1
1357	1	1
1359	1	1
1360	1	1
1361	1	1
1362	1	1
1366	1	1
1370	1	1
1374	1	1
1378	1	1
1382	1	1
1386	1	1
1390	1	1
1394	1	1
1398	1	1
1402	1	1
1406	1	1
1410	1	1
1414	1	1
1418	1	1
1422	1	1
1426	1	1
1430	1	1
1434	1	1
1438	1	1
1439	1	1
1443	1	1
1444	1	1
1448	1	1
1449	1	1
1450	1	1
1451	1	1
1455	1	1
1459	1	1
1460	1	1
1464	1	1
1478		unreachable
1486	1	1
1487	1	1

---

Cond Coverage for Module : rv_core_ibex_cfg_reg_top

	Total	Covered	Percent
Conditions	313	306	97.76
Logical	313	306	97.76
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
66-1295	98.60
1298-1322	89.29

---

Branch Coverage for Module : rv_core_ibex_cfg_reg_top

	Line No.	Total	Covered	Percent
Branches		35	34	97.14
TERNARY	1205	2	2	100.00
IF	76	3	2	66.67
TERNARY	133	2	2	100.00
IF	139	2	2	100.00
CASE	1357	26	26	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1205	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T21
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	133	((tl_i.a_address[(AW - 1):0] inside {[128:159]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T21
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	139	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T51
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1357	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T4,T5,T6
addr_hit[1]	Covered	T4,T5,T21
addr_hit[2]	Covered	T4,T5,T21
addr_hit[3]	Covered	T4,T5,T21
addr_hit[4]	Covered	T4,T5,T21
addr_hit[5]	Covered	T4,T5,T21
addr_hit[6]	Covered	T4,T5,T21
addr_hit[7]	Covered	T4,T5,T21
addr_hit[8]	Covered	T4,T21,T46
addr_hit[9]	Covered	T4,T5,T21
addr_hit[10]	Covered	T4,T21,T46
addr_hit[11]	Covered	T4,T21,T46
addr_hit[12]	Covered	T4,T5,T21
addr_hit[13]	Covered	T4,T5,T21
addr_hit[14]	Covered	T4,T21,T46
addr_hit[15]	Covered	T4,T5,T21
addr_hit[16]	Covered	T4,T21,T46
addr_hit[17]	Covered	T4,T5,T21
addr_hit[18]	Covered	T5,T49,T46
addr_hit[19]	Covered	T4,T5,T21
addr_hit[20]	Covered	T4,T5,T21
addr_hit[21]	Covered	T5,T49,T46
addr_hit[22]	Covered	T4,T5,T21
addr_hit[23]	Covered	T4,T21,T46
addr_hit[24]	Covered	T4,T5,T21
default	Covered	T4,T5,T21

---

Assert Coverage for Module : rv_core_ibex_cfg_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	117836957	25203	0	0
reAfterRv	117836957	25203	0	0
rePulse	117836957	18471	0	0
wePulse	117836957	6732	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	25203	0	0
T1	117128	6	0	0
T2	402628	104	0	0
T3	117128	6	0	0
T7	710612	2187	0	0
T8	402628	104	0	0
T42	188425	50	0	0
T43	188425	50	0	0
T45	117128	6	0	0
T55	117128	6	0	0
T56	117128	6	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	25203	0	0
T1	117128	6	0	0
T2	402628	104	0	0
T3	117128	6	0	0
T7	710612	2187	0	0
T8	402628	104	0	0
T42	188425	50	0	0
T43	188425	50	0	0
T45	117128	6	0	0
T55	117128	6	0	0
T56	117128	6	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	18471	0	0
T2	402628	56	0	0
T7	710612	2139	0	0
T8	402628	56	0	0
T9	402628	56	0	0
T25	255869	267	0	0
T27	710612	2139	0	0
T42	188425	50	0	0
T43	188425	50	0	0
T44	188425	50	0	0
T85	188425	50	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	6732	0	0
T1	117128	6	0	0
T2	402628	48	0	0
T3	117128	6	0	0
T7	710612	48	0	0
T8	402628	48	0	0
T42	188425	0	0	0
T45	117128	6	0	0
T55	117128	6	0	0
T56	117128	6	0	0
T86	117128	6	0	0
T87	0	6	0	0