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 LINE       1298
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T21
1	0	1	Covered	T5,T49,T1
1	1	0	Covered	T50,T57,T58
1	1	1	Covered	T2,T59,T60

 LINE       1301
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T21
1	0	1	Covered	T4,T5,T21
1	1	0	Covered	T4,T21,T63
1	1	1	Covered	T5,T49,T50

 LINE       1306
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T21
1	0	1	Covered	T5,T49,T50
1	1	0	Covered	T59,T60,T68
1	1	1	Covered	T4,T5,T21

 LINE       1311
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T21
1	0	1	Covered	T5,T49,T50
1	1	0	Covered	T59,T60,T68
1	1	1	Covered	T2,T59,T60

 LINE       1320
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T21
1	0	1	Covered	T5,T49,T50
1	1	0	Not Covered
1	1	1	Covered	T2,T59,T60

 LINE       1321
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T21
1	0	1	Covered	T4,T21,T50
1	1	0	Not Covered
1	1	1	Covered	T4,T21,T50

 LINE       1322
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T21
1	0	1	Covered	T4,T5,T21
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T21