Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.32			87.32

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rom_ctrl	89.75			89.75

---

Module Instance : tb.dut.top_earlgrey.u_rom_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.75			89.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.75			89.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.70	68.10		83.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	65	55	84.62
Total Bits	2808	2452	87.32
Total Bits 0->1	1404	1226	87.32
Total Bits 1->0	1404	1226	87.32

Ports	65	55	84.62
Port Bits	2808	2452	87.32
Port Bits 0->1	1404	1226	87.32
Port Bits 1->0	1404	1226	87.32

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[31:16]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
rom_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
rom_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:17]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T7,T27,T25	Yes	T7,T27,T25	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T7,T27,T25	Yes	T7,T27,T25	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[3:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[4]	No	No		No		OUTPUT
keymgr_data_o.data[9:5]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[10]	No	No		No		OUTPUT
keymgr_data_o.data[16:11]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[17]	No	No		No		OUTPUT
keymgr_data_o.data[20:18]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[22:21]	No	No		No		OUTPUT
keymgr_data_o.data[27:23]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[28]	No	No		No		OUTPUT
keymgr_data_o.data[32:29]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[33]	No	No		No		OUTPUT
keymgr_data_o.data[37:34]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[38]	No	No		No		OUTPUT
keymgr_data_o.data[43:39]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[45:44]	No	No		No		OUTPUT
keymgr_data_o.data[47:46]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[48]	No	No		No		OUTPUT
keymgr_data_o.data[49]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[50]	No	No		No		OUTPUT
keymgr_data_o.data[55:51]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[56]	No	No		No		OUTPUT
keymgr_data_o.data[59:57]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[60]	No	No		No		OUTPUT
keymgr_data_o.data[67:61]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[68]	No	No		No		OUTPUT
keymgr_data_o.data[69]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[71:70]	No	No		No		OUTPUT
keymgr_data_o.data[74:72]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[75]	No	No		No		OUTPUT
keymgr_data_o.data[76]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[77]	No	No		No		OUTPUT
keymgr_data_o.data[79:78]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[80]	No	No		No		OUTPUT
keymgr_data_o.data[88:81]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[89]	No	No		No		OUTPUT
keymgr_data_o.data[105:90]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[106]	No	No		No		OUTPUT
keymgr_data_o.data[115:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[116]	No	No		No		OUTPUT
keymgr_data_o.data[120:117]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[121]	No	No		No		OUTPUT
keymgr_data_o.data[135:122]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[136]	No	No		No		OUTPUT
keymgr_data_o.data[140:137]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[141]	No	No		No		OUTPUT
keymgr_data_o.data[142]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[143]	No	No		No		OUTPUT
keymgr_data_o.data[159:144]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[160]	No	No		No		OUTPUT
keymgr_data_o.data[161]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[162]	No	No		No		OUTPUT
keymgr_data_o.data[176:163]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[177]	No	No		No		OUTPUT
keymgr_data_o.data[203:178]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[204]	No	No		No		OUTPUT
keymgr_data_o.data[217:205]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[218]	No	No		No		OUTPUT
keymgr_data_o.data[221:219]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[223:222]	No	No		No		OUTPUT
keymgr_data_o.data[227:224]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[228]	No	No		No		OUTPUT
keymgr_data_o.data[237:229]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[239:238]	No	No		No		OUTPUT
keymgr_data_o.data[248:240]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[249]	No	No		No		OUTPUT
keymgr_data_o.data[250]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[251]	No	No		No		OUTPUT
keymgr_data_o.data[254:252]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255]	No	No		No		OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[12:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[13]	No	No		No		INPUT
kmac_data_i.digest_share1[19:14]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[20]	No	No		No		INPUT
kmac_data_i.digest_share1[34:21]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[35]	No	No		No		INPUT
kmac_data_i.digest_share1[46:36]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[48:47]	No	No		No		INPUT
kmac_data_i.digest_share1[60:49]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[61]	No	No		No		INPUT
kmac_data_i.digest_share1[63:62]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[64]	No	No		No		INPUT
kmac_data_i.digest_share1[66:65]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[67]	No	No		No		INPUT
kmac_data_i.digest_share1[98:68]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[99]	No	No		No		INPUT
kmac_data_i.digest_share1[104:100]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[105]	No	No		No		INPUT
kmac_data_i.digest_share1[108:106]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[109]	No	No		No		INPUT
kmac_data_i.digest_share1[112:110]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[113]	No	No		No		INPUT
kmac_data_i.digest_share1[146:114]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[147]	No	No		No		INPUT
kmac_data_i.digest_share1[157:148]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[158]	No	No		No		INPUT
kmac_data_i.digest_share1[160:159]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[161]	No	No		No		INPUT
kmac_data_i.digest_share1[163:162]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[164]	No	No		No		INPUT
kmac_data_i.digest_share1[177:165]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[178]	No	No		No		INPUT
kmac_data_i.digest_share1[183:179]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[184]	No	No		No		INPUT
kmac_data_i.digest_share1[186:185]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[187]	No	No		No		INPUT
kmac_data_i.digest_share1[191:188]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[192]	No	No		No		INPUT
kmac_data_i.digest_share1[212:193]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[213]	No	No		No		INPUT
kmac_data_i.digest_share1[217:214]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[218]	No	No		No		INPUT
kmac_data_i.digest_share1[220:219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[222:221]	No	No		No		INPUT
kmac_data_i.digest_share1[225:223]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[226]	No	No		No		INPUT
kmac_data_i.digest_share1[233:227]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[234]	No	No		No		INPUT
kmac_data_i.digest_share1[241:235]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[242]	No	No		No		INPUT
kmac_data_i.digest_share1[253:243]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[254]	No	No		No		INPUT
kmac_data_i.digest_share1[281:255]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[282]	No	No		No		INPUT
kmac_data_i.digest_share1[298:283]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[299]	No	No		No		INPUT
kmac_data_i.digest_share1[303:300]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[304]	No	No		No		INPUT
kmac_data_i.digest_share1[332:305]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[333]	No	No		No		INPUT
kmac_data_i.digest_share1[341:334]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[343:342]	No	No		No		INPUT
kmac_data_i.digest_share1[348:344]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[349]	No	No		No		INPUT
kmac_data_i.digest_share1[370:350]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[372:371]	No	No		No		INPUT
kmac_data_i.digest_share1[373]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[374]	No	No		No		INPUT
kmac_data_i.digest_share1[383:375]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[0]	No	No		No		INPUT
kmac_data_i.digest_share0[4:1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[5]	No	No		No		INPUT
kmac_data_i.digest_share0[17:6]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[18]	No	No		No		INPUT
kmac_data_i.digest_share0[22:19]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[23]	No	No		No		INPUT
kmac_data_i.digest_share0[25:24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[26]	No	No		No		INPUT
kmac_data_i.digest_share0[28:27]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[29]	No	No		No		INPUT
kmac_data_i.digest_share0[30]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[32:31]	No	No		No		INPUT
kmac_data_i.digest_share0[39:33]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[40]	No	No		No		INPUT
kmac_data_i.digest_share0[47:41]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[48]	No	No		No		INPUT
kmac_data_i.digest_share0[53:49]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[54]	No	No		No		INPUT
kmac_data_i.digest_share0[64:55]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[65]	No	No		No		INPUT
kmac_data_i.digest_share0[80:66]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[81]	No	No		No		INPUT
kmac_data_i.digest_share0[86:82]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[88:87]	No	No		No		INPUT
kmac_data_i.digest_share0[91:89]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[92]	No	No		No		INPUT
kmac_data_i.digest_share0[110:93]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[111]	No	No		No		INPUT
kmac_data_i.digest_share0[119:112]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[120]	No	No		No		INPUT
kmac_data_i.digest_share0[121]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[122]	No	No		No		INPUT
kmac_data_i.digest_share0[123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[125:124]	No	No		No		INPUT
kmac_data_i.digest_share0[145:126]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[146]	No	No		No		INPUT
kmac_data_i.digest_share0[148:147]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[150:149]	No	No		No		INPUT
kmac_data_i.digest_share0[151]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[152]	No	No		No		INPUT
kmac_data_i.digest_share0[164:153]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[165]	No	No		No		INPUT
kmac_data_i.digest_share0[166]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[168:167]	No	No		No		INPUT
kmac_data_i.digest_share0[169]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[170]	No	No		No		INPUT
kmac_data_i.digest_share0[174:171]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[175]	No	No		No		INPUT
kmac_data_i.digest_share0[184:176]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[185]	No	No		No		INPUT
kmac_data_i.digest_share0[198:186]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[199]	No	No		No		INPUT
kmac_data_i.digest_share0[201:200]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[202]	No	No		No		INPUT
kmac_data_i.digest_share0[217:203]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[218]	No	No		No		INPUT
kmac_data_i.digest_share0[221:219]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[222]	No	No		No		INPUT
kmac_data_i.digest_share0[229:223]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[230]	No	No		No		INPUT
kmac_data_i.digest_share0[240:231]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[241]	No	No		No		INPUT
kmac_data_i.digest_share0[267:242]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[268]	No	No		No		INPUT
kmac_data_i.digest_share0[273:269]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[275:274]	No	No		No		INPUT
kmac_data_i.digest_share0[281:276]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[282]	No	No		No		INPUT
kmac_data_i.digest_share0[284:283]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[285]	No	No		No		INPUT
kmac_data_i.digest_share0[292:286]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[293]	No	No		No		INPUT
kmac_data_i.digest_share0[295:294]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[296]	No	No		No		INPUT
kmac_data_i.digest_share0[297]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[298]	No	No		No		INPUT
kmac_data_i.digest_share0[302:299]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[303]	No	No		No		INPUT
kmac_data_i.digest_share0[306:304]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[307]	No	No		No		INPUT
kmac_data_i.digest_share0[309:308]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[310]	No	No		No		INPUT
kmac_data_i.digest_share0[315:311]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[316]	No	No		No		INPUT
kmac_data_i.digest_share0[321:317]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[322]	No	No		No		INPUT
kmac_data_i.digest_share0[327:323]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[328]	No	No		No		INPUT
kmac_data_i.digest_share0[331:329]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[332]	No	No		No		INPUT
kmac_data_i.digest_share0[340:333]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[341]	No	No		No		INPUT
kmac_data_i.digest_share0[344:342]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[346:345]	No	No		No		INPUT
kmac_data_i.digest_share0[349:347]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[350]	No	No		No		INPUT
kmac_data_i.digest_share0[363:351]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[364]	No	No		No		INPUT
kmac_data_i.digest_share0[377:365]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[378]	No	No		No		INPUT
kmac_data_i.digest_share0[380:379]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[381]	No	No		No		INPUT
kmac_data_i.digest_share0[383:382]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rom_ctrl

	Total	Covered	Percent
Totals	62	56	90.32
Total Bits	2732	2452	89.75
Total Bits 0->1	1366	1226	89.75
Total Bits 1->0	1366	1226	89.75

Ports	62	56	90.32
Port Bits	2732	2452	89.75
Port Bits 0->1	1366	1226	89.75
Port Bits 1->0	1366	1226	89.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[31:16]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
rom_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
rom_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:17]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T7,T27,T25	Yes	T7,T27,T25	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T7,T27,T25	Yes	T7,T27,T25	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[3:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[4]	No	No		No		OUTPUT
keymgr_data_o.data[9:5]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[10]	No	No		No		OUTPUT
keymgr_data_o.data[16:11]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[17]	No	No		No		OUTPUT
keymgr_data_o.data[20:18]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[22:21]	No	No		No		OUTPUT
keymgr_data_o.data[27:23]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[28]	No	No		No		OUTPUT
keymgr_data_o.data[32:29]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[33]	No	No		No		OUTPUT
keymgr_data_o.data[37:34]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[38]	No	No		No		OUTPUT
keymgr_data_o.data[43:39]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[45:44]	No	No		No		OUTPUT
keymgr_data_o.data[47:46]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[48]	No	No		No		OUTPUT
keymgr_data_o.data[49]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[50]	No	No		No		OUTPUT
keymgr_data_o.data[55:51]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[56]	No	No		No		OUTPUT
keymgr_data_o.data[59:57]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[60]	No	No		No		OUTPUT
keymgr_data_o.data[67:61]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[68]	No	No		No		OUTPUT
keymgr_data_o.data[69]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[71:70]	No	No		No		OUTPUT
keymgr_data_o.data[74:72]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[75]	No	No		No		OUTPUT
keymgr_data_o.data[76]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[77]	No	No		No		OUTPUT
keymgr_data_o.data[79:78]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[80]	No	No		No		OUTPUT
keymgr_data_o.data[88:81]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[89]	No	No		No		OUTPUT
keymgr_data_o.data[105:90]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[106]	No	No		No		OUTPUT
keymgr_data_o.data[115:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[116]	No	No		No		OUTPUT
keymgr_data_o.data[120:117]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[121]	No	No		No		OUTPUT
keymgr_data_o.data[135:122]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[136]	No	No		No		OUTPUT
keymgr_data_o.data[140:137]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[141]	No	No		No		OUTPUT
keymgr_data_o.data[142]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[143]	No	No		No		OUTPUT
keymgr_data_o.data[159:144]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[160]	No	No		No		OUTPUT
keymgr_data_o.data[161]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[162]	No	No		No		OUTPUT
keymgr_data_o.data[176:163]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[177]	No	No		No		OUTPUT
keymgr_data_o.data[203:178]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[204]	No	No		No		OUTPUT
keymgr_data_o.data[217:205]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[218]	No	No		No		OUTPUT
keymgr_data_o.data[221:219]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[223:222]	No	No		No		OUTPUT
keymgr_data_o.data[227:224]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	OUTPUT
keymgr_data_o.data[228]	No	No		No		OUTPUT
keymgr_data_o.data[237:229]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[239:238]	No	No		No		OUTPUT
keymgr_data_o.data[248:240]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[249]	No	No		No		OUTPUT
keymgr_data_o.data[250]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[251]	No	No		No		OUTPUT
keymgr_data_o.data[254:252]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255]	No	No		No		OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[12:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[13]	No	No		No		INPUT
kmac_data_i.digest_share1[19:14]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[20]	No	No		No		INPUT
kmac_data_i.digest_share1[34:21]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[35]	No	No		No		INPUT
kmac_data_i.digest_share1[46:36]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[48:47]	No	No		No		INPUT
kmac_data_i.digest_share1[60:49]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[61]	No	No		No		INPUT
kmac_data_i.digest_share1[63:62]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[64]	No	No		No		INPUT
kmac_data_i.digest_share1[66:65]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[67]	No	No		No		INPUT
kmac_data_i.digest_share1[98:68]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[99]	No	No		No		INPUT
kmac_data_i.digest_share1[104:100]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[105]	No	No		No		INPUT
kmac_data_i.digest_share1[108:106]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[109]	No	No		No		INPUT
kmac_data_i.digest_share1[112:110]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[113]	No	No		No		INPUT
kmac_data_i.digest_share1[146:114]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[147]	No	No		No		INPUT
kmac_data_i.digest_share1[157:148]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[158]	No	No		No		INPUT
kmac_data_i.digest_share1[160:159]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[161]	No	No		No		INPUT
kmac_data_i.digest_share1[163:162]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[164]	No	No		No		INPUT
kmac_data_i.digest_share1[177:165]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[178]	No	No		No		INPUT
kmac_data_i.digest_share1[183:179]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[184]	No	No		No		INPUT
kmac_data_i.digest_share1[186:185]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[187]	No	No		No		INPUT
kmac_data_i.digest_share1[191:188]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[192]	No	No		No		INPUT
kmac_data_i.digest_share1[212:193]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[213]	No	No		No		INPUT
kmac_data_i.digest_share1[217:214]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[218]	No	No		No		INPUT
kmac_data_i.digest_share1[220:219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[222:221]	No	No		No		INPUT
kmac_data_i.digest_share1[225:223]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[226]	No	No		No		INPUT
kmac_data_i.digest_share1[233:227]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[234]	No	No		No		INPUT
kmac_data_i.digest_share1[241:235]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[242]	No	No		No		INPUT
kmac_data_i.digest_share1[253:243]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[254]	No	No		No		INPUT
kmac_data_i.digest_share1[281:255]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[282]	No	No		No		INPUT
kmac_data_i.digest_share1[298:283]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[299]	No	No		No		INPUT
kmac_data_i.digest_share1[303:300]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[304]	No	No		No		INPUT
kmac_data_i.digest_share1[332:305]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[333]	No	No		No		INPUT
kmac_data_i.digest_share1[341:334]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[343:342]	No	No		No		INPUT
kmac_data_i.digest_share1[348:344]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share1[349]	No	No		No		INPUT
kmac_data_i.digest_share1[370:350]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[372:371]	No	No		No		INPUT
kmac_data_i.digest_share1[373]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share1[374]	No	No		No		INPUT
kmac_data_i.digest_share1[383:375]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[0]	No	No		No		INPUT
kmac_data_i.digest_share0[4:1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[5]	No	No		No		INPUT
kmac_data_i.digest_share0[17:6]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[18]	No	No		No		INPUT
kmac_data_i.digest_share0[22:19]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[23]	No	No		No		INPUT
kmac_data_i.digest_share0[25:24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[26]	No	No		No		INPUT
kmac_data_i.digest_share0[28:27]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[29]	No	No		No		INPUT
kmac_data_i.digest_share0[30]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[32:31]	No	No		No		INPUT
kmac_data_i.digest_share0[39:33]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[40]	No	No		No		INPUT
kmac_data_i.digest_share0[47:41]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[48]	No	No		No		INPUT
kmac_data_i.digest_share0[53:49]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[54]	No	No		No		INPUT
kmac_data_i.digest_share0[64:55]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[65]	No	No		No		INPUT
kmac_data_i.digest_share0[80:66]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[81]	No	No		No		INPUT
kmac_data_i.digest_share0[86:82]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[88:87]	No	No		No		INPUT
kmac_data_i.digest_share0[91:89]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[92]	No	No		No		INPUT
kmac_data_i.digest_share0[110:93]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[111]	No	No		No		INPUT
kmac_data_i.digest_share0[119:112]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[120]	No	No		No		INPUT
kmac_data_i.digest_share0[121]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[122]	No	No		No		INPUT
kmac_data_i.digest_share0[123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[125:124]	No	No		No		INPUT
kmac_data_i.digest_share0[145:126]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[146]	No	No		No		INPUT
kmac_data_i.digest_share0[148:147]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[150:149]	No	No		No		INPUT
kmac_data_i.digest_share0[151]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[152]	No	No		No		INPUT
kmac_data_i.digest_share0[164:153]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[165]	No	No		No		INPUT
kmac_data_i.digest_share0[166]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[168:167]	No	No		No		INPUT
kmac_data_i.digest_share0[169]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[170]	No	No		No		INPUT
kmac_data_i.digest_share0[174:171]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[175]	No	No		No		INPUT
kmac_data_i.digest_share0[184:176]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[185]	No	No		No		INPUT
kmac_data_i.digest_share0[198:186]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[199]	No	No		No		INPUT
kmac_data_i.digest_share0[201:200]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[202]	No	No		No		INPUT
kmac_data_i.digest_share0[217:203]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[218]	No	No		No		INPUT
kmac_data_i.digest_share0[221:219]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[222]	No	No		No		INPUT
kmac_data_i.digest_share0[229:223]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[230]	No	No		No		INPUT
kmac_data_i.digest_share0[240:231]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[241]	No	No		No		INPUT
kmac_data_i.digest_share0[267:242]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[268]	No	No		No		INPUT
kmac_data_i.digest_share0[273:269]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[275:274]	No	No		No		INPUT
kmac_data_i.digest_share0[281:276]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[282]	No	No		No		INPUT
kmac_data_i.digest_share0[284:283]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[285]	No	No		No		INPUT
kmac_data_i.digest_share0[292:286]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[293]	No	No		No		INPUT
kmac_data_i.digest_share0[295:294]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[296]	No	No		No		INPUT
kmac_data_i.digest_share0[297]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[298]	No	No		No		INPUT
kmac_data_i.digest_share0[302:299]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[303]	No	No		No		INPUT
kmac_data_i.digest_share0[306:304]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[307]	No	No		No		INPUT
kmac_data_i.digest_share0[309:308]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[310]	No	No		No		INPUT
kmac_data_i.digest_share0[315:311]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[316]	No	No		No		INPUT
kmac_data_i.digest_share0[321:317]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[322]	No	No		No		INPUT
kmac_data_i.digest_share0[327:323]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[328]	No	No		No		INPUT
kmac_data_i.digest_share0[331:329]	Yes	Yes	T42,T43,*T44	Yes	T42,T43,T44	INPUT
kmac_data_i.digest_share0[332]	No	No		No		INPUT
kmac_data_i.digest_share0[340:333]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[341]	No	No		No		INPUT
kmac_data_i.digest_share0[344:342]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[346:345]	No	No		No		INPUT
kmac_data_i.digest_share0[349:347]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[350]	No	No		No		INPUT
kmac_data_i.digest_share0[363:351]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[364]	No	No		No		INPUT
kmac_data_i.digest_share0[377:365]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[378]	No	No		No		INPUT
kmac_data_i.digest_share0[380:379]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[381]	No	No		No		INPUT
kmac_data_i.digest_share0[383:382]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	Excluded	Excluded		Excluded		OUTPUT	[UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range