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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
77.37 85.01 83.79 68.62 86.57 86.84 53.39


Total test records in report: 1927
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T1751 /workspace/coverage/cover_reg_top/1.xbar_smoke.8627131881124425687841526315369200523994720502416789085115059752932572059301 Nov 22 03:03:54 PM PST 23 Nov 22 03:04:03 PM PST 23 196985727 ps
T1752 /workspace/coverage/cover_reg_top/23.xbar_same_source.30743818823483506069600545910361290108466695777240758628577225307774724737320 Nov 22 03:05:52 PM PST 23 Nov 22 03:07:05 PM PST 23 2498784073 ps
T1753 /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.20812057387026735404304167574957904884522006990199264077246077876684218884713 Nov 22 03:05:19 PM PST 23 Nov 22 03:23:13 PM PST 23 60576345727 ps
T1754 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.55205680672994730530688129830923560272070495216240430704538754435032212418305 Nov 22 03:08:51 PM PST 23 Nov 22 03:13:54 PM PST 23 4815189184 ps
T1755 /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.85192784835131942305269209360010252341939777681093089781324937611419538411223 Nov 22 03:03:44 PM PST 23 Nov 22 03:54:51 PM PST 23 30604932618 ps
T1756 /workspace/coverage/cover_reg_top/9.xbar_error_random.52668404867986981417010499217045723142007844390871614282029261505364435859162 Nov 22 03:03:47 PM PST 23 Nov 22 03:05:01 PM PST 23 2231375727 ps
T1757 /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.29214553392540979764902223157134924136282278241025515354024209630770961733265 Nov 22 03:13:27 PM PST 23 Nov 22 03:14:15 PM PST 23 556965727 ps
T1758 /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.81265926166209870200367011763109716279671552332181212909149940305677625516678 Nov 22 03:08:45 PM PST 23 Nov 22 03:09:39 PM PST 23 1176995727 ps
T1759 /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.50985893312037579948385952114675059511414080954093107670999884980481160762916 Nov 22 03:05:32 PM PST 23 Nov 22 03:07:03 PM PST 23 7758585727 ps
T1760 /workspace/coverage/cover_reg_top/12.xbar_same_source.38603647512364463134499615380874140887686058763815261555221143083433579068241 Nov 22 03:04:01 PM PST 23 Nov 22 03:05:13 PM PST 23 2498784073 ps
T1761 /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.20895223398397878125983625330247913605185277073226554675032924582346912030974 Nov 22 03:04:19 PM PST 23 Nov 22 03:23:36 PM PST 23 97702135727 ps
T1762 /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.43418440867069179932216148725030443415259452578130365570375630316324898881494 Nov 22 03:07:40 PM PST 23 Nov 22 03:16:11 PM PST 23 13999524073 ps
T1763 /workspace/coverage/cover_reg_top/48.xbar_stress_all.30230533910118156206874114939229020877155515249720700645754903973228550358787 Nov 22 03:07:44 PM PST 23 Nov 22 03:16:50 PM PST 23 13992004073 ps
T1764 /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.90181289151263902371201590860463864599796336347087471730100223761851884473614 Nov 22 03:12:57 PM PST 23 Nov 22 03:14:25 PM PST 23 4856075727 ps
T1765 /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.100601441761108562352922158630261940888099840121022291324481757158134245483219 Nov 22 03:05:59 PM PST 23 Nov 22 03:06:42 PM PST 23 556965727 ps
T1766 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.14960022312600375951748868717296372553703331417148369466849665980641247879236 Nov 22 03:05:50 PM PST 23 Nov 22 03:11:10 PM PST 23 4815189184 ps
T1767 /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.111256544604906514687219071197034587850142748722756841631583194747465040935210 Nov 22 03:03:58 PM PST 23 Nov 22 03:04:43 PM PST 23 556965727 ps
T1768 /workspace/coverage/cover_reg_top/35.xbar_stress_all.44550441934850468415211695338383397203778629758462986696333267077738853692084 Nov 22 03:06:23 PM PST 23 Nov 22 03:15:04 PM PST 23 13992004073 ps
T1769 /workspace/coverage/cover_reg_top/46.xbar_error_random.67661479863180481140967713093418910798476928189769880626398616426030271916143 Nov 22 03:07:39 PM PST 23 Nov 22 03:08:56 PM PST 23 2231375727 ps
T1770 /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.48789525966360175602933164598063463949693186541670568078884224865906151727033 Nov 22 03:05:56 PM PST 23 Nov 22 03:07:27 PM PST 23 4856075727 ps
T1771 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.70583392710111029858263496030604437130465893671002694757333199678038550300183 Nov 22 03:03:48 PM PST 23 Nov 22 03:09:01 PM PST 23 4815189184 ps
T1772 /workspace/coverage/cover_reg_top/56.xbar_stress_all.94043970459092377920498099743428955513154662525973323028405581922268735944271 Nov 22 03:08:33 PM PST 23 Nov 22 03:17:14 PM PST 23 13992004073 ps
T1773 /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.74727027250937960015985057194340768269144070103741855099594291230718111257794 Nov 22 03:13:22 PM PST 23 Nov 22 03:14:09 PM PST 23 1171215727 ps
T1774 /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.31845395436987329168939171941022188827220634820044617768144264849589020769038 Nov 22 03:06:37 PM PST 23 Nov 22 03:08:11 PM PST 23 7758585727 ps
T1775 /workspace/coverage/cover_reg_top/6.xbar_smoke.46633722278953188341641565915705056462510736766040513669984449375652261324282 Nov 22 03:03:32 PM PST 23 Nov 22 03:03:41 PM PST 23 196985727 ps
T1776 /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.24414078954959487192917600018831767455188036000103049461496646323180766155324 Nov 22 03:03:44 PM PST 23 Nov 22 03:04:34 PM PST 23 1176995727 ps
T1777 /workspace/coverage/cover_reg_top/17.xbar_error_random.28048874855791374545840739029904029989782529996170088487742347698471263766322 Nov 22 03:04:56 PM PST 23 Nov 22 03:06:07 PM PST 23 2231375727 ps
T1778 /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.81728192259154506456280375820403752114696406586049456138878824438874851054224 Nov 22 03:10:37 PM PST 23 Nov 22 03:11:28 PM PST 23 1176995727 ps
T1779 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.68672286222721890600996324036941522153527016384962644409523756051775330631914 Nov 22 03:11:21 PM PST 23 Nov 22 03:19:23 PM PST 23 13999524073 ps
T1780 /workspace/coverage/cover_reg_top/36.xbar_access_same_device.63545284827190259101473976387988171557759733386368576477156756958156095553267 Nov 22 03:06:30 PM PST 23 Nov 22 03:08:17 PM PST 23 2590995727 ps
T1781 /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.94465256616891470825970729938804924382032145816739923763483823506818090551265 Nov 22 03:06:29 PM PST 23 Nov 22 03:15:18 PM PST 23 13999524073 ps
T1782 /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.65964904352756857694386645948169824363495805030439166712247073995290756365987 Nov 22 03:06:39 PM PST 23 Nov 22 03:24:47 PM PST 23 60576345727 ps
T1783 /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.37981470318948379771595353525298528241309334859066198842890816152757443401741 Nov 22 03:06:13 PM PST 23 Nov 22 03:26:14 PM PST 23 97702135727 ps
T1784 /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.108545434004923013371259409891050312938406778300029665065162281017037264402267 Nov 22 03:10:08 PM PST 23 Nov 22 03:11:36 PM PST 23 7758585727 ps
T1785 /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.53341195634565584701477911527014471919161910757452699663223979047805090775913 Nov 22 03:03:43 PM PST 23 Nov 22 03:05:09 PM PST 23 7758585727 ps
T1786 /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.79332197030217538905699677670323171585026770018783465449694314831839209279916 Nov 22 03:08:26 PM PST 23 Nov 22 03:09:53 PM PST 23 4856075727 ps
T1787 /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.61021380322810007919853126962877076344826146649541021788519309273010571220633 Nov 22 03:08:29 PM PST 23 Nov 22 03:09:15 PM PST 23 1171215727 ps
T1788 /workspace/coverage/cover_reg_top/77.xbar_error_random.33883211170199315037448721333835521850464852785081673107312731074686510088690 Nov 22 03:10:54 PM PST 23 Nov 22 03:12:13 PM PST 23 2231375727 ps
T1789 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.10279137323135216143390741254351764251355816945304937417906571763635407678383 Nov 22 03:10:36 PM PST 23 Nov 22 03:16:50 PM PST 23 4815189184 ps
T1790 /workspace/coverage/cover_reg_top/26.xbar_same_source.87632074507745844022813482292616868942918121635059462284537713747440251006053 Nov 22 03:05:39 PM PST 23 Nov 22 03:06:52 PM PST 23 2498784073 ps
T1791 /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.67403322349664315145485792668792797081662231929853570734592097612775525971165 Nov 22 03:07:45 PM PST 23 Nov 22 03:26:04 PM PST 23 97702135727 ps
T1792 /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.54080940756218630773854715868387410605274661541415963485368363929756928938434 Nov 22 03:08:47 PM PST 23 Nov 22 03:13:58 PM PST 23 4815189184 ps
T1793 /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.108525395687523560859725744483840251423227171398330266907042871566337527272805 Nov 22 03:12:51 PM PST 23 Nov 22 03:46:25 PM PST 23 115195295727 ps
T1794 /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.50219334484638336869929563663715087649910039763895397230323975303971675698051 Nov 22 03:07:50 PM PST 23 Nov 22 03:41:26 PM PST 23 115195295727 ps
T1795 /workspace/coverage/cover_reg_top/43.xbar_stress_all.38150935174001632839433877104834377823037884864977259378607732872861055631831 Nov 22 03:07:25 PM PST 23 Nov 22 03:15:59 PM PST 23 13992004073 ps
T1796 /workspace/coverage/cover_reg_top/64.xbar_stress_all.13658428599965730957394392190553481524927178226980960071660770761581380988380 Nov 22 03:09:47 PM PST 23 Nov 22 03:18:21 PM PST 23 13992004073 ps
T1797 /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.81998671304750658250712133433418220859532735052008188360507249683780590872168 Nov 22 03:05:55 PM PST 23 Nov 22 03:07:27 PM PST 23 7758585727 ps
T1798 /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.40170515140167680015783599585429303241563552649075501715751758043380856568762 Nov 22 03:06:59 PM PST 23 Nov 22 03:08:32 PM PST 23 7758585727 ps
T1799 /workspace/coverage/cover_reg_top/92.xbar_error_random.69744017197731115245309631623841954985463407610464363583788052412959802539254 Nov 22 03:12:56 PM PST 23 Nov 22 03:14:11 PM PST 23 2231375727 ps
T1800 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.78654269532187548314944859342210444243632105182697215024589587713385048719430 Nov 22 03:09:53 PM PST 23 Nov 22 03:16:26 PM PST 23 4815189184 ps
T1801 /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.108913922744548341931046843387689740908221872611682640707481290182788670028967 Nov 22 03:07:34 PM PST 23 Nov 22 03:26:23 PM PST 23 60576345727 ps
T1802 /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.41715693917661311165423675142968854646897084937605424605722244916932457142890 Nov 22 03:08:37 PM PST 23 Nov 22 03:09:25 PM PST 23 1176995727 ps
T1803 /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.63496400222761341792348990201762243219664244874466196725460245606112434461890 Nov 22 03:05:47 PM PST 23 Nov 22 03:06:35 PM PST 23 556965727 ps
T1804 /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.62635289400826322320650452106071031233708278535406792534444435000693468806609 Nov 22 03:10:49 PM PST 23 Nov 22 03:12:22 PM PST 23 4856075727 ps
T1805 /workspace/coverage/cover_reg_top/26.chip_tl_errors.36181468523105321581038101645265600592608295036522460198602217191180907819234 Nov 22 03:05:51 PM PST 23 Nov 22 03:08:42 PM PST 23 3069924257 ps
T1806 /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.111463476728612878116695584790970506499614246124107317743351692120268967927761 Nov 22 03:08:40 PM PST 23 Nov 22 03:42:21 PM PST 23 115195295727 ps
T1807 /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3347541223056431737152867827311646139996160685756337249722306251397258881878 Nov 22 03:10:45 PM PST 23 Nov 22 03:44:32 PM PST 23 115195295727 ps
T1808 /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.107653703829504372869153902686707474173598520387579838498607415353216531869989 Nov 22 03:03:56 PM PST 23 Nov 22 03:11:58 PM PST 23 13999524073 ps
T1809 /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.64970316132992344323439141266531544126304034692716222314484908581731695907943 Nov 22 03:08:52 PM PST 23 Nov 22 03:26:12 PM PST 23 60576345727 ps
T1810 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.52655552867141978001411975332144596766474681062488804808399069170671400799094 Nov 22 03:12:38 PM PST 23 Nov 22 03:17:43 PM PST 23 4815189184 ps
T1811 /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.56263195553032873414724027068128899183999928163711678930149701311574199217538 Nov 22 03:08:45 PM PST 23 Nov 22 03:09:31 PM PST 23 1171215727 ps
T1812 /workspace/coverage/cover_reg_top/7.xbar_smoke.4644101245506458657074149117809137963374638951481475845727301730253240235675 Nov 22 03:03:54 PM PST 23 Nov 22 03:04:02 PM PST 23 196985727 ps
T1813 /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.106707302949840973507323739406118963916773803516851377440609573339646802842568 Nov 22 03:07:12 PM PST 23 Nov 22 03:07:59 PM PST 23 556965727 ps
T1814 /workspace/coverage/cover_reg_top/0.xbar_error_random.113871381355182702495857302448044629235990852634881794182843979527077012471242 Nov 22 03:03:41 PM PST 23 Nov 22 03:04:50 PM PST 23 2231375727 ps
T1815 /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.8910856270173779148315479430632250405336325668752580917468612364993364332506 Nov 22 03:03:56 PM PST 23 Nov 22 03:04:42 PM PST 23 556965727 ps
T1816 /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.102457168449144508066888935450951793501561571978770765128520863417145180263880 Nov 22 03:11:43 PM PST 23 Nov 22 03:44:44 PM PST 23 115195295727 ps
T1817 /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.72269243687560915038331910293697094736476298406874713387521326387634191022325 Nov 22 03:03:43 PM PST 23 Nov 22 03:21:52 PM PST 23 97702135727 ps
T1818 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.88070693343669280256467290224802273265661964300040033388283282053681185614077 Nov 22 03:04:19 PM PST 23 Nov 22 03:09:41 PM PST 23 4815189184 ps
T1819 /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.89803339893804877316031125270062784004420593160995217875973665963539871607382 Nov 22 03:07:36 PM PST 23 Nov 22 03:26:34 PM PST 23 60576345727 ps
T1820 /workspace/coverage/cover_reg_top/44.xbar_access_same_device.104994326086979242256804238796667370468769911378458273612035893730821897490606 Nov 22 03:07:35 PM PST 23 Nov 22 03:09:19 PM PST 23 2590995727 ps
T1821 /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1712547315681494677558966199979450424296681103798097865117380502964237401128 Nov 22 03:08:42 PM PST 23 Nov 22 03:26:53 PM PST 23 97702135727 ps
T1822 /workspace/coverage/cover_reg_top/9.xbar_same_source.115714968513942458393094570783340710180604009848078625482959694551101366223247 Nov 22 03:03:48 PM PST 23 Nov 22 03:04:59 PM PST 23 2498784073 ps
T1823 /workspace/coverage/cover_reg_top/22.xbar_error_random.93333169478389929363514782948800969125324318065101439294810643389349510838614 Nov 22 03:05:43 PM PST 23 Nov 22 03:06:57 PM PST 23 2231375727 ps
T1824 /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.47193872429476743379063818013012662364736890395142575167593380919977206483909 Nov 22 03:10:41 PM PST 23 Nov 22 03:11:29 PM PST 23 556965727 ps
T1825 /workspace/coverage/cover_reg_top/3.chip_tl_errors.78304913536953359952669046840394687827733040492485334612065868317702945711687 Nov 22 03:03:48 PM PST 23 Nov 22 03:07:15 PM PST 23 3069924257 ps
T1826 /workspace/coverage/cover_reg_top/36.xbar_error_random.64040385932309626347121948663228318368431829110352707336063990662671363974789 Nov 22 03:06:30 PM PST 23 Nov 22 03:07:44 PM PST 23 2231375727 ps
T1827 /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.32859488419737019964126329745390824312399323642373253113104517208471145536862 Nov 22 03:05:31 PM PST 23 Nov 22 03:06:18 PM PST 23 556965727 ps
T1828 /workspace/coverage/cover_reg_top/19.xbar_same_source.58232707980254191248946822693902667462866014260397461106681162842781845356467 Nov 22 03:05:12 PM PST 23 Nov 22 03:06:25 PM PST 23 2498784073 ps
T1829 /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.37939007646612713934112834201937000022333084634097245455974634504455390986949 Nov 22 03:13:19 PM PST 23 Nov 22 03:14:09 PM PST 23 1176995727 ps
T1830 /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.108751758477151193290022390798700142986704716283031536903223862925379639831618 Nov 22 03:09:47 PM PST 23 Nov 22 03:29:03 PM PST 23 97702135727 ps
T1831 /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.86239777577655109701203915472951124882533987183341571678733225541064669966358 Nov 22 03:03:39 PM PST 23 Nov 22 03:34:27 PM PST 23 115195295727 ps
T1832 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.68912111517023082025758750121730205972495784919526094802572995640723506312454 Nov 22 03:10:54 PM PST 23 Nov 22 03:15:55 PM PST 23 4815189184 ps
T1833 /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.8791745073574624838261954620191696305235873221696543867310430949134034815810 Nov 22 03:05:46 PM PST 23 Nov 22 03:36:26 PM PST 23 115195295727 ps
T1834 /workspace/coverage/cover_reg_top/70.xbar_access_same_device.67981412619390557575376165121821362663851072615511110144070458433229811839875 Nov 22 03:10:19 PM PST 23 Nov 22 03:12:06 PM PST 23 2590995727 ps
T1835 /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.9418154724008372216938165733593832294149281287546796753470902658037310448341 Nov 22 03:05:50 PM PST 23 Nov 22 03:39:56 PM PST 23 115195295727 ps
T1836 /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.40728650025544807635576072937296182477805577905635900738380899045637362466147 Nov 22 03:04:24 PM PST 23 Nov 22 03:05:48 PM PST 23 7758585727 ps
T1837 /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.72176831282002239686814756100334188185996611619626527475727469517324977388859 Nov 22 03:09:58 PM PST 23 Nov 22 03:10:45 PM PST 23 556965727 ps
T1838 /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.106037384725786740413109340775547910043796401720711232077194543362540968476880 Nov 22 03:07:42 PM PST 23 Nov 22 03:08:40 PM PST 23 556965727 ps
T1839 /workspace/coverage/cover_reg_top/77.xbar_smoke.9651980841719575782415320623890385127141001663097190932770062382664324877303 Nov 22 03:10:43 PM PST 23 Nov 22 03:10:53 PM PST 23 196985727 ps
T1840 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.23888088566862454751038739491105958425727916051542163465646501902599847300893 Nov 22 03:09:18 PM PST 23 Nov 22 03:15:49 PM PST 23 4815189184 ps
T1841 /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.105908136690461634282677688325167952386129200301174801612505757137825962147061 Nov 22 03:09:52 PM PST 23 Nov 22 03:11:17 PM PST 23 7758585727 ps
T1842 /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.107857849061974982074851768448465965716908994023078452447615208271280940687879 Nov 22 03:03:34 PM PST 23 Nov 22 03:04:59 PM PST 23 4856075727 ps
T1843 /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.26467184248875365951991572175242109492620210429342128075023274546394503890985 Nov 22 03:06:43 PM PST 23 Nov 22 03:40:30 PM PST 23 115195295727 ps
T1844 /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.103178010646566188496015555179476284217263152309115658354643744745844776634256 Nov 22 03:12:46 PM PST 23 Nov 22 03:13:34 PM PST 23 1176995727 ps
T1845 /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.115072677043837883358180541985327615048974850502183618662919926433615566405342 Nov 22 03:07:24 PM PST 23 Nov 22 03:08:13 PM PST 23 1171215727 ps
T1846 /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.12551830171126597443035449955544475551981475206314601812585718004318898471293 Nov 22 03:11:24 PM PST 23 Nov 22 03:12:13 PM PST 23 1176995727 ps
T1847 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.17095304192878839743030664143789548324554585178986510048468795725887425251503 Nov 22 03:05:55 PM PST 23 Nov 22 03:12:11 PM PST 23 4815189184 ps
T1848 /workspace/coverage/cover_reg_top/94.xbar_stress_all.78889276418538327285023784607489447708202605154693547907945865001674185741293 Nov 22 03:13:18 PM PST 23 Nov 22 03:21:58 PM PST 23 13992004073 ps
T1849 /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.72037916561910136333817156461919845035287284493889692473591888437536352933565 Nov 22 03:08:27 PM PST 23 Nov 22 03:41:46 PM PST 23 115195295727 ps
T1850 /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.30000041809927494049028779623383569367901670245842037489178593769344463998096 Nov 22 03:10:34 PM PST 23 Nov 22 03:28:53 PM PST 23 60576345727 ps
T1851 /workspace/coverage/cover_reg_top/11.xbar_access_same_device.61968396332981418182388701000742855864729193220733452373928743333458583860672 Nov 22 03:03:52 PM PST 23 Nov 22 03:05:48 PM PST 23 2590995727 ps
T1852 /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3976203047366663453521350083736740395133902437808347659731508844784932661556 Nov 22 03:08:49 PM PST 23 Nov 22 03:10:19 PM PST 23 4856075727 ps
T1853 /workspace/coverage/cover_reg_top/60.xbar_error_random.96995966090394673050981511654817540794222160611810351743799284392698674750047 Nov 22 03:08:41 PM PST 23 Nov 22 03:09:57 PM PST 23 2231375727 ps
T1854 /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.59834279130335783319406159618099765347149756291933733650932237436898093692083 Nov 22 03:08:35 PM PST 23 Nov 22 03:10:05 PM PST 23 4856075727 ps
T1855 /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.56676171588476556943920578656879031356887227658318198666685847466911361352086 Nov 22 03:07:35 PM PST 23 Nov 22 03:08:27 PM PST 23 1176995727 ps
T1856 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.22174792944856586488240248425942224728400849582454222400944791616510767635186 Nov 22 03:07:44 PM PST 23 Nov 22 03:13:49 PM PST 23 4815189184 ps
T1857 /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.4942847547815717795567687514517700578964409039857741909055275235987597419099 Nov 22 03:06:27 PM PST 23 Nov 22 03:06:34 PM PST 23 45555727 ps
T1858 /workspace/coverage/cover_reg_top/39.xbar_access_same_device.17034868402969641932791694703767476671806089421659615019520662033550423921685 Nov 22 03:06:48 PM PST 23 Nov 22 03:08:48 PM PST 23 2590995727 ps
T1859 /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.83111825313927504393655332519543022338146617023607289520865686377776829816188 Nov 22 03:04:00 PM PST 23 Nov 22 03:21:56 PM PST 23 60576345727 ps
T1860 /workspace/coverage/cover_reg_top/71.xbar_error_random.48160014415257374309481673058314612436808463628159922828162077939829854465757 Nov 22 03:10:20 PM PST 23 Nov 22 03:11:32 PM PST 23 2231375727 ps
T1861 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.88558322275841748399109515658430915661350944883407272406071619238116363692468 Nov 22 03:10:35 PM PST 23 Nov 22 03:18:59 PM PST 23 13999524073 ps
T1862 /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.45226759621531852032816471865288548524557434027273557720331372468007234397742 Nov 22 03:05:35 PM PST 23 Nov 22 03:06:26 PM PST 23 1176995727 ps
T1863 /workspace/coverage/cover_reg_top/8.xbar_stress_all.71686388279830576950941744795487643828403424430056799379265704658468287950962 Nov 22 03:03:47 PM PST 23 Nov 22 03:13:31 PM PST 23 13992004073 ps
T1864 /workspace/coverage/cover_reg_top/93.xbar_smoke.89086514144763954103673116744153799216436283501309234795507686667786347304098 Nov 22 03:12:57 PM PST 23 Nov 22 03:13:07 PM PST 23 196985727 ps
T1865 /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.102867449606603668720351512727940224982993181471551459155219672587973063146389 Nov 22 03:08:43 PM PST 23 Nov 22 03:27:30 PM PST 23 97702135727 ps
T1866 /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.38931396959388932416765682587543562335031402054130442834338207512450235609764 Nov 22 03:12:01 PM PST 23 Nov 22 03:12:56 PM PST 23 556965727 ps
T1867 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.43268520726186906307243303059789933575941427566673617599508110138313314295358 Nov 22 03:10:08 PM PST 23 Nov 22 03:15:14 PM PST 23 4815189184 ps
T1868 /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.73446556495808474890067222187461649937449172735545798078103250526578423427493 Nov 22 03:05:38 PM PST 23 Nov 22 03:07:06 PM PST 23 4856075727 ps
T1869 /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.78912090471161567518937026077165819961380425478776103744721484082621484989065 Nov 22 03:06:20 PM PST 23 Nov 22 03:07:08 PM PST 23 556965727 ps
T1870 /workspace/coverage/cover_reg_top/97.xbar_random.62888873780578714898536957564050183763749468180080227729335050375870455336693 Nov 22 03:13:51 PM PST 23 Nov 22 03:15:08 PM PST 23 2231375727 ps
T1871 /workspace/coverage/cover_reg_top/54.xbar_same_source.80770055187626244906151068027095136303058818808398031207499585736246796608981 Nov 22 03:08:42 PM PST 23 Nov 22 03:09:58 PM PST 23 2498784073 ps
T1872 /workspace/coverage/cover_reg_top/27.chip_tl_errors.51914879289197636761753974082574676634482146833342944108927288189680669820756 Nov 22 03:05:56 PM PST 23 Nov 22 03:08:48 PM PST 23 3069924257 ps
T1873 /workspace/coverage/cover_reg_top/1.xbar_same_source.57983501511406780142997181645503302973253334270761376283344240833600856807136 Nov 22 03:02:59 PM PST 23 Nov 22 03:04:12 PM PST 23 2498784073 ps
T1874 /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.24980014236881749289033550279854064137386878948112265468899487755415901082299 Nov 22 03:12:25 PM PST 23 Nov 22 03:46:44 PM PST 23 115195295727 ps
T1875 /workspace/coverage/cover_reg_top/51.xbar_smoke.100339140850008443633214366765652461063156163694511785884744155707976630042724 Nov 22 03:07:57 PM PST 23 Nov 22 03:08:06 PM PST 23 196985727 ps
T1876 /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.67199185322508219392829471379417371520142421319962525809372435532256509471417 Nov 22 03:04:57 PM PST 23 Nov 22 03:06:29 PM PST 23 4856075727 ps
T1877 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.87525883604990154197714532991770718190383315852055370252310817459888229324876 Nov 22 03:05:33 PM PST 23 Nov 22 03:11:26 PM PST 23 4815189184 ps
T1878 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.89700128935543827426910446671336297177106496575773862504639996508442478107545 Nov 22 03:12:37 PM PST 23 Nov 22 03:18:50 PM PST 23 4815189184 ps
T1879 /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.102278565974787104748666545449904265050701720904161896074101537834571769042470 Nov 22 03:08:32 PM PST 23 Nov 22 03:09:15 PM PST 23 1171215727 ps
T1880 /workspace/coverage/cover_reg_top/16.chip_csr_rw.98155653596131336469584941986753772348826327594088273573453598195058948297737 Nov 22 03:05:24 PM PST 23 Nov 22 03:14:38 PM PST 23 5924944675 ps
T1881 /workspace/coverage/cover_reg_top/83.xbar_access_same_device.78494124958523760970056291652170944636957112588713683922647418968027812944197 Nov 22 03:11:46 PM PST 23 Nov 22 03:13:36 PM PST 23 2590995727 ps
T1882 /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.69774251791490852028347830411314571359238238414176085142644119919257196660731 Nov 22 03:06:10 PM PST 23 Nov 22 03:07:43 PM PST 23 7758585727 ps
T1883 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.18633851337787781571590842659164256680133859812939778979500468982992990169006 Nov 22 03:05:47 PM PST 23 Nov 22 03:14:49 PM PST 23 13999524073 ps
T1884 /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.6281720918606593540537660823167259348183316682160139715463743800438345643948 Nov 22 03:05:34 PM PST 23 Nov 22 03:38:06 PM PST 23 115195295727 ps
T1885 /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.43636538334677232089052183991990056796287106323651931275410670357283264766795 Nov 22 03:10:23 PM PST 23 Nov 22 03:11:10 PM PST 23 1171215727 ps
T1886 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.109219144623838008421810047497243319523359496062119495483577918699286069934752 Nov 22 03:04:19 PM PST 23 Nov 22 03:10:01 PM PST 23 4815189184 ps
T1887 /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.42837681905194416616184955883348540530179899757375863993338041920203839486753 Nov 22 03:08:48 PM PST 23 Nov 22 03:09:37 PM PST 23 556965727 ps
T1888 /workspace/coverage/cover_reg_top/53.xbar_stress_all.40028762596126129476361271806011828636658927244702605519725711454209597281180 Nov 22 03:08:26 PM PST 23 Nov 22 03:17:50 PM PST 23 13992004073 ps
T1889 /workspace/coverage/cover_reg_top/65.xbar_access_same_device.29643922165282733432697057632825072931297972963542945389521506661062627055057 Nov 22 03:09:46 PM PST 23 Nov 22 03:11:39 PM PST 23 2590995727 ps
T1890 /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.104217725949935000100094522367846595742477314362018030461644925131209028581370 Nov 22 03:10:32 PM PST 23 Nov 22 03:43:42 PM PST 23 115195295727 ps
T1891 /workspace/coverage/cover_reg_top/72.xbar_error_random.52575784305194322143646242121190414254963777809363059058640092987623054621197 Nov 22 03:10:30 PM PST 23 Nov 22 03:11:46 PM PST 23 2231375727 ps
T1892 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.9164938980754536431246614827906003157249808905190305725114051198444674576099 Nov 22 03:03:05 PM PST 23 Nov 22 03:09:18 PM PST 23 4815189184 ps
T1893 /workspace/coverage/cover_reg_top/0.xbar_same_source.11265774675437655664021985564958294402056546990332870205071350798682125401541 Nov 22 03:03:40 PM PST 23 Nov 22 03:04:48 PM PST 23 2498784073 ps
T1894 /workspace/coverage/cover_reg_top/30.xbar_smoke.81085372819484960655251979273189920244227844811878634184828230790998232553570 Nov 22 03:05:55 PM PST 23 Nov 22 03:06:04 PM PST 23 196985727 ps
T1895 /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.40703431404419760132981903528598951463391716107748825913860066826611311254080 Nov 22 03:13:34 PM PST 23 Nov 22 03:32:42 PM PST 23 97702135727 ps
T1896 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.84253438814460937654397108470506126918220625834603427923924914892062080032808 Nov 22 03:06:14 PM PST 23 Nov 22 03:12:55 PM PST 23 4815189184 ps
T1897 /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.16891199399108423789762047011369460056917296014388458840288832203672641737119 Nov 22 03:13:16 PM PST 23 Nov 22 03:13:23 PM PST 23 45555727 ps
T1898 /workspace/coverage/cover_reg_top/43.xbar_error_random.115529395207756933767065091281476207267176595175545347023842716376171381203130 Nov 22 03:07:22 PM PST 23 Nov 22 03:08:35 PM PST 23 2231375727 ps
T1899 /workspace/coverage/cover_reg_top/86.xbar_random.46140376599245248272068954771593641096839745158991061032750153883728222304808 Nov 22 03:12:09 PM PST 23 Nov 22 03:13:38 PM PST 23 2231375727 ps
T1900 /workspace/coverage/cover_reg_top/13.xbar_same_source.60444403010060794799216745533009895809588107289292204826962828380824917243686 Nov 22 03:04:19 PM PST 23 Nov 22 03:05:31 PM PST 23 2498784073 ps
T1901 /workspace/coverage/cover_reg_top/32.xbar_same_source.56746510402188595971986628959337974726904203116855588614638178978163440483452 Nov 22 03:06:07 PM PST 23 Nov 22 03:07:25 PM PST 23 2498784073 ps
T1902 /workspace/coverage/cover_reg_top/6.xbar_error_random.46314011507574365885078185264076012092513664005285892474809397745289791931712 Nov 22 03:03:30 PM PST 23 Nov 22 03:04:43 PM PST 23 2231375727 ps
T1903 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.81589631645254708292868559076781938317765796246023148872104127710773805215013 Nov 22 03:05:32 PM PST 23 Nov 22 03:13:17 PM PST 23 13999524073 ps
T1904 /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.21954289151328755872646753529568179872443416441054142401988951783979724020800 Nov 22 03:09:17 PM PST 23 Nov 22 03:09:23 PM PST 23 45555727 ps
T1905 /workspace/coverage/cover_reg_top/13.xbar_smoke.30566036498950474107076770103195863495370324818607310657569966429560013857674 Nov 22 03:04:08 PM PST 23 Nov 22 03:04:17 PM PST 23 196985727 ps
T1906 /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.22450761522172262138990260751261547065452185580917094682572770516855019539498 Nov 22 03:05:45 PM PST 23 Nov 22 03:40:10 PM PST 23 115195295727 ps
T1907 /workspace/coverage/cover_reg_top/11.xbar_smoke.4256138613248284896704369128630871178178648719534499034623685719849090214406 Nov 22 03:03:48 PM PST 23 Nov 22 03:03:56 PM PST 23 196985727 ps
T1908 /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.102493748534967926251546250632467025133670998327628913624502650155135194163091 Nov 22 03:10:08 PM PST 23 Nov 22 03:10:15 PM PST 23 45555727 ps
T1909 /workspace/coverage/cover_reg_top/96.xbar_random.41984586467423387669726167824255887280494305852923987181063749042019763984557 Nov 22 03:13:17 PM PST 23 Nov 22 03:14:34 PM PST 23 2231375727 ps
T1910 /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.31484472114771954372358584007844909661539020544341688934587320774839165946233 Nov 22 03:11:28 PM PST 23 Nov 22 03:12:13 PM PST 23 1171215727 ps
T1911 /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.10022574549386680646392562339519905826430997842010541605546028395575892181651 Nov 22 03:08:50 PM PST 23 Nov 22 03:10:21 PM PST 23 4856075727 ps
T1912 /workspace/coverage/cover_reg_top/56.xbar_random.28408149967428175776248732232288641922682837446914995013938038673041563321968 Nov 22 03:08:28 PM PST 23 Nov 22 03:09:46 PM PST 23 2231375727 ps
T1913 /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.13522221228776880445949626929851071681815152325822052989310844089020873656000 Nov 22 03:13:43 PM PST 23 Nov 22 03:14:29 PM PST 23 1171215727 ps
T1914 /workspace/coverage/cover_reg_top/18.chip_tl_errors.31177438292083680559866166221471077166652452263768764458379932647705236160902 Nov 22 03:05:35 PM PST 23 Nov 22 03:08:49 PM PST 23 3069924257 ps
T1915 /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.28905121356157637030945348548006275308317350695896638434673059649762701913432 Nov 22 03:10:32 PM PST 23 Nov 22 03:11:21 PM PST 23 1176995727 ps
T1916 /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.39346779131857716883725992135244261604412908278048010252711309628626423853042 Nov 22 03:03:33 PM PST 23 Nov 22 03:04:58 PM PST 23 7758585727 ps
T1917 /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.64357231288318698745336485913921777311701795989311541606759559385708358538268 Nov 22 03:05:21 PM PST 23 Nov 22 03:13:32 PM PST 23 13999524073 ps
T1918 /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.13563059667096962143541338839217316861141709993275457634032619844820402329682 Nov 22 03:11:23 PM PST 23 Nov 22 03:12:51 PM PST 23 4856075727 ps
T1919 /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.83532463156025777169583911552215547394703490523128203625588859046890070912847 Nov 22 03:07:44 PM PST 23 Nov 22 03:07:54 PM PST 23 45555727 ps
T1920 /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.48984259220576799365207481157248772863507612691889534763678562690615276961087 Nov 22 03:05:47 PM PST 23 Nov 22 03:39:24 PM PST 23 115195295727 ps
T1921 /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.50110933450182880856704156651883521458816263311226795112601426155553590740193 Nov 22 03:10:31 PM PST 23 Nov 22 03:12:01 PM PST 23 4856075727 ps
T1922 /workspace/coverage/cover_reg_top/93.xbar_stress_all.42907931261684948681249647258473986175768716488152233100380924973383277967666 Nov 22 03:13:01 PM PST 23 Nov 22 03:21:10 PM PST 23 13992004073 ps
T1923 /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.13768331529097040281275735356930343594429706783646304168231832262137938897593 Nov 22 03:04:14 PM PST 23 Nov 22 03:09:51 PM PST 23 7234930891 ps
T1924 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.22774306149266198085892537616665886474709412859329923044069469589870743177353 Nov 22 03:07:24 PM PST 23 Nov 22 03:16:18 PM PST 23 13999524073 ps
T1925 /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.99924841426374623896178381066969005959448154849366005077787373884199462952914 Nov 22 03:12:09 PM PST 23 Nov 22 03:13:39 PM PST 23 7758585727 ps
T1926 /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.31615693625217065961243403506892887088763332847843383289178163278173409456789 Nov 22 03:07:58 PM PST 23 Nov 22 03:08:49 PM PST 23 1176995727 ps
T1927 /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.65522002096079607808522948006853976654590275081446669393504491722185105329101 Nov 22 03:11:26 PM PST 23 Nov 22 03:11:32 PM PST 23 45555727 ps

Test location /workspace/coverage/cover_reg_top/25.chip_tl_errors.108729388215825906447148288425738023753236019808014012623022428054278857089626
Short name T1
Test name
Test status
Simulation time 3069924257 ps
CPU time 184.43 seconds
Started Nov 22 03:05:30 PM PST 23
Finished Nov 22 03:08:35 PM PST 23
Peak memory 580504 kb
Host smart-c7ef9bc3-c927-42a4-aee6-7622f29f2bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108729388215825906447148288425738023753236019808014012623022428054278857089626 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.108729388215825906447148288425738023753236019808014012623022428054278857089626
Directory /workspace/25.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.4631220530083704396582537584373043535730987145193087422074679221285960150478
Short name T7
Test name
Test status
Simulation time 72959944675 ps
CPU time 9203.55 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 05:36:58 PM PST 23
Peak memory 625324 kb
Host smart-3b29572c-030c-4da5-a417-371a6c6f7589
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4631220530083704396582537584373043535730987145193
087422074679221285960150478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_aliasing.4631220530083704396582537584373043535730987145
193087422074679221285960150478
Directory /workspace/0.chip_csr_aliasing/latest

Test location /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.30862242836865989722723526159259891850772090523596388286882899805559220768146
Short name T14
Test name
Test status
Simulation time 4139861104 ps
CPU time 232.07 seconds
Started Nov 22 02:57:03 PM PST 23
Finished Nov 22 03:00:56 PM PST 23
Peak memory 632488 kb
Host smart-9f3007bf-87b8-48d8-8d95-2a78ddcbdfed
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308622428368659897227235261592598918507720905235963882868828998055
59220768146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 4.chip_padctrl_attributes.308622428368659897227235261592598918507
72090523596388286882899805559220768146
Directory /workspace/4.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.69505366346054619553806835497918684927468346416625692203706088544629496954137
Short name T51
Test name
Test status
Simulation time 13999524073 ps
CPU time 513.07 seconds
Started Nov 22 03:04:20 PM PST 23
Finished Nov 22 03:12:54 PM PST 23
Peak memory 555740 kb
Host smart-312b96d8-1c5d-46dd-806e-b549541bf718
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69505366346054619553806835497918684927468346416625692203706088544629496954137 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.69505366346054619553806835497918684927468346416625692203706088544629496954137
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.64739456377403464847649034997225412634351580991118193699845629195010930371048
Short name T70
Test name
Test status
Simulation time 115195295727 ps
CPU time 2040.69 seconds
Started Nov 22 03:09:47 PM PST 23
Finished Nov 22 03:43:48 PM PST 23
Peak memory 554816 kb
Host smart-3a4cae38-ef4f-4d03-aaec-635d1f62adba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64739456377403464847649034997225412634351580991118193699845629195010930371048 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device_slow_rsp.64739456377403464847649034997225412634351580991118193699845629195010930371048
Directory /workspace/65.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_rw.108499982830464528946269141839163087321524093684085938146257384744788918019444
Short name T2
Test name
Test status
Simulation time 5924944675 ps
CPU time 571.31 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 03:13:05 PM PST 23
Peak memory 580504 kb
Host smart-bfd8a5ca-093d-4b62-8877-9486d6280d05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108499982830464528946269141839163087321524093684085938146257384744788918019444 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.108499982830464528946269141839163087321524093684085938146257384744788918019444
Directory /workspace/2.chip_csr_rw/latest

Test location /workspace/coverage/default/0.chip_jtag_csr_rw.82666310635438362931022012325167268063804073510308049291049505028557431125957
Short name T19
Test name
Test status
Simulation time 19824942265 ps
CPU time 1989.14 seconds
Started Nov 22 02:57:57 PM PST 23
Finished Nov 22 03:31:07 PM PST 23
Peak memory 587424 kb
Host smart-076824b0-6732-4e19-85d5-65cf024f1f07
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82666310635438362931022012325167268063804073510308049291049505028
557431125957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_csr_rw.826663106354383629310220123251672680638040735103080492910495050
28557431125957
Directory /workspace/0.chip_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.37914573050873893315509927279478909633777139773334848782606123250802928006307
Short name T42
Test name
Test status
Simulation time 7234930891 ps
CPU time 309.48 seconds
Started Nov 22 03:03:28 PM PST 23
Finished Nov 22 03:08:38 PM PST 23
Peak memory 622472 kb
Host smart-de66beeb-e834-494d-8266-f67dfb73a5e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791457305087389331550992727947
8909633777139773334848782606123250802928006307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.3791457305087
3893315509927279478909633777139773334848782606123250802928006307
Directory /workspace/2.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.101184752666135257390191357076404893938800322968469264194900226658313261131955
Short name T12
Test name
Test status
Simulation time 5984936856 ps
CPU time 324.07 seconds
Started Nov 22 03:03:28 PM PST 23
Finished Nov 22 03:08:53 PM PST 23
Peak memory 641820 kb
Host smart-954bceca-bce3-4edb-9de1-262fd17173b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101184752666135257390191357076404893938800322968469264194900226658313261131955
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_reset.101184752666135257390191357076404893938800322968469264194900226658313261131955
Directory /workspace/3.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.87174581946212533951226459826129893742279676474080266487815954887779351945489
Short name T62
Test name
Test status
Simulation time 556965727 ps
CPU time 47.33 seconds
Started Nov 22 03:05:14 PM PST 23
Finished Nov 22 03:06:02 PM PST 23
Peak memory 553708 kb
Host smart-681c1561-d794-445d-af2a-9c2fd6a820f8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87174581946212533951226459826129893742279676474080266487815954887779351945489 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.87174581946212533951226459826129893742279676474080266487815954887779351945489
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.38819300538155075132093940083695486907614465085625414881067400927824701724259
Short name T4
Test name
Test status
Simulation time 4815189184 ps
CPU time 382.7 seconds
Started Nov 22 03:04:09 PM PST 23
Finished Nov 22 03:10:33 PM PST 23
Peak memory 557320 kb
Host smart-f4e3035b-f3d2-43da-8e2c-76bbaf35f30e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38819300538155075132093940083695486907614465085625414881067400927824701724259 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.38819300538155075132093940083695486907614465085625414881067400
927824701724259
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all.47583897312403603942382159833840451176454635979258234310770708002722398241614
Short name T59
Test name
Test status
Simulation time 13992004073 ps
CPU time 491.96 seconds
Started Nov 22 03:13:29 PM PST 23
Finished Nov 22 03:21:41 PM PST 23
Peak memory 555844 kb
Host smart-98e5d8d7-b009-4980-97d8-75e185a5e0d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47583897312403603942382159833840451176454635979258234310770708002722398241614 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.47583897312403603942382159833840451176454635979258234310770708002722398241614
Directory /workspace/95.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.25302861032816795007375528087019931655060888129233892161888192552261277708353
Short name T78
Test name
Test status
Simulation time 97702135727 ps
CPU time 1154.83 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:25:03 PM PST 23
Peak memory 553596 kb
Host smart-f57df273-cd20-47c3-aeb5-dd8c9581346e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25302861032816795007375528087019931655060888129233892161888192552261277708353 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.25302861032816795007375528087019931655060888129233892161888192552261277708353
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.62666471107198800639838191996609324093467057095337660850657143266162597933805
Short name T40
Test name
Test status
Simulation time 10669917822 ps
CPU time 470.01 seconds
Started Nov 22 03:03:06 PM PST 23
Finished Nov 22 03:11:00 PM PST 23
Peak memory 576144 kb
Host smart-92d27d33-aa37-46e3-8b42-652f5a27a9e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62666471107198800639838191996609324093467057095337660850657143266162597
933805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.626664711071988006398381919966093240934670570953376608506
57143266162597933805
Directory /workspace/2.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.27764157554616651002963955850649742537055516898290864147778022606506913957304
Short name T26
Test name
Test status
Simulation time 30604932618 ps
CPU time 3213.88 seconds
Started Nov 22 03:03:07 PM PST 23
Finished Nov 22 03:56:44 PM PST 23
Peak memory 580536 kb
Host smart-686031c2-18d9-4d62-a808-9d803eaa9ca9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776415755461665100296395585064974253
7055516898290864147778022606506913957304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2776415755461665100296395
5850649742537055516898290864147778022606506913957304
Directory /workspace/2.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.73990001848247590627056082631281954154237720431247056862430093085689235212044
Short name T109
Test name
Test status
Simulation time 4815189184 ps
CPU time 316.93 seconds
Started Nov 22 03:05:52 PM PST 23
Finished Nov 22 03:11:09 PM PST 23
Peak memory 559780 kb
Host smart-d1735413-fef0-4e31-b72a-c658b8d211dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73990001848247590627056082631281954154237720431247056862430093085689235212044 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.739900018482475906270560826312819541542377204312470568624300
93085689235212044
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_jtag_mem_access.101178099729684598940586658916239046619658135003303933438672393203401501856559
Short name T16
Test name
Test status
Simulation time 12899942265 ps
CPU time 1073.89 seconds
Started Nov 22 02:57:59 PM PST 23
Finished Nov 22 03:15:54 PM PST 23
Peak memory 587340 kb
Host smart-469fce4a-da56-4636-9a16-5e931497649f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101178099729684598940586658916239046619658135003303933438672393203401501856559 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.101178099729684598940586658916239046619658135003303933438672393203401501856559
Directory /workspace/0.chip_jtag_mem_access/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.21030060827038479142095696077876289734908717171394223706748199149084223131249
Short name T89
Test name
Test status
Simulation time 60576345727 ps
CPU time 1058.58 seconds
Started Nov 22 03:06:38 PM PST 23
Finished Nov 22 03:24:17 PM PST 23
Peak memory 553632 kb
Host smart-77e284ce-1392-4df6-8bc9-906d484e9eec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030060827038479142095696077876289734908717171394223706748199149084223131249 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.21030060827038479142095696077876289734908717171394223706748199149084223131249
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.55609720754002837184172953959103479628076269406829864444684601216265854393357
Short name T23
Test name
Test status
Simulation time 7954924257 ps
CPU time 789.04 seconds
Started Nov 22 03:03:03 PM PST 23
Finished Nov 22 03:16:13 PM PST 23
Peak memory 580532 kb
Host smart-2a939ff5-9f12-4429-ab56-0909903a4835
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556097207540028371841729539591
03479628076269406829864444684601216265854393357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.55609720754002837184172953
959103479628076269406829864444684601216265854393357
Directory /workspace/0.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.104114527850964417061536243683883393977179968101490744752465044661102870165879
Short name T218
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.1 seconds
Started Nov 22 03:04:23 PM PST 23
Finished Nov 22 03:05:09 PM PST 23
Peak memory 553808 kb
Host smart-2314b015-adb0-4c0d-a0b0-6cd7ff676319
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104114527850964417061536243683883393977179968101490744752465044661102870165879 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.104114527850964417061536243683883393977179968101490744752465044661102870165879
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.chip_tl_errors.9287339741444537730612858653334709612480110914938834469152573227318076619081
Short name T54
Test name
Test status
Simulation time 3069924257 ps
CPU time 218.93 seconds
Started Nov 22 03:05:18 PM PST 23
Finished Nov 22 03:08:58 PM PST 23
Peak memory 580600 kb
Host smart-0c7b5359-f271-4a06-b253-84fdf4c18508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9287339741444537730612858653334709612480110914938834469152573227318076619081 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.9287339741444537730612858653334709612480110914938834469152573227318076619081
Directory /workspace/23.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.93992039457897902111507267461213879571615103902769741280830286794523547403905
Short name T38
Test name
Test status
Simulation time 10375158790 ps
CPU time 367.89 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:09:46 PM PST 23
Peak memory 576792 kb
Host smart-2fd12479-71aa-4c54-818f-eb20eb00e028
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9399203945789790211150726746121387957161510390276974128
0830286794523547403905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.93992039457897902111507267461213879
571615103902769741280830286794523547403905
Directory /workspace/0.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_same_source.83345078422558585211112338744835497516859863164459927961297107945483956750626
Short name T113
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.69 seconds
Started Nov 22 03:04:25 PM PST 23
Finished Nov 22 03:05:39 PM PST 23
Peak memory 553656 kb
Host smart-e9a66021-9886-4ca6-8dd3-d806b8667be2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83345078422558585211112338744835497516859863164459927961297107945483956750626 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.83345078422558585211112338744835497516859863164459927961297107945483956750626
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.63283790725569878462565877000491357107382196227430311924752598604995551118985
Short name T124
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.25 seconds
Started Nov 22 03:04:20 PM PST 23
Finished Nov 22 03:05:04 PM PST 23
Peak memory 553508 kb
Host smart-4225ad33-7acb-4173-b12f-b4fba1b63aef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63283790725569878462565877000491357107382196227430311924752598604995551118985 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.63283790725569878462565877000491357107382196227430311924752598604995551118985
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.78651971853911108204342419714886902136290121405288839309528098378700098248181
Short name T41
Test name
Test status
Simulation time 10669917822 ps
CPU time 435.55 seconds
Started Nov 22 03:03:52 PM PST 23
Finished Nov 22 03:11:08 PM PST 23
Peak memory 576156 kb
Host smart-9e477b55-7970-450b-8858-da7681ca6c77
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78651971853911108204342419714886902136290121405288839309528098378700098
248181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.786519718539111082043424197148869021362901214052888393095
28098378700098248181
Directory /workspace/0.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.50705348921137859855257362466190007286341963074280165684467902525508141703431
Short name T1256
Test name
Test status
Simulation time 5984936856 ps
CPU time 313.67 seconds
Started Nov 22 03:03:42 PM PST 23
Finished Nov 22 03:08:57 PM PST 23
Peak memory 641776 kb
Host smart-141b609c-45d5-45b5-bab3-c5527b2922e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50705348921137859855257362466190007286341963074280165684467902525508141703431
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_reset.50705348921137859855257362466190007286341963074280165684467902525508141703431
Directory /workspace/0.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.115172610020496357170113264382854049012887627924812887168970914087641483559605
Short name T772
Test name
Test status
Simulation time 7234930891 ps
CPU time 333.86 seconds
Started Nov 22 03:03:49 PM PST 23
Finished Nov 22 03:09:23 PM PST 23
Peak memory 622516 kb
Host smart-09047973-f594-4d7f-aeb5-fb35a4a411ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151726100204963571701132643828
54049012887627924812887168970914087641483559605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.115172610020
496357170113264382854049012887627924812887168970914087641483559605
Directory /workspace/0.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_rw.54352794679301591291431415749594013306967692758505170818992129223358758018214
Short name T1622
Test name
Test status
Simulation time 5924944675 ps
CPU time 515.57 seconds
Started Nov 22 03:03:57 PM PST 23
Finished Nov 22 03:12:33 PM PST 23
Peak memory 580492 kb
Host smart-1de61f3b-0985-49dc-8b6c-3424fe765427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54352794679301591291431415749594013306967692758505170818992129223358758018214 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.54352794679301591291431415749594013306967692758505170818992129223358758018214
Directory /workspace/0.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.72961150516499106884011348497438365222408873485222187132440334263141030462838
Short name T785
Test name
Test status
Simulation time 30604932618 ps
CPU time 3095.41 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:55:08 PM PST 23
Peak memory 580480 kb
Host smart-5f6882da-0590-4d65-800f-4f7fe916ab70
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7296115051649910688401134849743836522
2408873485222187132440334263141030462838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.7296115051649910688401134
8497438365222408873485222187132440334263141030462838
Directory /workspace/0.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.chip_tl_errors.81131131388215311850164896954738155330902124472096730849763209874053636103287
Short name T1517
Test name
Test status
Simulation time 3069924257 ps
CPU time 178.24 seconds
Started Nov 22 03:03:48 PM PST 23
Finished Nov 22 03:06:47 PM PST 23
Peak memory 580520 kb
Host smart-256ec0c6-afba-4ef5-be38-ab1e7c757244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81131131388215311850164896954738155330902124472096730849763209874053636103287 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.81131131388215311850164896954738155330902124472096730849763209874053636103287
Directory /workspace/0.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device.77464341345110785684902858736591304165904139312308130721392421316320889180551
Short name T1145
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.92 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:05:28 PM PST 23
Peak memory 554696 kb
Host smart-6f0c54fa-8bf7-4d45-84cc-c65371a4aa4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77464341345110785684902858736591304165904139312308130721392421316320889180551 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.77464341345110785684902858736591304165904139312308130721392421316320889180551
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.107811979471988142211199338826476397651953862491547934653251704333019863043478
Short name T614
Test name
Test status
Simulation time 115195295727 ps
CPU time 1958.95 seconds
Started Nov 22 03:03:36 PM PST 23
Finished Nov 22 03:36:16 PM PST 23
Peak memory 554812 kb
Host smart-790742df-1868-4263-bd01-271f3a3ab8aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107811979471988142211199338826476397651953862491547934653251704333019863043478 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.107811979471988142211199338826476397651953862491547934653251704333019863043478
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.77603292448962743141652987285712379694402433830361466523656432133120861595124
Short name T322
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.91 seconds
Started Nov 22 03:03:58 PM PST 23
Finished Nov 22 03:04:42 PM PST 23
Peak memory 553468 kb
Host smart-7727d8a3-7663-4bce-b9fa-530faf457693
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77603292448962743141652987285712379694402433830361466523656432133120861595124 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.77603292448962743141652987285712379694402433830361466523656432133120861595124
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_random.113871381355182702495857302448044629235990852634881794182843979527077012471242
Short name T1814
Test name
Test status
Simulation time 2231375727 ps
CPU time 67.62 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:04:50 PM PST 23
Peak memory 553520 kb
Host smart-7d5a6ea2-960d-4fd4-b01d-c98d31ddbce4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113871381355182702495857302448044629235990852634881794182843979527077012471242 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.xbar_error_random.113871381355182702495857302448044629235990852634881794182843979527077012471242
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random.76801377538849366036734124985771190241449915962374507092311102293674259738195
Short name T506
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.67 seconds
Started Nov 22 03:03:39 PM PST 23
Finished Nov 22 03:04:56 PM PST 23
Peak memory 553752 kb
Host smart-3a55c523-5e02-4eec-995f-00146ca8e383
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76801377538849366036734124985771190241449915962374507092311102293674259738195 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.xbar_random.76801377538849366036734124985771190241449915962374507092311102293674259738195
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.86008066457752142020883540836599173503422460071503962001824532536496306642267
Short name T910
Test name
Test status
Simulation time 97702135727 ps
CPU time 1092.48 seconds
Started Nov 22 03:03:42 PM PST 23
Finished Nov 22 03:21:56 PM PST 23
Peak memory 553684 kb
Host smart-6fdc3486-dbc1-4b71-b7d7-357485e2e041
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86008066457752142020883540836599173503422460071503962001824532536496306642267 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.86008066457752142020883540836599173503422460071503962001824532536496306642267
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.17451208462168609957564153599787100392179760957791543758048673602078709660929
Short name T1016
Test name
Test status
Simulation time 60576345727 ps
CPU time 1001.89 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:20:16 PM PST 23
Peak memory 553672 kb
Host smart-99e3bef8-c6e0-412a-8b29-7e7b66a41065
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17451208462168609957564153599787100392179760957791543758048673602078709660929 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.17451208462168609957564153599787100392179760957791543758048673602078709660929
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.29095143243577872173847762274538837441041349077551623085406048184340843142742
Short name T775
Test name
Test status
Simulation time 556965727 ps
CPU time 48.67 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:04:33 PM PST 23
Peak memory 553536 kb
Host smart-da51c184-7a24-4207-be00-19f154c28b3b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095143243577872173847762274538837441041349077551623085406048184340843142742 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.29095143243577872173847762274538837441041349077551623085406048184340843142742
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_same_source.11265774675437655664021985564958294402056546990332870205071350798682125401541
Short name T1893
Test name
Test status
Simulation time 2498784073 ps
CPU time 67.08 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:04:48 PM PST 23
Peak memory 553836 kb
Host smart-96a65400-8639-43ae-a3dc-5a97afdee7c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11265774675437655664021985564958294402056546990332870205071350798682125401541 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.11265774675437655664021985564958294402056546990332870205071350798682125401541
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke.114354608207184496576215091045483824824649865506324113954257129058903702546062
Short name T389
Test name
Test status
Simulation time 196985727 ps
CPU time 8.21 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:03:47 PM PST 23
Peak memory 552368 kb
Host smart-154ef81f-cbdf-4f48-b9aa-67198deabb00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114354608207184496576215091045483824824649865506324113954257129058903702546062 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.xbar_smoke.114354608207184496576215091045483824824649865506324113954257129058903702546062
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.53341195634565584701477911527014471919161910757452699663223979047805090775913
Short name T1785
Test name
Test status
Simulation time 7758585727 ps
CPU time 85.34 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:05:09 PM PST 23
Peak memory 552408 kb
Host smart-605ccdff-c910-4148-9860-49e2345879b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53341195634565584701477911527014471919161910757452699663223979047805090775913 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.53341195634565584701477911527014471919161910757452699663223979047805090775913
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.39333194312135079441547311026585461361028226811681173219127000325602342050954
Short name T1278
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.7 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:05:02 PM PST 23
Peak memory 552380 kb
Host smart-966f2342-2bd1-4c59-aad8-d2edee5de444
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39333194312135079441547311026585461361028226811681173219127000325602342050954 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.39333194312135079441547311026585461361028226811681173219127000325602342050954
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.13528424473870934018152740461095052480219008858455977223344214700225395910581
Short name T157
Test name
Test status
Simulation time 45555727 ps
CPU time 5.73 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:03:50 PM PST 23
Peak memory 552316 kb
Host smart-8d0b5a46-c0b6-4a6e-951c-e49f5e62bd4c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13528424473870934018152740461095052480219008858455977223344214700225395910581 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.13528424473870934018152740461095052480219008858455977223344214700225395910581
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all.61890556887242398010997061649898234429875515480984772976312777948647826484476
Short name T1097
Test name
Test status
Simulation time 13992004073 ps
CPU time 513.44 seconds
Started Nov 22 03:04:01 PM PST 23
Finished Nov 22 03:12:35 PM PST 23
Peak memory 555900 kb
Host smart-4da4402d-42cf-471d-8c2e-da8fe54499ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61890556887242398010997061649898234429875515480984772976312777948647826484476 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.61890556887242398010997061649898234429875515480984772976312777948647826484476
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.109261260054223852411158074483770885461835140354314511444005706455810393512191
Short name T846
Test name
Test status
Simulation time 13999524073 ps
CPU time 502.47 seconds
Started Nov 22 03:03:49 PM PST 23
Finished Nov 22 03:12:12 PM PST 23
Peak memory 555744 kb
Host smart-751fe7ee-8508-4958-b0b6-3ebe5f79b2be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109261260054223852411158074483770885461835140354314511444005706455810393512191 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.109261260054223852411158074483770885461835140354314511444005706455810393512191
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.61040050201107524507111530554258950622527429874934039526228046996769076055881
Short name T554
Test name
Test status
Simulation time 4815189184 ps
CPU time 360.67 seconds
Started Nov 22 03:03:59 PM PST 23
Finished Nov 22 03:10:01 PM PST 23
Peak memory 557240 kb
Host smart-736ecfa2-5a7f-441d-bbb1-e83df3858a89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61040050201107524507111530554258950622527429874934039526228046996769076055881 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.610400502011075245071115305542589506225274298749340395262280469
96769076055881
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.70583392710111029858263496030604437130465893671002694757333199678038550300183
Short name T1771
Test name
Test status
Simulation time 4815189184 ps
CPU time 312 seconds
Started Nov 22 03:03:48 PM PST 23
Finished Nov 22 03:09:01 PM PST 23
Peak memory 559720 kb
Host smart-86399bec-a209-4c88-a27f-f4d9fa2a7fd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70583392710111029858263496030604437130465893671002694757333199678038550300183 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.7058339271011102985826349603060443713046589367100269475733319
9678038550300183
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.53249569092124239044213555821820890737389269734358479344671368651424624345762
Short name T977
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.28 seconds
Started Nov 22 03:03:48 PM PST 23
Finished Nov 22 03:04:39 PM PST 23
Peak memory 553720 kb
Host smart-5b095cdb-1fc4-4e47-b338-c9e62a687316
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53249569092124239044213555821820890737389269734358479344671368651424624345762 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.53249569092124239044213555821820890737389269734358479344671368651424624345762
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.29191516114682929723119695043151213317311363941235574976945513466374159709286
Short name T27
Test name
Test status
Simulation time 72959944675 ps
CPU time 9176.81 seconds
Started Nov 22 03:04:00 PM PST 23
Finished Nov 22 05:36:58 PM PST 23
Peak memory 625260 kb
Host smart-563c8f85-74e8-4684-8e9c-b2266bfcbcbe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919151611468292972311969504315121331731136394123
5574976945513466374159709286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_aliasing.291915161146829297231196950431512133173113639
41235574976945513466374159709286
Directory /workspace/1.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.80106662949971462459986028617450127041319198340326282379357407357337005516495
Short name T1158
Test name
Test status
Simulation time 7954924257 ps
CPU time 746.55 seconds
Started Nov 22 03:04:01 PM PST 23
Finished Nov 22 03:16:28 PM PST 23
Peak memory 580536 kb
Host smart-310e5304-fdf4-456f-b1c2-c6ba4609a619
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801066629499714624599860286174
50127041319198340326282379357407357337005516495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.80106662949971462459986028
617450127041319198340326282379357407357337005516495
Directory /workspace/1.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.65132630688807639450519566049020948930439743073147814296056148154412809404023
Short name T10
Test name
Test status
Simulation time 5984936856 ps
CPU time 309.83 seconds
Started Nov 22 03:03:47 PM PST 23
Finished Nov 22 03:08:57 PM PST 23
Peak memory 641776 kb
Host smart-c5486a3a-d88c-44fe-8934-cbde016ac57b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65132630688807639450519566049020948930439743073147814296056148154412809404023
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_reset.65132630688807639450519566049020948930439743073147814296056148154412809404023
Directory /workspace/1.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.110668248927438164607040603675622526934283948884715837776724207127764068078926
Short name T1555
Test name
Test status
Simulation time 7234930891 ps
CPU time 314.91 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:08:45 PM PST 23
Peak memory 622436 kb
Host smart-5a4f1405-0a31-4dff-a2bb-d6e6d794fd9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106682489274381646070406036756
22526934283948884715837776724207127764068078926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.110668248927
438164607040603675622526934283948884715837776724207127764068078926
Directory /workspace/1.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_rw.106598373902679155272738242072868940931497749711944294373142802522757469410382
Short name T9
Test name
Test status
Simulation time 5924944675 ps
CPU time 492.85 seconds
Started Nov 22 03:03:04 PM PST 23
Finished Nov 22 03:11:22 PM PST 23
Peak memory 580532 kb
Host smart-3cd22411-ac19-4d99-bc49-524ec3d0ed1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106598373902679155272738242072868940931497749711944294373142802522757469410382 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.106598373902679155272738242072868940931497749711944294373142802522757469410382
Directory /workspace/1.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.76151225185055402927580845319844453343584004048243232085435983001830783724668
Short name T821
Test name
Test status
Simulation time 10669917822 ps
CPU time 448.51 seconds
Started Nov 22 03:03:55 PM PST 23
Finished Nov 22 03:11:24 PM PST 23
Peak memory 576156 kb
Host smart-a52585be-2f6b-4fe0-88ca-26895478ad31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76151225185055402927580845319844453343584004048243232085435983001830783
724668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.761512251850554029275808453198444533435840040482432320854
35983001830783724668
Directory /workspace/1.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.58839853181614315761294398506171754899174139438782284978611111604091351177711
Short name T37
Test name
Test status
Simulation time 10375158790 ps
CPU time 369.37 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:09:54 PM PST 23
Peak memory 576284 kb
Host smart-8234685e-10d2-4c1f-bc10-3ced11003820
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5883985318161431576129439850617175489917413943878228497
8611111604091351177711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.58839853181614315761294398506171754
899174139438782284978611111604091351177711
Directory /workspace/1.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.92539169368160659350254888710806531020999978556169083563991019768850592016987
Short name T713
Test name
Test status
Simulation time 30604932618 ps
CPU time 3138.99 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:56:03 PM PST 23
Peak memory 580112 kb
Host smart-eb022184-d47f-4202-9cb2-fd908a589885
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9253916936816065935025488871080653102
0999978556169083563991019768850592016987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.9253916936816065935025488
8710806531020999978556169083563991019768850592016987
Directory /workspace/1.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.chip_tl_errors.90239539700254739396312738929875118280113453912125610090106506217942050459460
Short name T1349
Test name
Test status
Simulation time 3069924257 ps
CPU time 166.18 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 03:06:20 PM PST 23
Peak memory 580492 kb
Host smart-7000e9ee-5763-48b4-ae4a-0f64498470b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90239539700254739396312738929875118280113453912125610090106506217942050459460 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.90239539700254739396312738929875118280113453912125610090106506217942050459460
Directory /workspace/1.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device.90814124228647836882889905466166350983702780525574142627600734547984346199974
Short name T717
Test name
Test status
Simulation time 2590995727 ps
CPU time 114.75 seconds
Started Nov 22 03:03:08 PM PST 23
Finished Nov 22 03:05:05 PM PST 23
Peak memory 554796 kb
Host smart-b47be6b4-66d3-4eec-a1ca-1794dc9cda41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90814124228647836882889905466166350983702780525574142627600734547984346199974 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.90814124228647836882889905466166350983702780525574142627600734547984346199974
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.29426217166403195922366897353179121535522316920570438994094849375416333544609
Short name T548
Test name
Test status
Simulation time 115195295727 ps
CPU time 2005.2 seconds
Started Nov 22 03:03:05 PM PST 23
Finished Nov 22 03:36:35 PM PST 23
Peak memory 554744 kb
Host smart-6eed1061-099c-4c04-87f1-a1d5d4f06fc3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29426217166403195922366897353179121535522316920570438994094849375416333544609 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.29426217166403195922366897353179121535522316920570438994094849375416333544609
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.110079714968002687455648217767420019632859324433580426990284961371675820344410
Short name T371
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.46 seconds
Started Nov 22 03:03:25 PM PST 23
Finished Nov 22 03:04:08 PM PST 23
Peak memory 553424 kb
Host smart-9cdcc5d5-93e1-47db-9770-42a6a626ce1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110079714968002687455648217767420019632859324433580426990284961371675820344410 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.110079714968002687455648217767420019632859324433580426990284961371675820344410
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_random.84121935257554626607534474475231871773323902503447435068261304844230566666482
Short name T1575
Test name
Test status
Simulation time 2231375727 ps
CPU time 69.08 seconds
Started Nov 22 03:03:27 PM PST 23
Finished Nov 22 03:04:37 PM PST 23
Peak memory 553516 kb
Host smart-bb74ceef-96a2-493c-9583-414526d6dffc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84121935257554626607534474475231871773323902503447435068261304844230566666482 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.xbar_error_random.84121935257554626607534474475231871773323902503447435068261304844230566666482
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random.65394621977326321503723202141819517287936229107132732177193314298329466601503
Short name T510
Test name
Test status
Simulation time 2231375727 ps
CPU time 68.88 seconds
Started Nov 22 03:03:45 PM PST 23
Finished Nov 22 03:04:55 PM PST 23
Peak memory 553708 kb
Host smart-2b273bbc-7c60-4135-ae28-3af7b9d51b91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65394621977326321503723202141819517287936229107132732177193314298329466601503 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.xbar_random.65394621977326321503723202141819517287936229107132732177193314298329466601503
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.39613328723937154727970803501503957861447527614121141885590994064033059881085
Short name T278
Test name
Test status
Simulation time 97702135727 ps
CPU time 1167.94 seconds
Started Nov 22 03:03:00 PM PST 23
Finished Nov 22 03:22:28 PM PST 23
Peak memory 553676 kb
Host smart-2ff4db1c-2b6d-4102-bf65-520215a34340
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613328723937154727970803501503957861447527614121141885590994064033059881085 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.39613328723937154727970803501503957861447527614121141885590994064033059881085
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.13854836329652411633638060552593615742616510782896879061219891816259823110264
Short name T406
Test name
Test status
Simulation time 60576345727 ps
CPU time 1015.62 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 03:20:30 PM PST 23
Peak memory 553644 kb
Host smart-c3bbd628-cd47-4200-9bf9-c8ea6ecc4cdd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854836329652411633638060552593615742616510782896879061219891816259823110264 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.13854836329652411633638060552593615742616510782896879061219891816259823110264
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.95579868445433616871714356070512289089776983833221735045739411001580178035074
Short name T350
Test name
Test status
Simulation time 556965727 ps
CPU time 43.98 seconds
Started Nov 22 03:03:29 PM PST 23
Finished Nov 22 03:04:13 PM PST 23
Peak memory 553632 kb
Host smart-4fe2ef7c-0895-44b2-b391-9f88dc9166a1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95579868445433616871714356070512289089776983833221735045739411001580178035074 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.95579868445433616871714356070512289089776983833221735045739411001580178035074
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_same_source.57983501511406780142997181645503302973253334270761376283344240833600856807136
Short name T1873
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.67 seconds
Started Nov 22 03:02:59 PM PST 23
Finished Nov 22 03:04:12 PM PST 23
Peak memory 553752 kb
Host smart-c5be0c86-b009-4af6-aaa5-2203e00554c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57983501511406780142997181645503302973253334270761376283344240833600856807136 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.57983501511406780142997181645503302973253334270761376283344240833600856807136
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke.8627131881124425687841526315369200523994720502416789085115059752932572059301
Short name T1751
Test name
Test status
Simulation time 196985727 ps
CPU time 8.15 seconds
Started Nov 22 03:03:54 PM PST 23
Finished Nov 22 03:04:03 PM PST 23
Peak memory 552360 kb
Host smart-f81b40b1-2c06-4d46-ac01-68ce2f4edc73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8627131881124425687841526315369200523994720502416789085115059752932572059301 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.xbar_smoke.8627131881124425687841526315369200523994720502416789085115059752932572059301
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.104559305651306286863701256807420531943607899049075145835366425461005283994750
Short name T241
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.5 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:05:06 PM PST 23
Peak memory 552352 kb
Host smart-be0bccf9-edce-4379-83b0-53f8754405a3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104559305651306286863701256807420531943607899049075145835366425461005283994750 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.104559305651306286863701256807420531943607899049075145835366425461005283994750
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.74184099631843923366970369597986043951864623136351147285203421803925699819748
Short name T941
Test name
Test status
Simulation time 4856075727 ps
CPU time 85.56 seconds
Started Nov 22 03:03:06 PM PST 23
Finished Nov 22 03:04:36 PM PST 23
Peak memory 552372 kb
Host smart-575fb49d-9da1-4528-a2fa-a2a3304edf1c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74184099631843923366970369597986043951864623136351147285203421803925699819748 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.74184099631843923366970369597986043951864623136351147285203421803925699819748
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.82184425657243646657629121609788407106302206711132744218756231916391551315755
Short name T905
Test name
Test status
Simulation time 45555727 ps
CPU time 5.92 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:03:37 PM PST 23
Peak memory 552336 kb
Host smart-423d1efe-e6bf-4991-92fc-65ee5a786dd1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82184425657243646657629121609788407106302206711132744218756231916391551315755 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.82184425657243646657629121609788407106302206711132744218756231916391551315755
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all.47083358904316297828225489036995684768119023349511290671200143589326988981152
Short name T1659
Test name
Test status
Simulation time 13992004073 ps
CPU time 564.96 seconds
Started Nov 22 03:03:05 PM PST 23
Finished Nov 22 03:12:35 PM PST 23
Peak memory 555832 kb
Host smart-88370815-51b2-4d24-a873-148220787074
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47083358904316297828225489036995684768119023349511290671200143589326988981152 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.47083358904316297828225489036995684768119023349511290671200143589326988981152
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.17327124608714978242967348276293524934699644328647069635392205411103861724552
Short name T142
Test name
Test status
Simulation time 13999524073 ps
CPU time 495.17 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:11:53 PM PST 23
Peak memory 555812 kb
Host smart-1962b0c2-312e-4f4d-a48e-85bd5dc659c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17327124608714978242967348276293524934699644328647069635392205411103861724552 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.17327124608714978242967348276293524934699644328647069635392205411103861724552
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.9164938980754536431246614827906003157249808905190305725114051198444674576099
Short name T1892
Test name
Test status
Simulation time 4815189184 ps
CPU time 368.29 seconds
Started Nov 22 03:03:05 PM PST 23
Finished Nov 22 03:09:18 PM PST 23
Peak memory 557216 kb
Host smart-2a2d9a20-a52e-43a2-abed-4678a68ad043
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9164938980754536431246614827906003157249808905190305725114051198444674576099 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.9164938980754536431246614827906003157249808905190305725114051198444674576099
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.96884384105704757835988667265975397530976844650701119279056107699867949721668
Short name T1415
Test name
Test status
Simulation time 4815189184 ps
CPU time 316.78 seconds
Started Nov 22 03:03:04 PM PST 23
Finished Nov 22 03:08:21 PM PST 23
Peak memory 559640 kb
Host smart-07bd2b0f-a4fb-4d12-a5c4-9cc29756f128
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96884384105704757835988667265975397530976844650701119279056107699867949721668 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.9688438410570475783598866726597539753097684465070111927905610
7699867949721668
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.95509289142117734756990627083162362296303595021037899817488300058369526970766
Short name T653
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.46 seconds
Started Nov 22 03:03:25 PM PST 23
Finished Nov 22 03:04:16 PM PST 23
Peak memory 553800 kb
Host smart-d68a3310-2c77-4d27-9017-2d42db30f7dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95509289142117734756990627083162362296303595021037899817488300058369526970766 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.95509289142117734756990627083162362296303595021037899817488300058369526970766
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.103586425426627801115927591267137377529101264275526994565018442794849560241654
Short name T633
Test name
Test status
Simulation time 7234930891 ps
CPU time 332.4 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:09:37 PM PST 23
Peak memory 622496 kb
Host smart-5ad9fc63-eb51-4f3f-b2d6-1dbff50a700a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035864254266278011159275912671
37377529101264275526994565018442794849560241654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.10358642542
6627801115927591267137377529101264275526994565018442794849560241654
Directory /workspace/10.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_rw.61442449766501451770194810555944211128347263640125822601191334405102563715761
Short name T8
Test name
Test status
Simulation time 5924944675 ps
CPU time 518.78 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:12:43 PM PST 23
Peak memory 580500 kb
Host smart-5d2b6330-1137-46bd-9e50-bc68b3c5e105
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61442449766501451770194810555944211128347263640125822601191334405102563715761 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.61442449766501451770194810555944211128347263640125822601191334405102563715761
Directory /workspace/10.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.104728453022919558735314939288517993485185463676938515788857193344488021130345
Short name T1605
Test name
Test status
Simulation time 30604932618 ps
CPU time 2928.45 seconds
Started Nov 22 03:03:57 PM PST 23
Finished Nov 22 03:52:47 PM PST 23
Peak memory 580524 kb
Host smart-7eb642a2-5cb2-4c60-9677-6e7c87fbc330
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047284530229195587353149392885179934
85185463676938515788857193344488021130345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.10472845302291955873531
4939288517993485185463676938515788857193344488021130345
Directory /workspace/10.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.chip_tl_errors.112944409693009476265887523405667253220856540388136590871772170425801957057921
Short name T3
Test name
Test status
Simulation time 3069924257 ps
CPU time 181.18 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:06:45 PM PST 23
Peak memory 580456 kb
Host smart-495db727-a718-4317-9081-578329d3cc74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112944409693009476265887523405667253220856540388136590871772170425801957057921 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.112944409693009476265887523405667253220856540388136590871772170425801957057921
Directory /workspace/10.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device.19051828165225004672234328365650613184649042172798642282198539362179850468656
Short name T677
Test name
Test status
Simulation time 2590995727 ps
CPU time 96.94 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:05:16 PM PST 23
Peak memory 554740 kb
Host smart-07a82412-f3c9-48d9-9318-b23a8164d42b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051828165225004672234328365650613184649042172798642282198539362179850468656 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.19051828165225004672234328365650613184649042172798642282198539362179850468656
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.93488065508980696161012748730072672527165106383527428732325641850733103542670
Short name T544
Test name
Test status
Simulation time 115195295727 ps
CPU time 2026.98 seconds
Started Nov 22 03:03:55 PM PST 23
Finished Nov 22 03:37:43 PM PST 23
Peak memory 554784 kb
Host smart-af5ba360-0007-4e08-89e4-a20734b2af9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93488065508980696161012748730072672527165106383527428732325641850733103542670 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.93488065508980696161012748730072672527165106383527428732325641850733103542670
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.7894405413389657051099187517099022656566783619987122880950553584298688162342
Short name T1023
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.65 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:04:50 PM PST 23
Peak memory 553456 kb
Host smart-3a341e2a-b6ec-4804-b589-96b2bdfa1b50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7894405413389657051099187517099022656566783619987122880950553584298688162342 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.7894405413389657051099187517099022656566783619987122880950553584298688162342
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_random.24909801815116269262536163083334527388646258696626119626436619385979531159711
Short name T1333
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.85 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:04:57 PM PST 23
Peak memory 553120 kb
Host smart-63ca0dfb-5001-480f-a618-459711ddbe8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909801815116269262536163083334527388646258696626119626436619385979531159711 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.xbar_error_random.24909801815116269262536163083334527388646258696626119626436619385979531159711
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random.24088237533669027929349920110132181265466296453510906676812414626180264297551
Short name T333
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.2 seconds
Started Nov 22 03:04:06 PM PST 23
Finished Nov 22 03:05:21 PM PST 23
Peak memory 553748 kb
Host smart-2a33349e-56f1-4339-bfb1-24ad7797c5eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088237533669027929349920110132181265466296453510906676812414626180264297551 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.xbar_random.24088237533669027929349920110132181265466296453510906676812414626180264297551
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.114688473773749000601699338082816447112139733469890360784855263967656591408185
Short name T444
Test name
Test status
Simulation time 97702135727 ps
CPU time 1135.42 seconds
Started Nov 22 03:03:52 PM PST 23
Finished Nov 22 03:22:48 PM PST 23
Peak memory 553676 kb
Host smart-8b130733-b637-4c47-8426-52b73e771bed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114688473773749000601699338082816447112139733469890360784855263967656591408185 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.114688473773749000601699338082816447112139733469890360784855263967656591408185
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.37554549366343107892550420020814329332927654724360203850265822933640940225209
Short name T1705
Test name
Test status
Simulation time 60576345727 ps
CPU time 1069.76 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:21:54 PM PST 23
Peak memory 553584 kb
Host smart-b276fdc5-ed99-44ae-9101-0dff80744a75
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37554549366343107892550420020814329332927654724360203850265822933640940225209 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.37554549366343107892550420020814329332927654724360203850265822933640940225209
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.99830884705940623238471487335227701328036993551638218562574540489256709561297
Short name T1371
Test name
Test status
Simulation time 556965727 ps
CPU time 47.29 seconds
Started Nov 22 03:04:08 PM PST 23
Finished Nov 22 03:04:56 PM PST 23
Peak memory 553704 kb
Host smart-e2b0dfb0-36bf-42ac-8a5b-b222852472d6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99830884705940623238471487335227701328036993551638218562574540489256709561297 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.99830884705940623238471487335227701328036993551638218562574540489256709561297
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_same_source.50293212138677194962303244508773403459884810842644131673775426130882765203355
Short name T1112
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.39 seconds
Started Nov 22 03:04:00 PM PST 23
Finished Nov 22 03:05:12 PM PST 23
Peak memory 553728 kb
Host smart-2af1c91f-5938-4261-942d-cf7be8bcd44f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50293212138677194962303244508773403459884810842644131673775426130882765203355 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.50293212138677194962303244508773403459884810842644131673775426130882765203355
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke.114597349842883367729769386461761591199999049415912489869603058644717173611337
Short name T1586
Test name
Test status
Simulation time 196985727 ps
CPU time 8.12 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:03:43 PM PST 23
Peak memory 552340 kb
Host smart-93a7dec2-a40c-46af-b8a2-8510b53519dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114597349842883367729769386461761591199999049415912489869603058644717173611337 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.xbar_smoke.114597349842883367729769386461761591199999049415912489869603058644717173611337
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.64453048562216338819381848648031199986521537983371809077475347545526318595879
Short name T575
Test name
Test status
Simulation time 7758585727 ps
CPU time 84.23 seconds
Started Nov 22 03:03:59 PM PST 23
Finished Nov 22 03:05:24 PM PST 23
Peak memory 552360 kb
Host smart-92a06907-2567-4474-be7f-6a8db7a0cafe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64453048562216338819381848648031199986521537983371809077475347545526318595879 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.64453048562216338819381848648031199986521537983371809077475347545526318595879
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.6053527040348866887667864326929203262952905909253849906943132273937505073815
Short name T1353
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.92 seconds
Started Nov 22 03:03:49 PM PST 23
Finished Nov 22 03:05:14 PM PST 23
Peak memory 552376 kb
Host smart-b6c7e130-3f33-4f40-b98b-da68bd2d91e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6053527040348866887667864326929203262952905909253849906943132273937505073815 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.6053527040348866887667864326929203262952905909253849906943132273937505073815
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.13306859559031257761101084035515866946500714867715551915661254688429961711696
Short name T1595
Test name
Test status
Simulation time 45555727 ps
CPU time 5.97 seconds
Started Nov 22 03:03:58 PM PST 23
Finished Nov 22 03:04:05 PM PST 23
Peak memory 552344 kb
Host smart-48f39d7b-521b-41c4-a6ff-86fa83608a75
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13306859559031257761101084035515866946500714867715551915661254688429961711696 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.13306859559031257761101084035515866946500714867715551915661254688429961711696
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all.59085544753957605070505243330308837647828419066225561241249254196154494620833
Short name T310
Test name
Test status
Simulation time 13992004073 ps
CPU time 518.08 seconds
Started Nov 22 03:04:07 PM PST 23
Finished Nov 22 03:12:46 PM PST 23
Peak memory 555904 kb
Host smart-578960ed-accb-44d5-b2e6-71ddd6912d05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59085544753957605070505243330308837647828419066225561241249254196154494620833 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.59085544753957605070505243330308837647828419066225561241249254196154494620833
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.55577273726017826682465342295855633583064044667603820713404968714479083231971
Short name T174
Test name
Test status
Simulation time 13999524073 ps
CPU time 483.18 seconds
Started Nov 22 03:04:00 PM PST 23
Finished Nov 22 03:12:04 PM PST 23
Peak memory 555764 kb
Host smart-b0bf7e8c-f6bb-400c-b297-31453e755010
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55577273726017826682465342295855633583064044667603820713404968714479083231971 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.55577273726017826682465342295855633583064044667603820713404968714479083231971
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1199577934371909359112508946174663749445122308677134899751727584929525488049
Short name T939
Test name
Test status
Simulation time 4815189184 ps
CPU time 360.77 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:10:05 PM PST 23
Peak memory 557204 kb
Host smart-e65018a6-5b07-447f-b035-715ce813963e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199577934371909359112508946174663749445122308677134899751727584929525488049 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.119957793437190935911250894617466374944512230867713489975172758
4929525488049
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.114708777046164753366119846741587088345111092318621595708719842007596829542793
Short name T805
Test name
Test status
Simulation time 4815189184 ps
CPU time 321.71 seconds
Started Nov 22 03:03:46 PM PST 23
Finished Nov 22 03:09:08 PM PST 23
Peak memory 559640 kb
Host smart-151fe8bb-8e17-45d3-a6ad-ede5207039aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114708777046164753366119846741587088345111092318621595708719842007596829542793 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.11470877704616475336611984674158708834511109231862159570871
9842007596829542793
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.53028419425818286245983298477673973590407157877240192782495304997513099606455
Short name T852
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.23 seconds
Started Nov 22 03:04:08 PM PST 23
Finished Nov 22 03:04:56 PM PST 23
Peak memory 553628 kb
Host smart-924c13e4-7508-4370-b7c2-546a3fb35f2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53028419425818286245983298477673973590407157877240192782495304997513099606455 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.53028419425818286245983298477673973590407157877240192782495304997513099606455
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.6017771775013735225514675965121833065833925023323611431179246777166415121389
Short name T1431
Test name
Test status
Simulation time 7234930891 ps
CPU time 312.92 seconds
Started Nov 22 03:03:49 PM PST 23
Finished Nov 22 03:09:02 PM PST 23
Peak memory 622436 kb
Host smart-d6f4674d-f6e3-47dc-ad78-bd12a463291d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6017771775013735225514675965121
833065833925023323611431179246777166415121389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.6017771775013
735225514675965121833065833925023323611431179246777166415121389
Directory /workspace/11.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_rw.32188909720676678875991930670198495150893582061045152451421195176461905645964
Short name T761
Test name
Test status
Simulation time 5924944675 ps
CPU time 544.37 seconds
Started Nov 22 03:04:02 PM PST 23
Finished Nov 22 03:13:07 PM PST 23
Peak memory 580572 kb
Host smart-313784d0-02ef-4bcb-90f0-acb87dec06d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32188909720676678875991930670198495150893582061045152451421195176461905645964 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.32188909720676678875991930670198495150893582061045152451421195176461905645964
Directory /workspace/11.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.69248068769111650473759246922481145379916231134091924083096739795519363613700
Short name T28
Test name
Test status
Simulation time 30604932618 ps
CPU time 3168.8 seconds
Started Nov 22 03:04:01 PM PST 23
Finished Nov 22 03:56:51 PM PST 23
Peak memory 580520 kb
Host smart-bb0093d0-506c-4aae-84d1-7332c62a50b4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6924806876911165047375924692248114537
9916231134091924083096739795519363613700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.692480687691116504737592
46922481145379916231134091924083096739795519363613700
Directory /workspace/11.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.chip_tl_errors.93873645118609369916653371464256778703728257241195402002969357625803836524842
Short name T1412
Test name
Test status
Simulation time 3069924257 ps
CPU time 179.39 seconds
Started Nov 22 03:04:08 PM PST 23
Finished Nov 22 03:07:08 PM PST 23
Peak memory 580412 kb
Host smart-704ba633-667c-4589-86a6-0970f7cdbb83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93873645118609369916653371464256778703728257241195402002969357625803836524842 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.93873645118609369916653371464256778703728257241195402002969357625803836524842
Directory /workspace/11.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device.61968396332981418182388701000742855864729193220733452373928743333458583860672
Short name T1851
Test name
Test status
Simulation time 2590995727 ps
CPU time 115.47 seconds
Started Nov 22 03:03:52 PM PST 23
Finished Nov 22 03:05:48 PM PST 23
Peak memory 554880 kb
Host smart-5e4efc0b-3085-4097-86ff-eb3956a9d500
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61968396332981418182388701000742855864729193220733452373928743333458583860672 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.61968396332981418182388701000742855864729193220733452373928743333458583860672
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.65848593361825818588283841389862917761801265840609947381185835081008618265393
Short name T1215
Test name
Test status
Simulation time 115195295727 ps
CPU time 2111.59 seconds
Started Nov 22 03:03:47 PM PST 23
Finished Nov 22 03:39:00 PM PST 23
Peak memory 554780 kb
Host smart-7f62f458-36d3-4b68-a826-d9ead1432982
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65848593361825818588283841389862917761801265840609947381185835081008618265393 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.65848593361825818588283841389862917761801265840609947381185835081008618265393
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.49452218173301903943307851762080682506300170876054486322081464189944376589967
Short name T669
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.74 seconds
Started Nov 22 03:04:11 PM PST 23
Finished Nov 22 03:04:58 PM PST 23
Peak memory 553464 kb
Host smart-c5fdaf4b-91dc-421f-be6e-d08c6f014d00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49452218173301903943307851762080682506300170876054486322081464189944376589967 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.49452218173301903943307851762080682506300170876054486322081464189944376589967
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_random.94450740151181800233108717754352537104150060253832443746282764023450127537257
Short name T1370
Test name
Test status
Simulation time 2231375727 ps
CPU time 68.48 seconds
Started Nov 22 03:04:02 PM PST 23
Finished Nov 22 03:05:10 PM PST 23
Peak memory 553572 kb
Host smart-7ad70acd-93b7-4f4a-af12-9cd4234aa1df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94450740151181800233108717754352537104150060253832443746282764023450127537257 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.xbar_error_random.94450740151181800233108717754352537104150060253832443746282764023450127537257
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random.52296096983770521417000456595794491420581286657138002107943342480078248163566
Short name T886
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.46 seconds
Started Nov 22 03:04:03 PM PST 23
Finished Nov 22 03:05:20 PM PST 23
Peak memory 553724 kb
Host smart-62d28d3b-8127-4634-bec6-fd83e3bac38c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52296096983770521417000456595794491420581286657138002107943342480078248163566 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.xbar_random.52296096983770521417000456595794491420581286657138002107943342480078248163566
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.97800489436282988961112113406587007320356499553766353060940548407295812946821
Short name T320
Test name
Test status
Simulation time 97702135727 ps
CPU time 1143.65 seconds
Started Nov 22 03:04:03 PM PST 23
Finished Nov 22 03:23:07 PM PST 23
Peak memory 553664 kb
Host smart-fb2d9cc0-fd16-450d-9b5e-443808d4837d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97800489436282988961112113406587007320356499553766353060940548407295812946821 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.97800489436282988961112113406587007320356499553766353060940548407295812946821
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.89422239391635476324086737986666207502092117213282643888913632751677099714870
Short name T943
Test name
Test status
Simulation time 60576345727 ps
CPU time 1027.15 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:21:11 PM PST 23
Peak memory 553708 kb
Host smart-a98f8a52-c4f8-450b-8816-1e7bc9f23c1e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89422239391635476324086737986666207502092117213282643888913632751677099714870 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.89422239391635476324086737986666207502092117213282643888913632751677099714870
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2679024384199342955992418837811606236936750739515464296547573241145793755803
Short name T1126
Test name
Test status
Simulation time 556965727 ps
CPU time 47.33 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:04:52 PM PST 23
Peak memory 553688 kb
Host smart-d0781d52-083b-4298-a911-9b72efa9d291
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679024384199342955992418837811606236936750739515464296547573241145793755803 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2679024384199342955992418837811606236936750739515464296547573241145793755803
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_same_source.105247311493742535250789986553698441305936109238735491085901132616540610723717
Short name T268
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.54 seconds
Started Nov 22 03:04:03 PM PST 23
Finished Nov 22 03:05:15 PM PST 23
Peak memory 553724 kb
Host smart-dcfb0b02-5300-4f5f-a92e-f6156077ce33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105247311493742535250789986553698441305936109238735491085901132616540610723717 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.105247311493742535250789986553698441305936109238735491085901132616540610723717
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke.4256138613248284896704369128630871178178648719534499034623685719849090214406
Short name T1907
Test name
Test status
Simulation time 196985727 ps
CPU time 7.86 seconds
Started Nov 22 03:03:48 PM PST 23
Finished Nov 22 03:03:56 PM PST 23
Peak memory 552324 kb
Host smart-03eeeece-56a8-4634-a4d9-80110d143ebe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256138613248284896704369128630871178178648719534499034623685719849090214406 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.xbar_smoke.4256138613248284896704369128630871178178648719534499034623685719849090214406
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.65694990366110091294846052349180705240662172173837576715560302841429441474478
Short name T1255
Test name
Test status
Simulation time 7758585727 ps
CPU time 87.45 seconds
Started Nov 22 03:04:08 PM PST 23
Finished Nov 22 03:05:36 PM PST 23
Peak memory 552380 kb
Host smart-469e606d-7ae5-419b-80f8-7e83d87a3437
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65694990366110091294846052349180705240662172173837576715560302841429441474478 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.65694990366110091294846052349180705240662172173837576715560302841429441474478
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.99417230590411337168949745120765712703837024312241028509950422160027777303361
Short name T1335
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.27 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:05:24 PM PST 23
Peak memory 552364 kb
Host smart-9543444d-4434-478d-a6c0-b72fae5acbf9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99417230590411337168949745120765712703837024312241028509950422160027777303361 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.99417230590411337168949745120765712703837024312241028509950422160027777303361
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.13818958409009967625198596909209936654085070905991577624833357341214486032431
Short name T1019
Test name
Test status
Simulation time 45555727 ps
CPU time 5.88 seconds
Started Nov 22 03:04:07 PM PST 23
Finished Nov 22 03:04:14 PM PST 23
Peak memory 552356 kb
Host smart-2f4f8031-01e3-471e-90e2-be71c3720119
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13818958409009967625198596909209936654085070905991577624833357341214486032431 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.13818958409009967625198596909209936654085070905991577624833357341214486032431
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all.41968466712684577265668399886293640822419413037514000627715798455658390701390
Short name T1346
Test name
Test status
Simulation time 13992004073 ps
CPU time 539.45 seconds
Started Nov 22 03:03:46 PM PST 23
Finished Nov 22 03:12:46 PM PST 23
Peak memory 555916 kb
Host smart-2ab16c93-2190-4eaa-844f-6444fde6aa9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41968466712684577265668399886293640822419413037514000627715798455658390701390 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.41968466712684577265668399886293640822419413037514000627715798455658390701390
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.96183218414174966542634932332106462881258826572461641141223453613328802560162
Short name T306
Test name
Test status
Simulation time 13999524073 ps
CPU time 508 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:12:32 PM PST 23
Peak memory 555640 kb
Host smart-a1192a4b-ecf7-4718-95d6-af8d3e0e37c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96183218414174966542634932332106462881258826572461641141223453613328802560162 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.96183218414174966542634932332106462881258826572461641141223453613328802560162
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.98747859324910869943668105121984276699584752580874172491802299323350685631522
Short name T1471
Test name
Test status
Simulation time 4815189184 ps
CPU time 367.2 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:10:04 PM PST 23
Peak memory 557208 kb
Host smart-b73c9d89-3a84-4632-b905-7fcd7d6e3df5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98747859324910869943668105121984276699584752580874172491802299323350685631522 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.98747859324910869943668105121984276699584752580874172491802299
323350685631522
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.114753119922718192777635729178807045502962150032880576895416804946449593367598
Short name T158
Test name
Test status
Simulation time 4815189184 ps
CPU time 308.09 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:09:05 PM PST 23
Peak memory 559672 kb
Host smart-e3e80251-0211-4cc7-b0b0-2f049ae0dd3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114753119922718192777635729178807045502962150032880576895416804946449593367598 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.11475311992271819277763572917880704550296215003288057689541
6804946449593367598
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.115326680480893588765489575212397208584067577049841843715322047860637996771196
Short name T967
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.11 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:04:44 PM PST 23
Peak memory 553668 kb
Host smart-822d882d-313b-4350-a76e-60e35374f03e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115326680480893588765489575212397208584067577049841843715322047860637996771196 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.115326680480893588765489575212397208584067577049841843715322047860637996771196
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.13768331529097040281275735356930343594429706783646304168231832262137938897593
Short name T1923
Test name
Test status
Simulation time 7234930891 ps
CPU time 336.75 seconds
Started Nov 22 03:04:14 PM PST 23
Finished Nov 22 03:09:51 PM PST 23
Peak memory 622520 kb
Host smart-566d2318-77cb-473a-b357-873545ffbce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376833152909704028127573535693
0343594429706783646304168231832262137938897593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.137683315290
97040281275735356930343594429706783646304168231832262137938897593
Directory /workspace/12.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_rw.55627460745428291603842860612232863575886367581394292188866679558501457301607
Short name T1451
Test name
Test status
Simulation time 5924944675 ps
CPU time 553.24 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:13:33 PM PST 23
Peak memory 580624 kb
Host smart-1a087d16-bf8e-4afe-a2a2-a750c5047291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55627460745428291603842860612232863575886367581394292188866679558501457301607 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.55627460745428291603842860612232863575886367581394292188866679558501457301607
Directory /workspace/12.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.27499700463455218793590596078180614196245098316049247065419687989470293459534
Short name T1520
Test name
Test status
Simulation time 30604932618 ps
CPU time 2971.94 seconds
Started Nov 22 03:04:03 PM PST 23
Finished Nov 22 03:53:36 PM PST 23
Peak memory 580512 kb
Host smart-42465080-6faa-46b1-98b1-100e2428f36b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749970046345521879359059607818061419
6245098316049247065419687989470293459534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.274997004634552187935905
96078180614196245098316049247065419687989470293459534
Directory /workspace/12.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.chip_tl_errors.49490152746301097163947271800249653499909061677564626275166783648265235977210
Short name T925
Test name
Test status
Simulation time 3069924257 ps
CPU time 181.01 seconds
Started Nov 22 03:04:03 PM PST 23
Finished Nov 22 03:07:05 PM PST 23
Peak memory 580508 kb
Host smart-b4e4861b-2903-4c52-bb8b-ccf874bb8bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49490152746301097163947271800249653499909061677564626275166783648265235977210 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.49490152746301097163947271800249653499909061677564626275166783648265235977210
Directory /workspace/12.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device.109426421907207188510599526445173053586011489683039338944733281868797983193728
Short name T1470
Test name
Test status
Simulation time 2590995727 ps
CPU time 101.51 seconds
Started Nov 22 03:04:07 PM PST 23
Finished Nov 22 03:05:49 PM PST 23
Peak memory 554792 kb
Host smart-f8a226c0-783f-4778-a165-eba55ea94c2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109426421907207188510599526445173053586011489683039338944733281868797983193728 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.109426421907207188510599526445173053586011489683039338944733281868797983193728
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.58326714267608836083054337404124241113914381944980357698978396324676747104839
Short name T338
Test name
Test status
Simulation time 115195295727 ps
CPU time 1981.51 seconds
Started Nov 22 03:04:02 PM PST 23
Finished Nov 22 03:37:04 PM PST 23
Peak memory 554780 kb
Host smart-e8712e60-807d-4f4c-92f0-2f113b0e473c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58326714267608836083054337404124241113914381944980357698978396324676747104839 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.58326714267608836083054337404124241113914381944980357698978396324676747104839
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_random.113529158502439127666840847859594091843759348845432046357955117570661435693221
Short name T1372
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.85 seconds
Started Nov 22 03:04:11 PM PST 23
Finished Nov 22 03:05:29 PM PST 23
Peak memory 553456 kb
Host smart-6080ece1-b617-4dc4-8ce6-246e30d34a2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113529158502439127666840847859594091843759348845432046357955117570661435693221 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.xbar_error_random.113529158502439127666840847859594091843759348845432046357955117570661435693221
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random.34033005167795716840052874698600558088059044102483772635280266998648467102370
Short name T180
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.79 seconds
Started Nov 22 03:04:23 PM PST 23
Finished Nov 22 03:05:38 PM PST 23
Peak memory 553740 kb
Host smart-946b32d0-5bf1-4b21-87c8-597e5a5bd93a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34033005167795716840052874698600558088059044102483772635280266998648467102370 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.xbar_random.34033005167795716840052874698600558088059044102483772635280266998648467102370
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.20895223398397878125983625330247913605185277073226554675032924582346912030974
Short name T1761
Test name
Test status
Simulation time 97702135727 ps
CPU time 1155.25 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:23:36 PM PST 23
Peak memory 553684 kb
Host smart-a15963d7-273b-4a76-be69-9cadce68e843
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895223398397878125983625330247913605185277073226554675032924582346912030974 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.20895223398397878125983625330247913605185277073226554675032924582346912030974
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.94549828188735808092628538417715377060466794680321051414953874747203254592025
Short name T796
Test name
Test status
Simulation time 60576345727 ps
CPU time 1136.66 seconds
Started Nov 22 03:04:07 PM PST 23
Finished Nov 22 03:23:04 PM PST 23
Peak memory 553680 kb
Host smart-bd0de621-2822-46af-8c39-0d24ea62b6d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94549828188735808092628538417715377060466794680321051414953874747203254592025 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.94549828188735808092628538417715377060466794680321051414953874747203254592025
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.44191435706287651658240360230243057524476069117703778746461768594007510032531
Short name T1468
Test name
Test status
Simulation time 556965727 ps
CPU time 43.49 seconds
Started Nov 22 03:04:21 PM PST 23
Finished Nov 22 03:05:05 PM PST 23
Peak memory 553704 kb
Host smart-456ada23-fb15-4438-8cff-62e2fead9ec9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44191435706287651658240360230243057524476069117703778746461768594007510032531 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.44191435706287651658240360230243057524476069117703778746461768594007510032531
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_same_source.38603647512364463134499615380874140887686058763815261555221143083433579068241
Short name T1760
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.24 seconds
Started Nov 22 03:04:01 PM PST 23
Finished Nov 22 03:05:13 PM PST 23
Peak memory 553680 kb
Host smart-c19ba961-e776-435a-9d95-e1b4e7ef0013
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603647512364463134499615380874140887686058763815261555221143083433579068241 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.38603647512364463134499615380874140887686058763815261555221143083433579068241
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke.99763143714943447355475906564841643075085568154618794048645929562780761197130
Short name T741
Test name
Test status
Simulation time 196985727 ps
CPU time 8.3 seconds
Started Nov 22 03:04:02 PM PST 23
Finished Nov 22 03:04:11 PM PST 23
Peak memory 552408 kb
Host smart-f50d9161-e729-4ab1-a23e-cd65e8110d80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99763143714943447355475906564841643075085568154618794048645929562780761197130 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.xbar_smoke.99763143714943447355475906564841643075085568154618794048645929562780761197130
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.31331715602129884388632169386672518593046843661403986560759454050748036077876
Short name T1567
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.22 seconds
Started Nov 22 03:03:55 PM PST 23
Finished Nov 22 03:05:24 PM PST 23
Peak memory 552352 kb
Host smart-f1c23bd1-1d02-4c54-bd90-06da6c4d0ac9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331715602129884388632169386672518593046843661403986560759454050748036077876 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.31331715602129884388632169386672518593046843661403986560759454050748036077876
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.17189377290244624768076061897563678029472544352279795133560251019810791652899
Short name T1542
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.26 seconds
Started Nov 22 03:04:04 PM PST 23
Finished Nov 22 03:05:29 PM PST 23
Peak memory 552300 kb
Host smart-6df8a8e0-8167-4ae8-b8b2-b38a8b3081c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17189377290244624768076061897563678029472544352279795133560251019810791652899 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.17189377290244624768076061897563678029472544352279795133560251019810791652899
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.100413614798557017682806826014432799448415766048143817594555360699345067609450
Short name T1091
Test name
Test status
Simulation time 45555727 ps
CPU time 6.03 seconds
Started Nov 22 03:04:00 PM PST 23
Finished Nov 22 03:04:07 PM PST 23
Peak memory 552448 kb
Host smart-c22e4177-1610-4f77-bc84-6056a28b7699
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100413614798557017682806826014432799448415766048143817594555360699345067609450 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.100413614798557017682806826014432799448415766048143817594555360699345067609450
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all.108359416366402201340127138495101806700676124214696616762827666018164289596596
Short name T875
Test name
Test status
Simulation time 13992004073 ps
CPU time 548.39 seconds
Started Nov 22 03:04:07 PM PST 23
Finished Nov 22 03:13:17 PM PST 23
Peak memory 555904 kb
Host smart-bf36715e-43fa-4ff6-a7d4-fa315f2c4528
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108359416366402201340127138495101806700676124214696616762827666018164289596596 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.108359416366402201340127138495101806700676124214696616762827666018164289596596
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.65697395446667004480383196295434220412605813119691409911522499820604834003543
Short name T700
Test name
Test status
Simulation time 13999524073 ps
CPU time 543.88 seconds
Started Nov 22 03:04:20 PM PST 23
Finished Nov 22 03:13:24 PM PST 23
Peak memory 555724 kb
Host smart-fb89b572-d373-4785-a15e-aa04ce724815
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65697395446667004480383196295434220412605813119691409911522499820604834003543 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.65697395446667004480383196295434220412605813119691409911522499820604834003543
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.62514418796074220909973864994683167978959412300129025693152184695346839086287
Short name T131
Test name
Test status
Simulation time 4815189184 ps
CPU time 313.64 seconds
Started Nov 22 03:04:21 PM PST 23
Finished Nov 22 03:09:35 PM PST 23
Peak memory 559660 kb
Host smart-3f038f79-48f7-41a3-bfd4-e2707c90526e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62514418796074220909973864994683167978959412300129025693152184695346839086287 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.625144187960742209099738649946831679789594123001290256931521
84695346839086287
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.30381594202123663432350176717377859534196130538638221165722787162864330631822
Short name T725
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.16 seconds
Started Nov 22 03:04:17 PM PST 23
Finished Nov 22 03:05:03 PM PST 23
Peak memory 553668 kb
Host smart-9655ee23-b7d1-4f92-a0a6-65552acab17f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30381594202123663432350176717377859534196130538638221165722787162864330631822 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.30381594202123663432350176717377859534196130538638221165722787162864330631822
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.50592556933573515535696232530975192099973851240809533174899887816269700727092
Short name T1384
Test name
Test status
Simulation time 7234930891 ps
CPU time 319.96 seconds
Started Nov 22 03:04:14 PM PST 23
Finished Nov 22 03:09:35 PM PST 23
Peak memory 622496 kb
Host smart-60af3af7-82f3-43f3-ad0d-7e76bdde1045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5059255693357351553569623253097
5192099973851240809533174899887816269700727092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.505925569335
73515535696232530975192099973851240809533174899887816269700727092
Directory /workspace/13.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_rw.73851944342567274498961157144315941240394105068788380265137972759731074578680
Short name T798
Test name
Test status
Simulation time 5924944675 ps
CPU time 584.08 seconds
Started Nov 22 03:04:18 PM PST 23
Finished Nov 22 03:14:02 PM PST 23
Peak memory 580540 kb
Host smart-25ab8739-7905-4d39-91b2-be7148ca0fa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73851944342567274498961157144315941240394105068788380265137972759731074578680 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.73851944342567274498961157144315941240394105068788380265137972759731074578680
Directory /workspace/13.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.84050254287997085028684269595046356818475096037353093219793408054552181299996
Short name T1481
Test name
Test status
Simulation time 30604932618 ps
CPU time 3282.55 seconds
Started Nov 22 03:04:24 PM PST 23
Finished Nov 22 03:59:07 PM PST 23
Peak memory 580540 kb
Host smart-57cf6d30-dbc1-4a11-bbcc-0a4fedec82c5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8405025428799708502868426959504635681
8475096037353093219793408054552181299996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.840502542879970850286842
69595046356818475096037353093219793408054552181299996
Directory /workspace/13.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.chip_tl_errors.113501187957029851811158630607668845619645219583859072127975404963345458361742
Short name T87
Test name
Test status
Simulation time 3069924257 ps
CPU time 180.3 seconds
Started Nov 22 03:04:29 PM PST 23
Finished Nov 22 03:07:30 PM PST 23
Peak memory 580564 kb
Host smart-6b7b81c1-e2e1-42ad-9759-2abd5bc00b04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113501187957029851811158630607668845619645219583859072127975404963345458361742 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.113501187957029851811158630607668845619645219583859072127975404963345458361742
Directory /workspace/13.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device.99589237326451108027658249904793379487964527337123195444272525364584075425027
Short name T366
Test name
Test status
Simulation time 2590995727 ps
CPU time 100.71 seconds
Started Nov 22 03:04:25 PM PST 23
Finished Nov 22 03:06:06 PM PST 23
Peak memory 554716 kb
Host smart-f03c89d8-1df6-4381-8f71-cee72d1c4bc0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99589237326451108027658249904793379487964527337123195444272525364584075425027 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.99589237326451108027658249904793379487964527337123195444272525364584075425027
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.112973644085360587983056373890153892682106183239205064507538516343648699666866
Short name T924
Test name
Test status
Simulation time 115195295727 ps
CPU time 1969.42 seconds
Started Nov 22 03:04:17 PM PST 23
Finished Nov 22 03:37:07 PM PST 23
Peak memory 554796 kb
Host smart-3ca3126e-046d-4900-94cf-e1140e8b339f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112973644085360587983056373890153892682106183239205064507538516343648699666866 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.112973644085360587983056373890153892682106183239205064507538516343648699666866
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.104961317615603634689593058638752730655992683319520545342768075257502711185030
Short name T73
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.17 seconds
Started Nov 22 03:04:15 PM PST 23
Finished Nov 22 03:05:01 PM PST 23
Peak memory 553464 kb
Host smart-1d1cf050-dfad-4846-8733-b0e24d32a9f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104961317615603634689593058638752730655992683319520545342768075257502711185030 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.104961317615603634689593058638752730655992683319520545342768075257502711185030
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_random.28427825784684593915593700452703484205694373991710791581922410292308114513362
Short name T1329
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.89 seconds
Started Nov 22 03:04:14 PM PST 23
Finished Nov 22 03:05:26 PM PST 23
Peak memory 553512 kb
Host smart-bea4170a-0041-4d29-8eed-ef0aa12f7267
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427825784684593915593700452703484205694373991710791581922410292308114513362 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.xbar_error_random.28427825784684593915593700452703484205694373991710791581922410292308114513362
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random.110819266218120493899577605676606069238199278609173642200980367351397504609081
Short name T1301
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.94 seconds
Started Nov 22 03:04:30 PM PST 23
Finished Nov 22 03:05:52 PM PST 23
Peak memory 553668 kb
Host smart-a94c6662-4a03-46dc-b979-de699c617be9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110819266218120493899577605676606069238199278609173642200980367351397504609081 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.xbar_random.110819266218120493899577605676606069238199278609173642200980367351397504609081
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.62451853671566206846000395207396714746961548372530732847655125033533019400812
Short name T134
Test name
Test status
Simulation time 97702135727 ps
CPU time 1144.81 seconds
Started Nov 22 03:04:07 PM PST 23
Finished Nov 22 03:23:12 PM PST 23
Peak memory 553648 kb
Host smart-2e368228-8a75-4881-9cbb-0c76d1d66b55
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62451853671566206846000395207396714746961548372530732847655125033533019400812 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.62451853671566206846000395207396714746961548372530732847655125033533019400812
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.20204912067012632538251394936146270785829857145413038147064972560147057849675
Short name T1351
Test name
Test status
Simulation time 60576345727 ps
CPU time 1049.96 seconds
Started Nov 22 03:04:11 PM PST 23
Finished Nov 22 03:21:41 PM PST 23
Peak memory 553708 kb
Host smart-a208dc2e-c534-4d6d-821a-a9f07aef7c76
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20204912067012632538251394936146270785829857145413038147064972560147057849675 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.20204912067012632538251394936146270785829857145413038147064972560147057849675
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1806869347991635983667961307442088406032582880537007830310260932214237026389
Short name T930
Test name
Test status
Simulation time 556965727 ps
CPU time 50.02 seconds
Started Nov 22 03:04:32 PM PST 23
Finished Nov 22 03:05:23 PM PST 23
Peak memory 553716 kb
Host smart-b51e90ef-2424-4c61-81a8-857927637faa
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806869347991635983667961307442088406032582880537007830310260932214237026389 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1806869347991635983667961307442088406032582880537007830310260932214237026389
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_same_source.60444403010060794799216745533009895809588107289292204826962828380824917243686
Short name T1900
Test name
Test status
Simulation time 2498784073 ps
CPU time 70.63 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:05:31 PM PST 23
Peak memory 553696 kb
Host smart-4f447397-13d9-4b47-9002-c6ceb6087184
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60444403010060794799216745533009895809588107289292204826962828380824917243686 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.60444403010060794799216745533009895809588107289292204826962828380824917243686
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke.30566036498950474107076770103195863495370324818607310657569966429560013857674
Short name T1905
Test name
Test status
Simulation time 196985727 ps
CPU time 8.5 seconds
Started Nov 22 03:04:08 PM PST 23
Finished Nov 22 03:04:17 PM PST 23
Peak memory 552312 kb
Host smart-48f4183f-227a-49d7-a6f1-d429299e8108
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30566036498950474107076770103195863495370324818607310657569966429560013857674 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.xbar_smoke.30566036498950474107076770103195863495370324818607310657569966429560013857674
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.40728650025544807635576072937296182477805577905635900738380899045637362466147
Short name T1836
Test name
Test status
Simulation time 7758585727 ps
CPU time 83.73 seconds
Started Nov 22 03:04:24 PM PST 23
Finished Nov 22 03:05:48 PM PST 23
Peak memory 552352 kb
Host smart-645e5b8d-748a-4efe-95b6-39866f47c0d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40728650025544807635576072937296182477805577905635900738380899045637362466147 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.40728650025544807635576072937296182477805577905635900738380899045637362466147
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.88344403767568383152476816002214708906030404675107746161778556246288670523084
Short name T71
Test name
Test status
Simulation time 4856075727 ps
CPU time 91.09 seconds
Started Nov 22 03:04:15 PM PST 23
Finished Nov 22 03:05:47 PM PST 23
Peak memory 552368 kb
Host smart-fea11340-42cc-413a-aafd-90bc665d653b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88344403767568383152476816002214708906030404675107746161778556246288670523084 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.88344403767568383152476816002214708906030404675107746161778556246288670523084
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.97107951293670720686509044261858175761815813428384721879714925625250480791875
Short name T558
Test name
Test status
Simulation time 45555727 ps
CPU time 5.72 seconds
Started Nov 22 03:04:17 PM PST 23
Finished Nov 22 03:04:24 PM PST 23
Peak memory 552316 kb
Host smart-f435ae18-ee1b-41df-ba89-e12e681e666b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97107951293670720686509044261858175761815813428384721879714925625250480791875 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.97107951293670720686509044261858175761815813428384721879714925625250480791875
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all.28819257949309964371376639749307523389802461164526976054340964379642400221875
Short name T534
Test name
Test status
Simulation time 13992004073 ps
CPU time 560.66 seconds
Started Nov 22 03:04:14 PM PST 23
Finished Nov 22 03:13:35 PM PST 23
Peak memory 555872 kb
Host smart-310eab3e-43cf-493f-8dcb-f0209ce46f8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28819257949309964371376639749307523389802461164526976054340964379642400221875 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.28819257949309964371376639749307523389802461164526976054340964379642400221875
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.40693836175022404758593391842859941370859123221986937560200753069805230357763
Short name T797
Test name
Test status
Simulation time 4815189184 ps
CPU time 379.13 seconds
Started Nov 22 03:04:15 PM PST 23
Finished Nov 22 03:10:35 PM PST 23
Peak memory 557192 kb
Host smart-200d44ae-79bc-469f-bc07-4492dd693d09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40693836175022404758593391842859941370859123221986937560200753069805230357763 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.40693836175022404758593391842859941370859123221986937560200753
069805230357763
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.88070693343669280256467290224802273265661964300040033388283282053681185614077
Short name T1818
Test name
Test status
Simulation time 4815189184 ps
CPU time 320.24 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:09:41 PM PST 23
Peak memory 559772 kb
Host smart-b36cd51d-90cf-415e-be14-6af7983a087a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88070693343669280256467290224802273265661964300040033388283282053681185614077 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.880706933436692802564672902248022732656619643000400333882832
82053681185614077
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.52576553162288598560372057853270059343065350664040106998628730336547732326374
Short name T1578
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.99 seconds
Started Nov 22 03:04:22 PM PST 23
Finished Nov 22 03:05:10 PM PST 23
Peak memory 553812 kb
Host smart-a7cf2cda-5265-4389-b0a2-e32a9fa0b680
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52576553162288598560372057853270059343065350664040106998628730336547732326374 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.52576553162288598560372057853270059343065350664040106998628730336547732326374
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.24788821402601934562701056056276238895077026273538936175848702407277570980971
Short name T622
Test name
Test status
Simulation time 7234930891 ps
CPU time 331.83 seconds
Started Nov 22 03:04:17 PM PST 23
Finished Nov 22 03:09:50 PM PST 23
Peak memory 622540 kb
Host smart-42ef48b2-3253-48fa-8742-c873aeb3e894
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478882140260193456270105605627
6238895077026273538936175848702407277570980971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.247888214026
01934562701056056276238895077026273538936175848702407277570980971
Directory /workspace/14.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_rw.15146149723667630762001667956713092623386947098966130474939828764210701872
Short name T991
Test name
Test status
Simulation time 5924944675 ps
CPU time 558.41 seconds
Started Nov 22 03:04:23 PM PST 23
Finished Nov 22 03:13:42 PM PST 23
Peak memory 580564 kb
Host smart-f24d88b5-2314-4a01-a563-4993fc4f5031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146149723667630762001667956713092623386947098966130474939828764210701872 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.15146149723667630762001667956713092623386947098966130474939828764210701872
Directory /workspace/14.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.5820689973344023335793953736072297680109316158471247299591531320388734988413
Short name T883
Test name
Test status
Simulation time 30604932618 ps
CPU time 2965.06 seconds
Started Nov 22 03:04:20 PM PST 23
Finished Nov 22 03:53:46 PM PST 23
Peak memory 580580 kb
Host smart-abf8b010-0603-4ac0-ba3a-321218d5748a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5820689973344023335793953736072297680
109316158471247299591531320388734988413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.5820689973344023335793953
736072297680109316158471247299591531320388734988413
Directory /workspace/14.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.chip_tl_errors.69760897591599630079338358683367726037133007073930231387562881768303079833303
Short name T975
Test name
Test status
Simulation time 3069924257 ps
CPU time 187.66 seconds
Started Nov 22 03:04:20 PM PST 23
Finished Nov 22 03:07:28 PM PST 23
Peak memory 580532 kb
Host smart-5b9ea4dd-3871-430c-b36d-a9a3ede37905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69760897591599630079338358683367726037133007073930231387562881768303079833303 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.69760897591599630079338358683367726037133007073930231387562881768303079833303
Directory /workspace/14.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device.67400289882669255349192591576650153674487608660162763694018976406871133797228
Short name T74
Test name
Test status
Simulation time 2590995727 ps
CPU time 101.61 seconds
Started Nov 22 03:04:23 PM PST 23
Finished Nov 22 03:06:05 PM PST 23
Peak memory 554884 kb
Host smart-72f13374-d06b-413a-88eb-214c89a9820f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67400289882669255349192591576650153674487608660162763694018976406871133797228 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.67400289882669255349192591576650153674487608660162763694018976406871133797228
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.11970378798685166968578679816291319780604704010257981949063097396343917033849
Short name T1300
Test name
Test status
Simulation time 115195295727 ps
CPU time 2068.66 seconds
Started Nov 22 03:04:13 PM PST 23
Finished Nov 22 03:38:43 PM PST 23
Peak memory 554768 kb
Host smart-7f5085cc-b6d9-433b-914e-6907143e6653
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11970378798685166968578679816291319780604704010257981949063097396343917033849 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.11970378798685166968578679816291319780604704010257981949063097396343917033849
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.45182226811584946890149182445557941140729420049948755881826650955264324865081
Short name T1193
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.02 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:05:03 PM PST 23
Peak memory 553428 kb
Host smart-372a3af3-8a52-4cf1-bf75-1d90b32928a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45182226811584946890149182445557941140729420049948755881826650955264324865081 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.45182226811584946890149182445557941140729420049948755881826650955264324865081
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_random.45038397531528564122073731927924834570989554155239589589056398703534622104406
Short name T1726
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.97 seconds
Started Nov 22 03:04:20 PM PST 23
Finished Nov 22 03:05:33 PM PST 23
Peak memory 553592 kb
Host smart-587df340-419a-4406-8364-88b270b0efff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45038397531528564122073731927924834570989554155239589589056398703534622104406 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.xbar_error_random.45038397531528564122073731927924834570989554155239589589056398703534622104406
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random.44347443171268201148237504294433732694790640326886429358960958007408276190251
Short name T854
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.76 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:05:32 PM PST 23
Peak memory 553720 kb
Host smart-b12690c7-c842-48eb-8492-a39f8c853bba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44347443171268201148237504294433732694790640326886429358960958007408276190251 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.xbar_random.44347443171268201148237504294433732694790640326886429358960958007408276190251
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.46556205750165216593956007795559483263544009672840962292258273302653953688576
Short name T1183
Test name
Test status
Simulation time 97702135727 ps
CPU time 1071.34 seconds
Started Nov 22 03:04:15 PM PST 23
Finished Nov 22 03:22:07 PM PST 23
Peak memory 553664 kb
Host smart-b93198d6-61ae-4ed6-814d-0c9e97fb57fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46556205750165216593956007795559483263544009672840962292258273302653953688576 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.46556205750165216593956007795559483263544009672840962292258273302653953688576
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.41182655477471383938183399480133191496520877873777623204475041799335990680557
Short name T1397
Test name
Test status
Simulation time 60576345727 ps
CPU time 1131.02 seconds
Started Nov 22 03:04:15 PM PST 23
Finished Nov 22 03:23:07 PM PST 23
Peak memory 553692 kb
Host smart-8fb84dc8-d541-4cf5-9756-256cfb6a1941
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41182655477471383938183399480133191496520877873777623204475041799335990680557 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.41182655477471383938183399480133191496520877873777623204475041799335990680557
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.52284957300656653783491901564492968942543450225412887449861372219639788127615
Short name T712
Test name
Test status
Simulation time 556965727 ps
CPU time 47.83 seconds
Started Nov 22 03:04:15 PM PST 23
Finished Nov 22 03:05:04 PM PST 23
Peak memory 553696 kb
Host smart-96a97c53-7fb7-42dd-a663-25726195dbc2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52284957300656653783491901564492968942543450225412887449861372219639788127615 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.52284957300656653783491901564492968942543450225412887449861372219639788127615
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke.87150471231007219763364680340939065119885460566946028946666163729389304312559
Short name T1436
Test name
Test status
Simulation time 196985727 ps
CPU time 8.77 seconds
Started Nov 22 03:04:14 PM PST 23
Finished Nov 22 03:04:23 PM PST 23
Peak memory 552352 kb
Host smart-f86f02b4-c8f5-43fe-a242-2bdc20e112de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87150471231007219763364680340939065119885460566946028946666163729389304312559 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.xbar_smoke.87150471231007219763364680340939065119885460566946028946666163729389304312559
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.99680004181937572408649519720997186722312977374472752836801989781454234812255
Short name T1676
Test name
Test status
Simulation time 7758585727 ps
CPU time 85.25 seconds
Started Nov 22 03:04:15 PM PST 23
Finished Nov 22 03:05:40 PM PST 23
Peak memory 552380 kb
Host smart-e9b08e76-6c46-42c1-b733-6f19460ea1e1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99680004181937572408649519720997186722312977374472752836801989781454234812255 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.99680004181937572408649519720997186722312977374472752836801989781454234812255
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.113817355813506635227667885104896827840602670066486302749546884778675533835313
Short name T549
Test name
Test status
Simulation time 4856075727 ps
CPU time 82.6 seconds
Started Nov 22 03:04:12 PM PST 23
Finished Nov 22 03:05:35 PM PST 23
Peak memory 552460 kb
Host smart-79562a95-2c6c-471a-a4ab-7ee973ad0037
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113817355813506635227667885104896827840602670066486302749546884778675533835313 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.113817355813506635227667885104896827840602670066486302749546884778675533835313
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.65198211047461125625416615163204127695890714125793779405177971994202886891066
Short name T1484
Test name
Test status
Simulation time 45555727 ps
CPU time 5.9 seconds
Started Nov 22 03:04:20 PM PST 23
Finished Nov 22 03:04:26 PM PST 23
Peak memory 552168 kb
Host smart-e6d557cd-9e39-45cb-945d-ed0381137054
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65198211047461125625416615163204127695890714125793779405177971994202886891066 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.65198211047461125625416615163204127695890714125793779405177971994202886891066
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all.41286874753802295229254969931745254764969162191879806267558576153318097051875
Short name T744
Test name
Test status
Simulation time 13992004073 ps
CPU time 520.27 seconds
Started Nov 22 03:04:16 PM PST 23
Finished Nov 22 03:12:57 PM PST 23
Peak memory 555892 kb
Host smart-82da8539-c489-4fd9-9066-7524841f613b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41286874753802295229254969931745254764969162191879806267558576153318097051875 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.41286874753802295229254969931745254764969162191879806267558576153318097051875
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.101479118572889324350216890430413331302776081361015137860769089113595064159299
Short name T804
Test name
Test status
Simulation time 13999524073 ps
CPU time 521.31 seconds
Started Nov 22 03:04:26 PM PST 23
Finished Nov 22 03:13:08 PM PST 23
Peak memory 555760 kb
Host smart-052a75b0-83ca-42b5-ae04-1b338f1ccd55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101479118572889324350216890430413331302776081361015137860769089113595064159299 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.101479118572889324350216890430413331302776081361015137860769089113595064159299
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.101515592695205146877909080744150973546625135850984325192689494372426242591742
Short name T193
Test name
Test status
Simulation time 4815189184 ps
CPU time 358.42 seconds
Started Nov 22 03:04:25 PM PST 23
Finished Nov 22 03:10:24 PM PST 23
Peak memory 557176 kb
Host smart-53d1b53d-09a1-455c-a312-92d4f1580a59
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101515592695205146877909080744150973546625135850984325192689494372426242591742 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.1015155926952051468779090807441509735466251358509843251926894
94372426242591742
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.109219144623838008421810047497243319523359496062119495483577918699286069934752
Short name T1886
Test name
Test status
Simulation time 4815189184 ps
CPU time 340.49 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:10:01 PM PST 23
Peak memory 559628 kb
Host smart-d758d8e1-3d46-4bd2-97e8-05fddb2d8868
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109219144623838008421810047497243319523359496062119495483577918699286069934752 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.10921914462383800842181004749724331952335949606211949548357
7918699286069934752
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2479919945252317425164753091162598994156758977352001017798479886080794426173
Short name T771
Test name
Test status
Simulation time 7234930891 ps
CPU time 270.82 seconds
Started Nov 22 03:04:51 PM PST 23
Finished Nov 22 03:09:22 PM PST 23
Peak memory 622496 kb
Host smart-1d941be6-69c6-4f86-acc8-9f2ff51e1534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479919945252317425164753091162
598994156758977352001017798479886080794426173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.2479919945252
317425164753091162598994156758977352001017798479886080794426173
Directory /workspace/15.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_rw.6333842933039311211500986586057601722695467246491646739180134862215651592222
Short name T1294
Test name
Test status
Simulation time 5924944675 ps
CPU time 516.26 seconds
Started Nov 22 03:05:14 PM PST 23
Finished Nov 22 03:13:51 PM PST 23
Peak memory 580528 kb
Host smart-da23df35-d075-4015-97d1-359581a8abd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6333842933039311211500986586057601722695467246491646739180134862215651592222 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.6333842933039311211500986586057601722695467246491646739180134862215651592222
Directory /workspace/15.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3127311229255411036526361824662069134009409885618194852104327364759441214283
Short name T803
Test name
Test status
Simulation time 30604932618 ps
CPU time 3213.15 seconds
Started Nov 22 03:04:10 PM PST 23
Finished Nov 22 03:57:44 PM PST 23
Peak memory 580520 kb
Host smart-de969440-e2a6-4ed4-9057-380305cf6621
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127311229255411036526361824662069134
009409885618194852104327364759441214283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3127311229255411036526361
824662069134009409885618194852104327364759441214283
Directory /workspace/15.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.chip_tl_errors.38100784948719328754955340649744632929538434841673907700888191686345303086613
Short name T45
Test name
Test status
Simulation time 3069924257 ps
CPU time 185.26 seconds
Started Nov 22 03:04:22 PM PST 23
Finished Nov 22 03:07:27 PM PST 23
Peak memory 580604 kb
Host smart-e809a081-9710-4810-a765-415a3d628f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100784948719328754955340649744632929538434841673907700888191686345303086613 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.38100784948719328754955340649744632929538434841673907700888191686345303086613
Directory /workspace/15.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device.12875434714789015069838931654977480695776546975666674141552744171424812031256
Short name T542
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.66 seconds
Started Nov 22 03:04:52 PM PST 23
Finished Nov 22 03:06:39 PM PST 23
Peak memory 554904 kb
Host smart-d77bef41-e122-4ebd-9754-a154a9773066
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12875434714789015069838931654977480695776546975666674141552744171424812031256 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.12875434714789015069838931654977480695776546975666674141552744171424812031256
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.93208740227225399148392572088414751759367376932919783525303447045843643679494
Short name T835
Test name
Test status
Simulation time 115195295727 ps
CPU time 1945.64 seconds
Started Nov 22 03:05:27 PM PST 23
Finished Nov 22 03:37:53 PM PST 23
Peak memory 554788 kb
Host smart-c93be5e7-db2d-4be9-b4a8-919cc2ece2df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93208740227225399148392572088414751759367376932919783525303447045843643679494 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.93208740227225399148392572088414751759367376932919783525303447045843643679494
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.18184069235606667126180941578531832420677754006858791108949774040207217696974
Short name T475
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.85 seconds
Started Nov 22 03:05:15 PM PST 23
Finished Nov 22 03:06:02 PM PST 23
Peak memory 553436 kb
Host smart-ebc20935-90d7-4dfd-96bb-929deddbab4c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18184069235606667126180941578531832420677754006858791108949774040207217696974 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.18184069235606667126180941578531832420677754006858791108949774040207217696974
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_random.74198943770059486273826417670967479237291784046626339057533077315985636227804
Short name T860
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.53 seconds
Started Nov 22 03:04:54 PM PST 23
Finished Nov 22 03:06:11 PM PST 23
Peak memory 553544 kb
Host smart-b8748042-2a94-43d5-8d86-7e9156090e74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74198943770059486273826417670967479237291784046626339057533077315985636227804 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.xbar_error_random.74198943770059486273826417670967479237291784046626339057533077315985636227804
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random.111847276995203311378678146755908523148666895333242045984824541753184611238475
Short name T709
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.61 seconds
Started Nov 22 03:04:54 PM PST 23
Finished Nov 22 03:06:11 PM PST 23
Peak memory 553772 kb
Host smart-399013ba-b7bc-42de-b4b4-a3815fff04a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111847276995203311378678146755908523148666895333242045984824541753184611238475 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.xbar_random.111847276995203311378678146755908523148666895333242045984824541753184611238475
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.90696355180781588476414678254358739657261480232060540746296514867416614182505
Short name T471
Test name
Test status
Simulation time 97702135727 ps
CPU time 1141.13 seconds
Started Nov 22 03:05:03 PM PST 23
Finished Nov 22 03:24:05 PM PST 23
Peak memory 553584 kb
Host smart-a3f135cf-96f4-43d6-8616-a0e05b35df90
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90696355180781588476414678254358739657261480232060540746296514867416614182505 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.90696355180781588476414678254358739657261480232060540746296514867416614182505
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.6477055164942767721031881898349506866885489953215418030012633746613884404894
Short name T173
Test name
Test status
Simulation time 60576345727 ps
CPU time 1032.41 seconds
Started Nov 22 03:04:53 PM PST 23
Finished Nov 22 03:22:06 PM PST 23
Peak memory 553644 kb
Host smart-d4ef1a62-b217-49b7-b328-0e92ce74de86
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6477055164942767721031881898349506866885489953215418030012633746613884404894 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.6477055164942767721031881898349506866885489953215418030012633746613884404894
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.27116952796132189168352783934250363323264612010380117572546608023728197625800
Short name T1223
Test name
Test status
Simulation time 556965727 ps
CPU time 50.84 seconds
Started Nov 22 03:05:27 PM PST 23
Finished Nov 22 03:06:18 PM PST 23
Peak memory 553808 kb
Host smart-b4ee6a94-2550-44ce-b54b-d21020f1aa7c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27116952796132189168352783934250363323264612010380117572546608023728197625800 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.27116952796132189168352783934250363323264612010380117572546608023728197625800
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_same_source.7099974861346396029865147803393791042152017484710808217933662499688171440971
Short name T1382
Test name
Test status
Simulation time 2498784073 ps
CPU time 78.14 seconds
Started Nov 22 03:05:05 PM PST 23
Finished Nov 22 03:06:24 PM PST 23
Peak memory 553836 kb
Host smart-c30c5c2c-215e-4fd5-a892-2dfac1196886
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7099974861346396029865147803393791042152017484710808217933662499688171440971 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.7099974861346396029865147803393791042152017484710808217933662499688171440971
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke.47992804406378259528248243714780849007062179668748108725147269379903021506617
Short name T916
Test name
Test status
Simulation time 196985727 ps
CPU time 7.83 seconds
Started Nov 22 03:04:16 PM PST 23
Finished Nov 22 03:04:25 PM PST 23
Peak memory 552352 kb
Host smart-ecdf7c1e-efb4-4265-8d95-49e0af2aabda
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47992804406378259528248243714780849007062179668748108725147269379903021506617 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.xbar_smoke.47992804406378259528248243714780849007062179668748108725147269379903021506617
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.74709742529825689134841747305261698416960993212369664529346972036677114721086
Short name T899
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.47 seconds
Started Nov 22 03:04:19 PM PST 23
Finished Nov 22 03:05:50 PM PST 23
Peak memory 552324 kb
Host smart-a686d6db-88d6-459f-82cd-67f2df38ef6e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74709742529825689134841747305261698416960993212369664529346972036677114721086 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.74709742529825689134841747305261698416960993212369664529346972036677114721086
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.23505560921467826655305126156437936875727269479602683201761480908156282162685
Short name T887
Test name
Test status
Simulation time 4856075727 ps
CPU time 91.53 seconds
Started Nov 22 03:04:54 PM PST 23
Finished Nov 22 03:06:26 PM PST 23
Peak memory 552392 kb
Host smart-1abacf1a-3f68-4d69-a852-e82020cfa65e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23505560921467826655305126156437936875727269479602683201761480908156282162685 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.23505560921467826655305126156437936875727269479602683201761480908156282162685
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.63943410821423966721388659210536160680557447846194194063288354023328446049669
Short name T539
Test name
Test status
Simulation time 45555727 ps
CPU time 5.96 seconds
Started Nov 22 03:04:29 PM PST 23
Finished Nov 22 03:04:36 PM PST 23
Peak memory 552404 kb
Host smart-83890312-ab77-48f4-a23a-10c7224afb67
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63943410821423966721388659210536160680557447846194194063288354023328446049669 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.63943410821423966721388659210536160680557447846194194063288354023328446049669
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all.115638374118582293436615996167152331452655842583552534233640994211210409539697
Short name T1582
Test name
Test status
Simulation time 13992004073 ps
CPU time 574.04 seconds
Started Nov 22 03:05:08 PM PST 23
Finished Nov 22 03:14:42 PM PST 23
Peak memory 555900 kb
Host smart-9e983c2b-c0d5-4559-a5b0-be3156ad8ce5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115638374118582293436615996167152331452655842583552534233640994211210409539697 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.115638374118582293436615996167152331452655842583552534233640994211210409539697
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.93936056214700078173241238145166779421116447272317533331868171811995608315712
Short name T664
Test name
Test status
Simulation time 13999524073 ps
CPU time 517.34 seconds
Started Nov 22 03:04:53 PM PST 23
Finished Nov 22 03:13:31 PM PST 23
Peak memory 555728 kb
Host smart-6fef3443-19c6-44e5-8678-a077873778a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93936056214700078173241238145166779421116447272317533331868171811995608315712 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.93936056214700078173241238145166779421116447272317533331868171811995608315712
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.58168998943535301073644698867285666483776246394125483657126309389008680373770
Short name T130
Test name
Test status
Simulation time 4815189184 ps
CPU time 358.71 seconds
Started Nov 22 03:04:58 PM PST 23
Finished Nov 22 03:10:57 PM PST 23
Peak memory 557272 kb
Host smart-2aecb590-62fa-48b6-bd4b-5f3f83032594
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58168998943535301073644698867285666483776246394125483657126309389008680373770 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.58168998943535301073644698867285666483776246394125483657126309
389008680373770
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.9309156201312198997697523243838353192046457735465594759946742866019036806330
Short name T616
Test name
Test status
Simulation time 4815189184 ps
CPU time 315.65 seconds
Started Nov 22 03:04:53 PM PST 23
Finished Nov 22 03:10:09 PM PST 23
Peak memory 559724 kb
Host smart-8c31beee-042f-4cd4-853f-eb87a0eeb03d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9309156201312198997697523243838353192046457735465594759946742866019036806330 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.9309156201312198997697523243838353192046457735465594759946742
866019036806330
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.94341257720571908166962050858437422382142688777234602654250395062022294434007
Short name T1508
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.65 seconds
Started Nov 22 03:04:51 PM PST 23
Finished Nov 22 03:05:39 PM PST 23
Peak memory 553816 kb
Host smart-6f3c1c0e-d994-490f-9d21-9294aabb54a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94341257720571908166962050858437422382142688777234602654250395062022294434007 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.94341257720571908166962050858437422382142688777234602654250395062022294434007
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.20442925995201933352508656013495298920676972325384263658786432636731028082593
Short name T1509
Test name
Test status
Simulation time 7234930891 ps
CPU time 367.59 seconds
Started Nov 22 03:04:54 PM PST 23
Finished Nov 22 03:11:02 PM PST 23
Peak memory 622576 kb
Host smart-f0c0bd6d-729a-49f2-81b2-793f01288739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044292599520193335250865601349
5298920676972325384263658786432636731028082593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.204429259952
01933352508656013495298920676972325384263658786432636731028082593
Directory /workspace/16.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_rw.98155653596131336469584941986753772348826327594088273573453598195058948297737
Short name T1880
Test name
Test status
Simulation time 5924944675 ps
CPU time 553.06 seconds
Started Nov 22 03:05:24 PM PST 23
Finished Nov 22 03:14:38 PM PST 23
Peak memory 580536 kb
Host smart-d123736e-ea71-4c19-9487-51ff1f007e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98155653596131336469584941986753772348826327594088273573453598195058948297737 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.98155653596131336469584941986753772348826327594088273573453598195058948297737
Directory /workspace/16.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.73236091739005091216703671568296161029426576113528512471452330354859836996555
Short name T1540
Test name
Test status
Simulation time 30604932618 ps
CPU time 3066.83 seconds
Started Nov 22 03:05:27 PM PST 23
Finished Nov 22 03:56:35 PM PST 23
Peak memory 580520 kb
Host smart-8f0cbf1f-d9db-4391-bb74-597d862c8521
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7323609173900509121670367156829616102
9426576113528512471452330354859836996555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.732360917390050912167036
71568296161029426576113528512471452330354859836996555
Directory /workspace/16.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.chip_tl_errors.8428794420410921354123359807796337335118300297526042130231130318530567311706
Short name T689
Test name
Test status
Simulation time 3069924257 ps
CPU time 167.91 seconds
Started Nov 22 03:04:52 PM PST 23
Finished Nov 22 03:07:40 PM PST 23
Peak memory 580492 kb
Host smart-36fcbeec-9d40-4091-aba5-6afc2cae82bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8428794420410921354123359807796337335118300297526042130231130318530567311706 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.8428794420410921354123359807796337335118300297526042130231130318530567311706
Directory /workspace/16.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device.89387414840662778033654670181292833155056019035538762062842612556739970565195
Short name T615
Test name
Test status
Simulation time 2590995727 ps
CPU time 103.29 seconds
Started Nov 22 03:04:54 PM PST 23
Finished Nov 22 03:06:37 PM PST 23
Peak memory 554820 kb
Host smart-5a9378ce-1de5-45b6-9694-7289e6741708
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89387414840662778033654670181292833155056019035538762062842612556739970565195 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.89387414840662778033654670181292833155056019035538762062842612556739970565195
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.16664443605785503990082324292230916896303663295009325033005721037913033954054
Short name T129
Test name
Test status
Simulation time 115195295727 ps
CPU time 2004.05 seconds
Started Nov 22 03:04:52 PM PST 23
Finished Nov 22 03:38:17 PM PST 23
Peak memory 554692 kb
Host smart-b7083f8f-8e7c-4022-b2dc-1513620fb67e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664443605785503990082324292230916896303663295009325033005721037913033954054 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.16664443605785503990082324292230916896303663295009325033005721037913033954054
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.5660795903911429964221975445453321775321346568726918430887596923237468721964
Short name T1195
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.02 seconds
Started Nov 22 03:04:55 PM PST 23
Finished Nov 22 03:05:37 PM PST 23
Peak memory 553440 kb
Host smart-15019c9a-1c93-42d0-907f-98fd89d07e4e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5660795903911429964221975445453321775321346568726918430887596923237468721964 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.5660795903911429964221975445453321775321346568726918430887596923237468721964
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_random.53635883151197954301919530383050066610247138542279686436257712554274053097827
Short name T1587
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.12 seconds
Started Nov 22 03:04:56 PM PST 23
Finished Nov 22 03:06:10 PM PST 23
Peak memory 553540 kb
Host smart-515b668a-680b-4fb8-b801-1c86ab8a8c10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53635883151197954301919530383050066610247138542279686436257712554274053097827 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.xbar_error_random.53635883151197954301919530383050066610247138542279686436257712554274053097827
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random.36463821975197296936255060666106735923417063336757949097758353099425892631572
Short name T273
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.31 seconds
Started Nov 22 03:05:05 PM PST 23
Finished Nov 22 03:06:19 PM PST 23
Peak memory 553560 kb
Host smart-4f7556dc-e19a-4c42-b09c-814f4813220e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36463821975197296936255060666106735923417063336757949097758353099425892631572 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.xbar_random.36463821975197296936255060666106735923417063336757949097758353099425892631572
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.62642930522231261889237684362133793212846608149032222197983988343028418180343
Short name T750
Test name
Test status
Simulation time 97702135727 ps
CPU time 1154.45 seconds
Started Nov 22 03:04:52 PM PST 23
Finished Nov 22 03:24:07 PM PST 23
Peak memory 553668 kb
Host smart-3237930c-16f1-4b95-831c-a19fa62c3ba1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62642930522231261889237684362133793212846608149032222197983988343028418180343 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.62642930522231261889237684362133793212846608149032222197983988343028418180343
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.61333628991541476397889806707579280864690223573255289709599353928982305401587
Short name T1532
Test name
Test status
Simulation time 60576345727 ps
CPU time 1143.74 seconds
Started Nov 22 03:04:51 PM PST 23
Finished Nov 22 03:23:56 PM PST 23
Peak memory 553712 kb
Host smart-19925189-c8fb-4318-ba58-2ef0bdcef75a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61333628991541476397889806707579280864690223573255289709599353928982305401587 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.61333628991541476397889806707579280864690223573255289709599353928982305401587
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.59126517962544035186472426608072480051080506257532550393148416148413041429380
Short name T648
Test name
Test status
Simulation time 556965727 ps
CPU time 46.33 seconds
Started Nov 22 03:04:55 PM PST 23
Finished Nov 22 03:05:42 PM PST 23
Peak memory 553616 kb
Host smart-cb700aea-f8a5-4088-8b42-7dbc5f1314b9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59126517962544035186472426608072480051080506257532550393148416148413041429380 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.59126517962544035186472426608072480051080506257532550393148416148413041429380
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_same_source.70366969214258240654854962134867865239775298447694361675618814272008638299092
Short name T743
Test name
Test status
Simulation time 2498784073 ps
CPU time 74.19 seconds
Started Nov 22 03:04:52 PM PST 23
Finished Nov 22 03:06:07 PM PST 23
Peak memory 553672 kb
Host smart-2e0a240d-83e2-49a1-9655-a171a347ae0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70366969214258240654854962134867865239775298447694361675618814272008638299092 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.70366969214258240654854962134867865239775298447694361675618814272008638299092
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke.115778849014361915505922732284541178105803500124955508515416080129902909408240
Short name T1437
Test name
Test status
Simulation time 196985727 ps
CPU time 8.51 seconds
Started Nov 22 03:04:53 PM PST 23
Finished Nov 22 03:05:02 PM PST 23
Peak memory 552368 kb
Host smart-5c386174-1018-41fb-a48d-88ab4b1c49d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115778849014361915505922732284541178105803500124955508515416080129902909408240 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.xbar_smoke.115778849014361915505922732284541178105803500124955508515416080129902909408240
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.101587047809440204037672771725329246556304948148009440552560137788660241654813
Short name T940
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.36 seconds
Started Nov 22 03:04:54 PM PST 23
Finished Nov 22 03:06:24 PM PST 23
Peak memory 552384 kb
Host smart-d5bd4679-44b1-4b8f-aab8-23d02486c6d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101587047809440204037672771725329246556304948148009440552560137788660241654813 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.101587047809440204037672771725329246556304948148009440552560137788660241654813
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.77993622498591459491855627302879602219177373558490870059356605174889754177445
Short name T856
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.65 seconds
Started Nov 22 03:04:53 PM PST 23
Finished Nov 22 03:06:23 PM PST 23
Peak memory 552340 kb
Host smart-c088e85e-c122-4fff-92c0-b3e26c5bf744
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77993622498591459491855627302879602219177373558490870059356605174889754177445 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.77993622498591459491855627302879602219177373558490870059356605174889754177445
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.40061034314295114009626448533660553660969403642291282816231727228899643521099
Short name T720
Test name
Test status
Simulation time 45555727 ps
CPU time 6.03 seconds
Started Nov 22 03:05:02 PM PST 23
Finished Nov 22 03:05:08 PM PST 23
Peak memory 552356 kb
Host smart-6c093c7e-e79b-48bf-84a0-391d0a5b3683
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061034314295114009626448533660553660969403642291282816231727228899643521099 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.40061034314295114009626448533660553660969403642291282816231727228899643521099
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all.57652502743072828080720661233194257296433530963048354853862294592580561287053
Short name T227
Test name
Test status
Simulation time 13992004073 ps
CPU time 599.36 seconds
Started Nov 22 03:05:02 PM PST 23
Finished Nov 22 03:15:02 PM PST 23
Peak memory 555896 kb
Host smart-d1040d81-8986-49bf-b343-09d7b3e966e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57652502743072828080720661233194257296433530963048354853862294592580561287053 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.57652502743072828080720661233194257296433530963048354853862294592580561287053
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.93727018161877185383904080541570260863284204685815459005830382059827854767331
Short name T767
Test name
Test status
Simulation time 13999524073 ps
CPU time 537.58 seconds
Started Nov 22 03:04:56 PM PST 23
Finished Nov 22 03:13:55 PM PST 23
Peak memory 555716 kb
Host smart-cc6ef82b-a2e1-430b-835c-d322afba4277
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93727018161877185383904080541570260863284204685815459005830382059827854767331 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.93727018161877185383904080541570260863284204685815459005830382059827854767331
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.104432079968713865764445694408668113866732345491239445891693432204532034683722
Short name T466
Test name
Test status
Simulation time 4815189184 ps
CPU time 389.72 seconds
Started Nov 22 03:05:32 PM PST 23
Finished Nov 22 03:12:02 PM PST 23
Peak memory 557144 kb
Host smart-331ece3b-99d1-41da-8089-038b8f396217
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104432079968713865764445694408668113866732345491239445891693432204532034683722 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1044320799687138657644456944086681138667323454912394458916934
32204532034683722
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.41779562436809524558116791479175390127572878576296951561703535950150161628210
Short name T1123
Test name
Test status
Simulation time 4815189184 ps
CPU time 309.57 seconds
Started Nov 22 03:05:37 PM PST 23
Finished Nov 22 03:10:47 PM PST 23
Peak memory 559716 kb
Host smart-3d341576-7f24-4487-bd65-648e25a70c71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41779562436809524558116791479175390127572878576296951561703535950150161628210 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.417795624368095245581167914791753901275728785762969515617035
35950150161628210
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.85917135464321989959408022164900170307406307332203017713353792861888496132372
Short name T251
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.85 seconds
Started Nov 22 03:05:34 PM PST 23
Finished Nov 22 03:06:20 PM PST 23
Peak memory 553716 kb
Host smart-d82146ff-8f8f-418e-a716-287b12c890f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85917135464321989959408022164900170307406307332203017713353792861888496132372 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.85917135464321989959408022164900170307406307332203017713353792861888496132372
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.21568497237543408986967599859797626107238506203076513823774284986634732806320
Short name T859
Test name
Test status
Simulation time 7234930891 ps
CPU time 330.12 seconds
Started Nov 22 03:05:39 PM PST 23
Finished Nov 22 03:11:10 PM PST 23
Peak memory 622544 kb
Host smart-2245c4a2-a205-49da-bdf0-729007d145e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156849723754340898696759985979
7626107238506203076513823774284986634732806320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.215684972375
43408986967599859797626107238506203076513823774284986634732806320
Directory /workspace/17.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_rw.71984641620784127659020468422421876076596327327463097733315855098630070409015
Short name T1276
Test name
Test status
Simulation time 5924944675 ps
CPU time 527.97 seconds
Started Nov 22 03:05:02 PM PST 23
Finished Nov 22 03:13:50 PM PST 23
Peak memory 580404 kb
Host smart-20d97523-3b68-454f-ab07-119fae62edf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71984641620784127659020468422421876076596327327463097733315855098630070409015 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.71984641620784127659020468422421876076596327327463097733315855098630070409015
Directory /workspace/17.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.13574140976385298586340347541128853813281341738684939347894136410618014020061
Short name T853
Test name
Test status
Simulation time 30604932618 ps
CPU time 3291.79 seconds
Started Nov 22 03:05:01 PM PST 23
Finished Nov 22 03:59:54 PM PST 23
Peak memory 580496 kb
Host smart-19f682bc-8d0a-45c8-9d72-38f9995d1a20
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357414097638529858634034754112885381
3281341738684939347894136410618014020061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.135741409763852985863403
47541128853813281341738684939347894136410618014020061
Directory /workspace/17.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.chip_tl_errors.94201673117121913003102880048876688292008513022365499208093646509747122845333
Short name T873
Test name
Test status
Simulation time 3069924257 ps
CPU time 179.2 seconds
Started Nov 22 03:05:03 PM PST 23
Finished Nov 22 03:08:02 PM PST 23
Peak memory 580384 kb
Host smart-c140fbbf-2ca4-4307-9370-b616d8339548
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94201673117121913003102880048876688292008513022365499208093646509747122845333 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.94201673117121913003102880048876688292008513022365499208093646509747122845333
Directory /workspace/17.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device.18499733737794272722106488929800329461674001086839621682522187134557086566388
Short name T766
Test name
Test status
Simulation time 2590995727 ps
CPU time 126.24 seconds
Started Nov 22 03:05:35 PM PST 23
Finished Nov 22 03:07:42 PM PST 23
Peak memory 554808 kb
Host smart-3810f617-548d-49bb-82ff-c73e0718eca1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18499733737794272722106488929800329461674001086839621682522187134557086566388 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.18499733737794272722106488929800329461674001086839621682522187134557086566388
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.6281720918606593540537660823167259348183316682160139715463743800438345643948
Short name T1884
Test name
Test status
Simulation time 115195295727 ps
CPU time 1951.86 seconds
Started Nov 22 03:05:34 PM PST 23
Finished Nov 22 03:38:06 PM PST 23
Peak memory 554776 kb
Host smart-947d131b-fb45-4a56-ad19-9136cb2e536b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6281720918606593540537660823167259348183316682160139715463743800438345643948 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.6281720918606593540537660823167259348183316682160139715463743800438345643948
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.87572624789615287851425502014540192598757096278392548640235295019474583477829
Short name T382
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.63 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:06:26 PM PST 23
Peak memory 553376 kb
Host smart-f5fc8305-e10e-4ac9-91a0-7865fe684f97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87572624789615287851425502014540192598757096278392548640235295019474583477829 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.87572624789615287851425502014540192598757096278392548640235295019474583477829
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_random.28048874855791374545840739029904029989782529996170088487742347698471263766322
Short name T1777
Test name
Test status
Simulation time 2231375727 ps
CPU time 70.1 seconds
Started Nov 22 03:04:56 PM PST 23
Finished Nov 22 03:06:07 PM PST 23
Peak memory 553504 kb
Host smart-7b48f36c-ce49-4485-83a7-8ba2305097ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28048874855791374545840739029904029989782529996170088487742347698471263766322 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.xbar_error_random.28048874855791374545840739029904029989782529996170088487742347698471263766322
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random.14067803424158561631894090239864255114116060691849147298146013961442447439883
Short name T1708
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.65 seconds
Started Nov 22 03:05:28 PM PST 23
Finished Nov 22 03:06:51 PM PST 23
Peak memory 553756 kb
Host smart-c3aca29c-a064-4070-8a71-7820558bedf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14067803424158561631894090239864255114116060691849147298146013961442447439883 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.xbar_random.14067803424158561631894090239864255114116060691849147298146013961442447439883
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.97030457374772646655415729714753305612131220376832522288288016943259174677675
Short name T1152
Test name
Test status
Simulation time 97702135727 ps
CPU time 1068.73 seconds
Started Nov 22 03:05:03 PM PST 23
Finished Nov 22 03:22:52 PM PST 23
Peak memory 553668 kb
Host smart-6e52d904-3978-4c6a-bfd2-0a166fbc78a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97030457374772646655415729714753305612131220376832522288288016943259174677675 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.97030457374772646655415729714753305612131220376832522288288016943259174677675
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.56811822467915643339804609475677091723923812225606006506890576855130703961279
Short name T1723
Test name
Test status
Simulation time 60576345727 ps
CPU time 1121.29 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:24:24 PM PST 23
Peak memory 553592 kb
Host smart-48a7984a-9f05-46d6-85c6-5e1a49574ff7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56811822467915643339804609475677091723923812225606006506890576855130703961279 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.56811822467915643339804609475677091723923812225606006506890576855130703961279
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.17163174167378076289016453498693321384862330322263159937681882165068189333732
Short name T1608
Test name
Test status
Simulation time 556965727 ps
CPU time 48.75 seconds
Started Nov 22 03:05:29 PM PST 23
Finished Nov 22 03:06:18 PM PST 23
Peak memory 553616 kb
Host smart-af60bd16-fd6d-4383-9bc4-dc382f326d38
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163174167378076289016453498693321384862330322263159937681882165068189333732 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.17163174167378076289016453498693321384862330322263159937681882165068189333732
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_same_source.26517215941603842136311092820977808837844046406888153255154311291512415231895
Short name T248
Test name
Test status
Simulation time 2498784073 ps
CPU time 82.08 seconds
Started Nov 22 03:04:58 PM PST 23
Finished Nov 22 03:06:21 PM PST 23
Peak memory 553744 kb
Host smart-2548a338-58fe-4b05-ae38-88267e21e421
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26517215941603842136311092820977808837844046406888153255154311291512415231895 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.26517215941603842136311092820977808837844046406888153255154311291512415231895
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke.75876125134743460408093395874017075628145694606347403639428085461369377415237
Short name T747
Test name
Test status
Simulation time 196985727 ps
CPU time 8.69 seconds
Started Nov 22 03:05:01 PM PST 23
Finished Nov 22 03:05:10 PM PST 23
Peak memory 552372 kb
Host smart-3eb8820e-c5f1-4413-bb83-46be9c2ba3de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75876125134743460408093395874017075628145694606347403639428085461369377415237 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.xbar_smoke.75876125134743460408093395874017075628145694606347403639428085461369377415237
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.50985893312037579948385952114675059511414080954093107670999884980481160762916
Short name T1759
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.75 seconds
Started Nov 22 03:05:32 PM PST 23
Finished Nov 22 03:07:03 PM PST 23
Peak memory 552316 kb
Host smart-bef1972e-e6b9-4c11-9644-111822d2a8cc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50985893312037579948385952114675059511414080954093107670999884980481160762916 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.50985893312037579948385952114675059511414080954093107670999884980481160762916
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.97431991948608212527909924758478063220125203437293510482611501350909110958408
Short name T791
Test name
Test status
Simulation time 4856075727 ps
CPU time 80 seconds
Started Nov 22 03:05:04 PM PST 23
Finished Nov 22 03:06:25 PM PST 23
Peak memory 552392 kb
Host smart-1aeca9cc-c928-49de-b49e-e479b8d19904
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97431991948608212527909924758478063220125203437293510482611501350909110958408 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.97431991948608212527909924758478063220125203437293510482611501350909110958408
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.71118642518752879454461131784545850917546214943146434020211943245992605012258
Short name T1519
Test name
Test status
Simulation time 45555727 ps
CPU time 6.19 seconds
Started Nov 22 03:05:29 PM PST 23
Finished Nov 22 03:05:35 PM PST 23
Peak memory 552380 kb
Host smart-067e80f7-94bb-4d58-90dc-8ee744d385c5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71118642518752879454461131784545850917546214943146434020211943245992605012258 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.71118642518752879454461131784545850917546214943146434020211943245992605012258
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all.43274068972028261764272401625574872250604507521403916298279615850017970151280
Short name T849
Test name
Test status
Simulation time 13992004073 ps
CPU time 570.53 seconds
Started Nov 22 03:05:01 PM PST 23
Finished Nov 22 03:14:32 PM PST 23
Peak memory 555884 kb
Host smart-cdf340e4-f2c6-4aaa-98a2-398bcdaa382a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43274068972028261764272401625574872250604507521403916298279615850017970151280 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.43274068972028261764272401625574872250604507521403916298279615850017970151280
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.48265462220028078593570215166158868377593689294314605627983496097927999058371
Short name T1596
Test name
Test status
Simulation time 13999524073 ps
CPU time 505.37 seconds
Started Nov 22 03:05:27 PM PST 23
Finished Nov 22 03:13:53 PM PST 23
Peak memory 555708 kb
Host smart-3f28da1c-abcc-443c-b609-ce593189948f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48265462220028078593570215166158868377593689294314605627983496097927999058371 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.48265462220028078593570215166158868377593689294314605627983496097927999058371
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.20037654204829370498158195392467359120174868023579601681343788079430819931095
Short name T308
Test name
Test status
Simulation time 4815189184 ps
CPU time 396.46 seconds
Started Nov 22 03:05:39 PM PST 23
Finished Nov 22 03:12:17 PM PST 23
Peak memory 557276 kb
Host smart-2570e106-549a-46ad-ae7e-280549aa8eeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20037654204829370498158195392467359120174868023579601681343788079430819931095 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.20037654204829370498158195392467359120174868023579601681343788
079430819931095
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.62138722378949244173344043193426180645560246861726698726063751630569543687974
Short name T249
Test name
Test status
Simulation time 4815189184 ps
CPU time 321.98 seconds
Started Nov 22 03:04:57 PM PST 23
Finished Nov 22 03:10:19 PM PST 23
Peak memory 559696 kb
Host smart-48513ae9-21a3-4ad8-a998-dbd392f8233b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62138722378949244173344043193426180645560246861726698726063751630569543687974 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.621387223789492441733440431934261806455602468617266987260637
51630569543687974
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.38445916133137391422770760097360306292127772811910649254194576424989829234759
Short name T437
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.63 seconds
Started Nov 22 03:05:25 PM PST 23
Finished Nov 22 03:06:14 PM PST 23
Peak memory 553664 kb
Host smart-f3f31c1d-a065-4d56-a037-75b39a2f6dba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445916133137391422770760097360306292127772811910649254194576424989829234759 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.38445916133137391422770760097360306292127772811910649254194576424989829234759
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.27728194433597477181959615557814641823940530180949567725963411691115480043171
Short name T984
Test name
Test status
Simulation time 7234930891 ps
CPU time 325.75 seconds
Started Nov 22 03:05:04 PM PST 23
Finished Nov 22 03:10:30 PM PST 23
Peak memory 622480 kb
Host smart-49e58abf-65f3-4137-b8ee-bec3b006b5bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772819443359747718195961555781
4641823940530180949567725963411691115480043171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.277281944335
97477181959615557814641823940530180949567725963411691115480043171
Directory /workspace/18.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_rw.43960553378852598709762502518482164858173672100773235923932766540469739058653
Short name T690
Test name
Test status
Simulation time 5924944675 ps
CPU time 573.89 seconds
Started Nov 22 03:05:34 PM PST 23
Finished Nov 22 03:15:09 PM PST 23
Peak memory 580548 kb
Host smart-b41ac3d5-a9c2-4f68-b97b-13b0fb85c656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43960553378852598709762502518482164858173672100773235923932766540469739058653 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.43960553378852598709762502518482164858173672100773235923932766540469739058653
Directory /workspace/18.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.43644111418066246491059676873326914503391084540606923079278089971990587623254
Short name T1455
Test name
Test status
Simulation time 30604932618 ps
CPU time 2992.21 seconds
Started Nov 22 03:05:29 PM PST 23
Finished Nov 22 03:55:22 PM PST 23
Peak memory 580340 kb
Host smart-5111fd88-23cc-4f90-9cbc-e60fc43a2c7d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4364411141806624649105967687332691450
3391084540606923079278089971990587623254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.436441114180662464910596
76873326914503391084540606923079278089971990587623254
Directory /workspace/18.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.chip_tl_errors.31177438292083680559866166221471077166652452263768764458379932647705236160902
Short name T1914
Test name
Test status
Simulation time 3069924257 ps
CPU time 193.69 seconds
Started Nov 22 03:05:35 PM PST 23
Finished Nov 22 03:08:49 PM PST 23
Peak memory 580524 kb
Host smart-938505d7-fed0-4732-8a47-1d3adbb87328
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31177438292083680559866166221471077166652452263768764458379932647705236160902 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.31177438292083680559866166221471077166652452263768764458379932647705236160902
Directory /workspace/18.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device.49758604215681804202349350268706586812780893273804554660159918975709042440257
Short name T881
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.97 seconds
Started Nov 22 03:05:03 PM PST 23
Finished Nov 22 03:06:53 PM PST 23
Peak memory 554736 kb
Host smart-c27e71f0-9bdb-4592-8aff-931150de10dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49758604215681804202349350268706586812780893273804554660159918975709042440257 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.49758604215681804202349350268706586812780893273804554660159918975709042440257
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.75837407619223654880367569180349562379390382210999003071217017930102769218087
Short name T590
Test name
Test status
Simulation time 115195295727 ps
CPU time 1883.77 seconds
Started Nov 22 03:04:56 PM PST 23
Finished Nov 22 03:36:21 PM PST 23
Peak memory 554780 kb
Host smart-f60e4c36-516e-44bf-8755-62331770e687
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75837407619223654880367569180349562379390382210999003071217017930102769218087 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.75837407619223654880367569180349562379390382210999003071217017930102769218087
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.82694449669950236157869838651183595579338545300654436907374448361754302079738
Short name T634
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.03 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:06:30 PM PST 23
Peak memory 553584 kb
Host smart-7e6fb42e-08b2-4e2e-939b-b7a4d73390c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82694449669950236157869838651183595579338545300654436907374448361754302079738 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.82694449669950236157869838651183595579338545300654436907374448361754302079738
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_random.94369393428021155481143709170193534945940353999524132113429750496881738763693
Short name T1429
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.04 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:07:05 PM PST 23
Peak memory 553516 kb
Host smart-668d7f23-3282-4e71-a8c8-6bd676431133
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94369393428021155481143709170193534945940353999524132113429750496881738763693 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.xbar_error_random.94369393428021155481143709170193534945940353999524132113429750496881738763693
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random.39054623909519494224424443719140801100637903268888729015219765585558112456505
Short name T1024
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.11 seconds
Started Nov 22 03:05:31 PM PST 23
Finished Nov 22 03:06:47 PM PST 23
Peak memory 553692 kb
Host smart-ae605751-3cc3-4161-8a39-93833b7a3013
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39054623909519494224424443719140801100637903268888729015219765585558112456505 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.xbar_random.39054623909519494224424443719140801100637903268888729015219765585558112456505
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.39074825271725961637553894725796307094791221510396271205550677438204864875139
Short name T330
Test name
Test status
Simulation time 97702135727 ps
CPU time 1173.53 seconds
Started Nov 22 03:05:10 PM PST 23
Finished Nov 22 03:24:44 PM PST 23
Peak memory 553664 kb
Host smart-1d7ed9ff-69e2-4fe5-bdf0-47889a495c87
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39074825271725961637553894725796307094791221510396271205550677438204864875139 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.39074825271725961637553894725796307094791221510396271205550677438204864875139
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.38569171339652062980219665299557782202753367331066726893541324291287542658198
Short name T1569
Test name
Test status
Simulation time 60576345727 ps
CPU time 1069.63 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:23:28 PM PST 23
Peak memory 553724 kb
Host smart-7760c04f-323e-4c5e-b638-837ada28b70b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38569171339652062980219665299557782202753367331066726893541324291287542658198 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.38569171339652062980219665299557782202753367331066726893541324291287542658198
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.65388192252480427548642062888991039046909929870018687396745355602413190387524
Short name T1625
Test name
Test status
Simulation time 556965727 ps
CPU time 47.87 seconds
Started Nov 22 03:05:35 PM PST 23
Finished Nov 22 03:06:24 PM PST 23
Peak memory 553712 kb
Host smart-9fab430c-c085-4819-81ee-a2f3e6e71b13
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65388192252480427548642062888991039046909929870018687396745355602413190387524 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.65388192252480427548642062888991039046909929870018687396745355602413190387524
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_same_source.90980218639938717067580314031783312020219208255941721319188659233827445198690
Short name T300
Test name
Test status
Simulation time 2498784073 ps
CPU time 80.86 seconds
Started Nov 22 03:05:32 PM PST 23
Finished Nov 22 03:06:53 PM PST 23
Peak memory 553616 kb
Host smart-3db8be21-3b4e-46dd-97ea-7a14e67a90f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90980218639938717067580314031783312020219208255941721319188659233827445198690 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.90980218639938717067580314031783312020219208255941721319188659233827445198690
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke.112756744246607867171519691185427653931307610637818112605432328980961564342283
Short name T1015
Test name
Test status
Simulation time 196985727 ps
CPU time 9.09 seconds
Started Nov 22 03:04:56 PM PST 23
Finished Nov 22 03:05:06 PM PST 23
Peak memory 552336 kb
Host smart-45d4abf6-aa72-4e17-90be-87112a6fcfa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112756744246607867171519691185427653931307610637818112605432328980961564342283 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.xbar_smoke.112756744246607867171519691185427653931307610637818112605432328980961564342283
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.57083663597837856995671166788789338902685735744491262186711222161326135299009
Short name T421
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.62 seconds
Started Nov 22 03:05:25 PM PST 23
Finished Nov 22 03:06:56 PM PST 23
Peak memory 552292 kb
Host smart-142c9055-86cb-409f-810e-edc49a92533b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57083663597837856995671166788789338902685735744491262186711222161326135299009 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.57083663597837856995671166788789338902685735744491262186711222161326135299009
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.67199185322508219392829471379417371520142421319962525809372435532256509471417
Short name T1876
Test name
Test status
Simulation time 4856075727 ps
CPU time 91.86 seconds
Started Nov 22 03:04:57 PM PST 23
Finished Nov 22 03:06:29 PM PST 23
Peak memory 552324 kb
Host smart-2d85cd31-e9b6-4598-bd87-fb16e3b31535
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67199185322508219392829471379417371520142421319962525809372435532256509471417 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.67199185322508219392829471379417371520142421319962525809372435532256509471417
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.53885351355937893073806796367969724468324578964195744233817855403155543292732
Short name T1747
Test name
Test status
Simulation time 45555727 ps
CPU time 6.04 seconds
Started Nov 22 03:04:56 PM PST 23
Finished Nov 22 03:05:03 PM PST 23
Peak memory 552364 kb
Host smart-8d81c5f5-6a0b-4cb3-abcd-49704a6b1f89
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53885351355937893073806796367969724468324578964195744233817855403155543292732 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.53885351355937893073806796367969724468324578964195744233817855403155543292732
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all.103414096683364887704694115843442374108412042522445284748983892590675312389624
Short name T568
Test name
Test status
Simulation time 13992004073 ps
CPU time 576.98 seconds
Started Nov 22 03:05:06 PM PST 23
Finished Nov 22 03:14:43 PM PST 23
Peak memory 555868 kb
Host smart-494a874d-e53f-49ea-a19a-ddb30648f0cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103414096683364887704694115843442374108412042522445284748983892590675312389624 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.103414096683364887704694115843442374108412042522445284748983892590675312389624
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.75129906960397670475039552426229206653665834438624247119467034944358658118641
Short name T1460
Test name
Test status
Simulation time 13999524073 ps
CPU time 504.57 seconds
Started Nov 22 03:05:10 PM PST 23
Finished Nov 22 03:13:35 PM PST 23
Peak memory 555716 kb
Host smart-0e931570-4a8a-42b4-910e-bdfd11a7182a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75129906960397670475039552426229206653665834438624247119467034944358658118641 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.75129906960397670475039552426229206653665834438624247119467034944358658118641
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.112694880793986745639672256881905096443447350048207847594570038827780230373114
Short name T1072
Test name
Test status
Simulation time 4815189184 ps
CPU time 400.62 seconds
Started Nov 22 03:05:05 PM PST 23
Finished Nov 22 03:11:47 PM PST 23
Peak memory 557328 kb
Host smart-6717fcce-627d-4afc-9851-fbd11919efd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112694880793986745639672256881905096443447350048207847594570038827780230373114 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1126948807939867456396722568819050964434473500482078475945700
38827780230373114
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.109652228895537065010739482122029031502085379636165059068140213169212982514192
Short name T1600
Test name
Test status
Simulation time 4815189184 ps
CPU time 336.56 seconds
Started Nov 22 03:05:39 PM PST 23
Finished Nov 22 03:11:17 PM PST 23
Peak memory 559740 kb
Host smart-f966049f-8997-4473-9cb5-73dac238ba1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109652228895537065010739482122029031502085379636165059068140213169212982514192 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.10965222889553706501073948212202903150208537963616505906814
0213169212982514192
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.70557092668906587090553844356293814784725623790468930632019425082008477609032
Short name T806
Test name
Test status
Simulation time 1176995727 ps
CPU time 44.18 seconds
Started Nov 22 03:05:10 PM PST 23
Finished Nov 22 03:05:55 PM PST 23
Peak memory 553700 kb
Host smart-d88be429-3f9a-4a0e-86b0-d5a324a52e42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70557092668906587090553844356293814784725623790468930632019425082008477609032 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.70557092668906587090553844356293814784725623790468930632019425082008477609032
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.55052884010323531004648712031310869272000959074385060885964017921617427071838
Short name T85
Test name
Test status
Simulation time 7234930891 ps
CPU time 335.4 seconds
Started Nov 22 03:05:08 PM PST 23
Finished Nov 22 03:10:44 PM PST 23
Peak memory 622520 kb
Host smart-9c327d10-22de-4174-ac03-38bf70ac5dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5505288401032353100464871203131
0869272000959074385060885964017921617427071838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.550528840103
23531004648712031310869272000959074385060885964017921617427071838
Directory /workspace/19.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_rw.74142582040430995677361645841934059849582538170317626542593412943694744503606
Short name T53
Test name
Test status
Simulation time 5924944675 ps
CPU time 515.71 seconds
Started Nov 22 03:05:37 PM PST 23
Finished Nov 22 03:14:13 PM PST 23
Peak memory 580532 kb
Host smart-b8b8fdf3-2934-453f-b9a9-786cd85fd127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74142582040430995677361645841934059849582538170317626542593412943694744503606 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.74142582040430995677361645841934059849582538170317626542593412943694744503606
Directory /workspace/19.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.92706884352214173472948860725836936266530477045664730796782535640135919828859
Short name T1237
Test name
Test status
Simulation time 30604932618 ps
CPU time 3027.54 seconds
Started Nov 22 03:05:36 PM PST 23
Finished Nov 22 03:56:04 PM PST 23
Peak memory 580524 kb
Host smart-e7d7283d-9ad9-44bb-9084-b2b404d73131
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9270688435221417347294886072583693626
6530477045664730796782535640135919828859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.927068843522141734729488
60725836936266530477045664730796782535640135919828859
Directory /workspace/19.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.chip_tl_errors.98524528068034778480571136112291879029616681721803194946435659855874999943164
Short name T1713
Test name
Test status
Simulation time 3069924257 ps
CPU time 185.32 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:08:50 PM PST 23
Peak memory 580096 kb
Host smart-a402e72b-3528-40e5-b024-ddb876f2baf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98524528068034778480571136112291879029616681721803194946435659855874999943164 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.98524528068034778480571136112291879029616681721803194946435659855874999943164
Directory /workspace/19.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device.74314820357133290628312161958031679318051309840403003570345393491968443443001
Short name T1185
Test name
Test status
Simulation time 2590995727 ps
CPU time 108.43 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:07:35 PM PST 23
Peak memory 554836 kb
Host smart-4955a850-4476-4ae1-8952-d3beac9a3d13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74314820357133290628312161958031679318051309840403003570345393491968443443001 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.74314820357133290628312161958031679318051309840403003570345393491968443443001
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.13169890438559050702281791116805570384162460894947559886445386128282953414707
Short name T1068
Test name
Test status
Simulation time 115195295727 ps
CPU time 1922.44 seconds
Started Nov 22 03:05:05 PM PST 23
Finished Nov 22 03:37:08 PM PST 23
Peak memory 554652 kb
Host smart-7644cc54-be6c-4084-b12a-2e1ec36b78b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13169890438559050702281791116805570384162460894947559886445386128282953414707 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.13169890438559050702281791116805570384162460894947559886445386128282953414707
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.11411372906620901463804952319832466452477593001753247110779998702586275409362
Short name T1511
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.52 seconds
Started Nov 22 03:05:13 PM PST 23
Finished Nov 22 03:05:57 PM PST 23
Peak memory 553508 kb
Host smart-53ed8e98-8e6f-4695-a3f6-8b42e0960b31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411372906620901463804952319832466452477593001753247110779998702586275409362 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.11411372906620901463804952319832466452477593001753247110779998702586275409362
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_random.12027588511278982149176248324357885228588642282753363061286610349919922140147
Short name T1093
Test name
Test status
Simulation time 2231375727 ps
CPU time 70.72 seconds
Started Nov 22 03:05:10 PM PST 23
Finished Nov 22 03:06:22 PM PST 23
Peak memory 553448 kb
Host smart-5d926292-7d20-40e8-b386-e0c04ef8044b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12027588511278982149176248324357885228588642282753363061286610349919922140147 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.xbar_error_random.12027588511278982149176248324357885228588642282753363061286610349919922140147
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random.7616852441660928477623094012647256951146295640050753865095164064588542244413
Short name T1445
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.16 seconds
Started Nov 22 03:05:07 PM PST 23
Finished Nov 22 03:06:28 PM PST 23
Peak memory 553720 kb
Host smart-131fdeea-9b0d-4fae-a97c-4035dbff23b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7616852441660928477623094012647256951146295640050753865095164064588542244413 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.xbar_random.7616852441660928477623094012647256951146295640050753865095164064588542244413
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.67411518196639478519559636443092446096353509683099638657302584243973324769943
Short name T413
Test name
Test status
Simulation time 97702135727 ps
CPU time 1111.58 seconds
Started Nov 22 03:05:20 PM PST 23
Finished Nov 22 03:23:52 PM PST 23
Peak memory 553632 kb
Host smart-e7f4ae5f-2497-4138-b687-23258460f013
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67411518196639478519559636443092446096353509683099638657302584243973324769943 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.67411518196639478519559636443092446096353509683099638657302584243973324769943
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.20812057387026735404304167574957904884522006990199264077246077876684218884713
Short name T1753
Test name
Test status
Simulation time 60576345727 ps
CPU time 1073.55 seconds
Started Nov 22 03:05:19 PM PST 23
Finished Nov 22 03:23:13 PM PST 23
Peak memory 553800 kb
Host smart-9ed48847-c3e6-4312-a4eb-730d6bbbd8c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20812057387026735404304167574957904884522006990199264077246077876684218884713 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.20812057387026735404304167574957904884522006990199264077246077876684218884713
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_same_source.58232707980254191248946822693902667462866014260397461106681162842781845356467
Short name T1828
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.36 seconds
Started Nov 22 03:05:12 PM PST 23
Finished Nov 22 03:06:25 PM PST 23
Peak memory 553756 kb
Host smart-8089e2e4-dc29-4f69-b253-d19d87b15401
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58232707980254191248946822693902667462866014260397461106681162842781845356467 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.58232707980254191248946822693902667462866014260397461106681162842781845356467
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke.44625984229333258087330112690284181637444003996986588920854176226391255057462
Short name T1661
Test name
Test status
Simulation time 196985727 ps
CPU time 8.16 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:05:51 PM PST 23
Peak memory 552256 kb
Host smart-cbad0672-0b0f-4eab-8a81-595715713a81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44625984229333258087330112690284181637444003996986588920854176226391255057462 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.xbar_smoke.44625984229333258087330112690284181637444003996986588920854176226391255057462
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3586995742724618607250934194770133417025122928220714985651823815746604950117
Short name T674
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.49 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:07:13 PM PST 23
Peak memory 552484 kb
Host smart-74fb9f84-52b4-4872-a85e-334eed17115a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586995742724618607250934194770133417025122928220714985651823815746604950117 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3586995742724618607250934194770133417025122928220714985651823815746604950117
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.82913519464427062894806628177700575929242976953898147316176836658580750073909
Short name T1196
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.65 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:07:23 PM PST 23
Peak memory 552364 kb
Host smart-75e6e280-99f5-4bf2-843d-355d024d3b45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82913519464427062894806628177700575929242976953898147316176836658580750073909 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.82913519464427062894806628177700575929242976953898147316176836658580750073909
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.30143588942007734122330068243413730095905747210958851039029149856478661913215
Short name T1411
Test name
Test status
Simulation time 45555727 ps
CPU time 6.01 seconds
Started Nov 22 03:05:21 PM PST 23
Finished Nov 22 03:05:27 PM PST 23
Peak memory 552400 kb
Host smart-2787f1b8-de16-4f3c-a957-a0fb47158ecb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30143588942007734122330068243413730095905747210958851039029149856478661913215 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.30143588942007734122330068243413730095905747210958851039029149856478661913215
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all.21662706531332636479741625117692047401964737508988931922584135676025985564218
Short name T1599
Test name
Test status
Simulation time 13992004073 ps
CPU time 528.11 seconds
Started Nov 22 03:05:39 PM PST 23
Finished Nov 22 03:14:28 PM PST 23
Peak memory 555924 kb
Host smart-13675f94-bc6e-4bb7-888c-77a448e9f32e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662706531332636479741625117692047401964737508988931922584135676025985564218 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.21662706531332636479741625117692047401964737508988931922584135676025985564218
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.97720742604136863044780928223863993484231670654749462560615793289854115638544
Short name T425
Test name
Test status
Simulation time 13999524073 ps
CPU time 522.37 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:14:41 PM PST 23
Peak memory 555712 kb
Host smart-4692c2ac-d00a-4722-a887-fc909990f0f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97720742604136863044780928223863993484231670654749462560615793289854115638544 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.97720742604136863044780928223863993484231670654749462560615793289854115638544
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.114854389121322180772771408913858113342125783339709865522431848923205705726095
Short name T1556
Test name
Test status
Simulation time 4815189184 ps
CPU time 373.45 seconds
Started Nov 22 03:05:07 PM PST 23
Finished Nov 22 03:11:21 PM PST 23
Peak memory 557260 kb
Host smart-72e5b7ea-f040-4766-a61c-c2faa0dca208
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114854389121322180772771408913858113342125783339709865522431848923205705726095 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.1148543891213221807727714089138581133421257833397098655224318
48923205705726095
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.47138382554576293638478368733562412773008299569846638470963623956426547218094
Short name T1507
Test name
Test status
Simulation time 4815189184 ps
CPU time 335.4 seconds
Started Nov 22 03:05:40 PM PST 23
Finished Nov 22 03:11:16 PM PST 23
Peak memory 559728 kb
Host smart-584b31b5-1ad1-4a36-ae14-f60b0df31699
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47138382554576293638478368733562412773008299569846638470963623956426547218094 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.471383825545762936384783687335624127730082995698466384709636
23956426547218094
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.45226759621531852032816471865288548524557434027273557720331372468007234397742
Short name T1862
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.3 seconds
Started Nov 22 03:05:35 PM PST 23
Finished Nov 22 03:06:26 PM PST 23
Peak memory 553724 kb
Host smart-c29703e0-3d09-4cb0-ab93-a2e4bd6d2da4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45226759621531852032816471865288548524557434027273557720331372468007234397742 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.45226759621531852032816471865288548524557434027273557720331372468007234397742
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.25062605226826524273007387207502451640930981849023566994321535799936821225279
Short name T1224
Test name
Test status
Simulation time 72959944675 ps
CPU time 9278.15 seconds
Started Nov 22 03:03:04 PM PST 23
Finished Nov 22 05:37:44 PM PST 23
Peak memory 625272 kb
Host smart-84ca2553-450e-451a-898f-9a56d932bbeb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506260522682652427300738720750245164093098184902
3566994321535799936821225279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_aliasing.250626052268265242730073872075024516409309818
49023566994321535799936821225279
Directory /workspace/2.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.26368734563066750255518235795463266434099083602949894216448135743464254975125
Short name T24
Test name
Test status
Simulation time 7954924257 ps
CPU time 816.49 seconds
Started Nov 22 03:03:08 PM PST 23
Finished Nov 22 03:16:47 PM PST 23
Peak memory 580484 kb
Host smart-9cbcb873-303b-4caa-9dec-3571636d2e04
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263687345630667502555182357954
63266434099083602949894216448135743464254975125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.26368734563066750255518235
795463266434099083602949894216448135743464254975125
Directory /workspace/2.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.59295859381066542723166291838721156328335687939995319251811350245126382259509
Short name T1408
Test name
Test status
Simulation time 5984936856 ps
CPU time 337.94 seconds
Started Nov 22 03:03:48 PM PST 23
Finished Nov 22 03:09:27 PM PST 23
Peak memory 641808 kb
Host smart-c693af48-086c-4115-9ba9-b927198a0a27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59295859381066542723166291838721156328335687939995319251811350245126382259509
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_reset.59295859381066542723166291838721156328335687939995319251811350245126382259509
Directory /workspace/2.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.21654799007712575909686708356858640636099822848182427729243514575990663080251
Short name T39
Test name
Test status
Simulation time 10375158790 ps
CPU time 367.47 seconds
Started Nov 22 03:03:08 PM PST 23
Finished Nov 22 03:09:18 PM PST 23
Peak memory 576644 kb
Host smart-c76870f9-c763-4707-aa88-e5b0b78b7519
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165479900771257590968670835685864063609982284818242772
9243514575990663080251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.21654799007712575909686708356858640
636099822848182427729243514575990663080251
Directory /workspace/2.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.chip_tl_errors.114649247175953638714896197312828951611881500409785053655828100460421022632356
Short name T1648
Test name
Test status
Simulation time 3069924257 ps
CPU time 150.81 seconds
Started Nov 22 03:03:05 PM PST 23
Finished Nov 22 03:05:41 PM PST 23
Peak memory 580524 kb
Host smart-70649a22-e0ac-4752-8c4c-422dc5222e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114649247175953638714896197312828951611881500409785053655828100460421022632356 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.114649247175953638714896197312828951611881500409785053655828100460421022632356
Directory /workspace/2.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device.13615316724024210159746888738549304240249539914603377665115529813153680830925
Short name T1013
Test name
Test status
Simulation time 2590995727 ps
CPU time 99.49 seconds
Started Nov 22 03:03:31 PM PST 23
Finished Nov 22 03:05:11 PM PST 23
Peak memory 554664 kb
Host smart-b2425330-9594-4388-bb00-4fdf98b1e4cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615316724024210159746888738549304240249539914603377665115529813153680830925 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.13615316724024210159746888738549304240249539914603377665115529813153680830925
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.6846388033339431903414496702773578406292563655103484311201034866149600385937
Short name T728
Test name
Test status
Simulation time 115195295727 ps
CPU time 1850.17 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:34:32 PM PST 23
Peak memory 554788 kb
Host smart-670e0861-c94f-420f-ba99-ce2d474e6e50
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6846388033339431903414496702773578406292563655103484311201034866149600385937 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.6846388033339431903414496702773578406292563655103484311201034866149600385937
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.34197425951305557104031405486508597037401197454378536181966938455316794912091
Short name T1572
Test name
Test status
Simulation time 1171215727 ps
CPU time 41.44 seconds
Started Nov 22 03:03:11 PM PST 23
Finished Nov 22 03:03:55 PM PST 23
Peak memory 553488 kb
Host smart-39377acc-05fe-49cb-b7d3-60be271c79bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197425951305557104031405486508597037401197454378536181966938455316794912091 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.34197425951305557104031405486508597037401197454378536181966938455316794912091
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_random.55961338391049293885944953010294828169554894530924031796455426989882932009982
Short name T1228
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.64 seconds
Started Nov 22 03:03:51 PM PST 23
Finished Nov 22 03:05:03 PM PST 23
Peak memory 553452 kb
Host smart-30e388bc-644c-4880-8ba5-3261c2c65e9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55961338391049293885944953010294828169554894530924031796455426989882932009982 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.xbar_error_random.55961338391049293885944953010294828169554894530924031796455426989882932009982
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random.87107198802121347199255049398858909039815657591310145529763046475853562080834
Short name T1675
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.31 seconds
Started Nov 22 03:03:25 PM PST 23
Finished Nov 22 03:04:46 PM PST 23
Peak memory 553776 kb
Host smart-67aca5bf-b93f-484a-8940-57f4418d532e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87107198802121347199255049398858909039815657591310145529763046475853562080834 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.xbar_random.87107198802121347199255049398858909039815657591310145529763046475853562080834
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.83866389998782349933158146662512341191245895337200414760271590465873686528892
Short name T625
Test name
Test status
Simulation time 97702135727 ps
CPU time 1086.99 seconds
Started Nov 22 03:03:26 PM PST 23
Finished Nov 22 03:21:34 PM PST 23
Peak memory 553620 kb
Host smart-06e70297-1377-4e59-a300-566d635c0aa2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83866389998782349933158146662512341191245895337200414760271590465873686528892 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.83866389998782349933158146662512341191245895337200414760271590465873686528892
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.108214997809026726022568513565833195504780687441776963188952367730981451831127
Short name T751
Test name
Test status
Simulation time 60576345727 ps
CPU time 1072.48 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:21:31 PM PST 23
Peak memory 553644 kb
Host smart-1510177b-ce56-428f-957d-07bbebdd63c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108214997809026726022568513565833195504780687441776963188952367730981451831127 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.108214997809026726022568513565833195504780687441776963188952367730981451831127
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.8910856270173779148315479430632250405336325668752580917468612364993364332506
Short name T1815
Test name
Test status
Simulation time 556965727 ps
CPU time 44.76 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:04:42 PM PST 23
Peak memory 553652 kb
Host smart-a388aae5-9639-4566-b156-017b2298727c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8910856270173779148315479430632250405336325668752580917468612364993364332506 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.8910856270173779148315479430632250405336325668752580917468612364993364332506
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_same_source.23802863822133897838935081472030749984918045223690439388598291714510365875592
Short name T1163
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.5 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:04:48 PM PST 23
Peak memory 553736 kb
Host smart-d68c7ac0-af15-4b22-86cd-47101c1d92d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23802863822133897838935081472030749984918045223690439388598291714510365875592 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.23802863822133897838935081472030749984918045223690439388598291714510365875592
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke.71615828035330371003815247248020969873774380200249792898388773654304118929870
Short name T1720
Test name
Test status
Simulation time 196985727 ps
CPU time 9.06 seconds
Started Nov 22 03:03:28 PM PST 23
Finished Nov 22 03:03:38 PM PST 23
Peak memory 552356 kb
Host smart-b8d84138-984a-4430-a7be-cdb8da7a8a70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71615828035330371003815247248020969873774380200249792898388773654304118929870 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.xbar_smoke.71615828035330371003815247248020969873774380200249792898388773654304118929870
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.39346779131857716883725992135244261604412908278048010252711309628626423853042
Short name T1916
Test name
Test status
Simulation time 7758585727 ps
CPU time 83.67 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 03:04:58 PM PST 23
Peak memory 552324 kb
Host smart-805a8c4e-13dc-40ac-ae38-04fbe6f7b5b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39346779131857716883725992135244261604412908278048010252711309628626423853042 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.39346779131857716883725992135244261604412908278048010252711309628626423853042
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.79148142204332484089063887149108924066665451485931191694362125229186706753453
Short name T978
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.16 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:05:03 PM PST 23
Peak memory 552384 kb
Host smart-16ea8798-d2b9-4dd1-863e-63da0bdc6e4a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79148142204332484089063887149108924066665451485931191694362125229186706753453 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.79148142204332484089063887149108924066665451485931191694362125229186706753453
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.20597479442408891761344887368038399751593099941610612548654136806145224517349
Short name T1641
Test name
Test status
Simulation time 45555727 ps
CPU time 5.79 seconds
Started Nov 22 03:03:28 PM PST 23
Finished Nov 22 03:03:34 PM PST 23
Peak memory 552288 kb
Host smart-9dbcf0b3-a930-4630-8a01-a9ffb493b41b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20597479442408891761344887368038399751593099941610612548654136806145224517349 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.20597479442408891761344887368038399751593099941610612548654136806145224517349
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all.56968956328729827940479275309192099150497023836321186327160732177406132977969
Short name T1286
Test name
Test status
Simulation time 13992004073 ps
CPU time 543.92 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:12:39 PM PST 23
Peak memory 555896 kb
Host smart-11b21f5b-4b88-4069-a959-06084d95bb54
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56968956328729827940479275309192099150497023836321186327160732177406132977969 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.56968956328729827940479275309192099150497023836321186327160732177406132977969
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.50049232874336872174359890483726708503802758075407742113531103449035532046767
Short name T1607
Test name
Test status
Simulation time 13999524073 ps
CPU time 505.3 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:12:22 PM PST 23
Peak memory 555660 kb
Host smart-2eff0ace-df5d-4f5d-82b7-136cfae6f566
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50049232874336872174359890483726708503802758075407742113531103449035532046767 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.50049232874336872174359890483726708503802758075407742113531103449035532046767
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.35000762041451050523389038573750107196499362478155000843369419401679182572867
Short name T63
Test name
Test status
Simulation time 4815189184 ps
CPU time 368.68 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:09:47 PM PST 23
Peak memory 557200 kb
Host smart-c7c4d19e-ccb0-4c0b-941e-7e0a3edad752
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35000762041451050523389038573750107196499362478155000843369419401679182572867 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.350007620414510505233890385737501071964993624781550008433694194
01679182572867
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.95233988641469963994327508532579378491718215342964124129877225533937702139093
Short name T716
Test name
Test status
Simulation time 4815189184 ps
CPU time 316.16 seconds
Started Nov 22 03:03:28 PM PST 23
Finished Nov 22 03:08:44 PM PST 23
Peak memory 559668 kb
Host smart-c876b240-5067-4a62-ab14-49182a6ca8cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95233988641469963994327508532579378491718215342964124129877225533937702139093 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.9523398864146996399432750853257937849171821534296412412987722
5533937702139093
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.104774698485609358620358548281003110258457932706192893126526212153830362617226
Short name T1396
Test name
Test status
Simulation time 1176995727 ps
CPU time 44.01 seconds
Started Nov 22 03:03:26 PM PST 23
Finished Nov 22 03:04:11 PM PST 23
Peak memory 553672 kb
Host smart-ac87d200-10a3-47a5-9d03-67445b4f58ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104774698485609358620358548281003110258457932706192893126526212153830362617226 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.104774698485609358620358548281003110258457932706192893126526212153830362617226
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.chip_tl_errors.19406299459926674710761786143931145670607447899356868241242345221904121756925
Short name T1151
Test name
Test status
Simulation time 3069924257 ps
CPU time 183.78 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:08:46 PM PST 23
Peak memory 580608 kb
Host smart-46f4717e-03d6-4ad4-9d15-147fe447ece2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19406299459926674710761786143931145670607447899356868241242345221904121756925 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.19406299459926674710761786143931145670607447899356868241242345221904121756925
Directory /workspace/20.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device.967123764033881711231040143399712956720508025989684830412739826777533086174
Short name T1212
Test name
Test status
Simulation time 2590995727 ps
CPU time 104.03 seconds
Started Nov 22 03:05:21 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 554756 kb
Host smart-72dd9454-f0ca-4660-8473-056f09408cc8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967123764033881711231040143399712956720508025989684830412739826777533086174 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.967123764033881711231040143399712956720508025989684830412739826777533086174
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.22450761522172262138990260751261547065452185580917094682572770516855019539498
Short name T1906
Test name
Test status
Simulation time 115195295727 ps
CPU time 2063.27 seconds
Started Nov 22 03:05:45 PM PST 23
Finished Nov 22 03:40:10 PM PST 23
Peak memory 554756 kb
Host smart-09bd969e-5e69-4c49-bfc9-0b17baf15c22
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22450761522172262138990260751261547065452185580917094682572770516855019539498 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.22450761522172262138990260751261547065452185580917094682572770516855019539498
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.50631246432445202108138441823435241121634221290174865126105210051749315043992
Short name T555
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.31 seconds
Started Nov 22 03:05:09 PM PST 23
Finished Nov 22 03:05:53 PM PST 23
Peak memory 553488 kb
Host smart-d319f429-987d-4791-aa33-7214fe5bdd64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50631246432445202108138441823435241121634221290174865126105210051749315043992 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.50631246432445202108138441823435241121634221290174865126105210051749315043992
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_random.51842343817746543406816829885537651503846689376673566014887890595122588361552
Short name T72
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.99 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 553108 kb
Host smart-25a71bcc-fbe4-4c4d-a4e4-2b3d48ea2cf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51842343817746543406816829885537651503846689376673566014887890595122588361552 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 20.xbar_error_random.51842343817746543406816829885537651503846689376673566014887890595122588361552
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random.34653728075256984653773652783935402993160127570165132639792632807426580406442
Short name T708
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.03 seconds
Started Nov 22 03:05:10 PM PST 23
Finished Nov 22 03:06:28 PM PST 23
Peak memory 553664 kb
Host smart-60e4da3e-8307-4dcc-9e87-279443cc3b6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653728075256984653773652783935402993160127570165132639792632807426580406442 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 20.xbar_random.34653728075256984653773652783935402993160127570165132639792632807426580406442
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.97530265951621192373434964984502047933374207743553925354335879453281910165503
Short name T1660
Test name
Test status
Simulation time 97702135727 ps
CPU time 1100 seconds
Started Nov 22 03:05:41 PM PST 23
Finished Nov 22 03:24:01 PM PST 23
Peak memory 553592 kb
Host smart-f43fc692-1791-4b8e-9647-a2a0a6e8e650
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97530265951621192373434964984502047933374207743553925354335879453281910165503 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.97530265951621192373434964984502047933374207743553925354335879453281910165503
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.70433168676965980180400356272931835585252165252789906678176277678940222341444
Short name T299
Test name
Test status
Simulation time 60576345727 ps
CPU time 1104.15 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:24:11 PM PST 23
Peak memory 553744 kb
Host smart-2a2f8d5a-2eeb-4696-8157-d6aa11ef20d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70433168676965980180400356272931835585252165252789906678176277678940222341444 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.70433168676965980180400356272931835585252165252789906678176277678940222341444
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.73104100327932996722153053312887425927705059318145032478165242362601236161310
Short name T364
Test name
Test status
Simulation time 556965727 ps
CPU time 45.18 seconds
Started Nov 22 03:05:45 PM PST 23
Finished Nov 22 03:06:31 PM PST 23
Peak memory 553696 kb
Host smart-db83ca49-2ed2-4b10-b587-708226e9cccd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73104100327932996722153053312887425927705059318145032478165242362601236161310 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.73104100327932996722153053312887425927705059318145032478165242362601236161310
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_same_source.37834412323997077656656906529449372477699397265213180222759187222107348749710
Short name T259
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.55 seconds
Started Nov 22 03:05:06 PM PST 23
Finished Nov 22 03:06:22 PM PST 23
Peak memory 553728 kb
Host smart-8c6be730-203e-4b4b-a3b9-2e08cc78dc7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37834412323997077656656906529449372477699397265213180222759187222107348749710 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.37834412323997077656656906529449372477699397265213180222759187222107348749710
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke.100108540987975307712631811074417658953908879494023277583823413249689246020207
Short name T811
Test name
Test status
Simulation time 196985727 ps
CPU time 8.44 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:05:51 PM PST 23
Peak memory 552464 kb
Host smart-99690c1d-6fd0-492a-897a-2eb8465db408
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100108540987975307712631811074417658953908879494023277583823413249689246020207 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 20.xbar_smoke.100108540987975307712631811074417658953908879494023277583823413249689246020207
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.83905920362553457456147405352587335198543535992031904670260110030890892115025
Short name T1085
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.27 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:07:15 PM PST 23
Peak memory 552456 kb
Host smart-c8860aa2-b4dd-4b64-b7bb-3049e919f2fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83905920362553457456147405352587335198543535992031904670260110030890892115025 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.83905920362553457456147405352587335198543535992031904670260110030890892115025
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.19791911401179496374810528875880034887283487252598366475045741048280364039583
Short name T970
Test name
Test status
Simulation time 4856075727 ps
CPU time 85.11 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:07:03 PM PST 23
Peak memory 552420 kb
Host smart-8292c440-477b-4b1f-8253-52be1b6b2914
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19791911401179496374810528875880034887283487252598366475045741048280364039583 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.19791911401179496374810528875880034887283487252598366475045741048280364039583
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.69010955618182667780189970824471325385036483545651668047188503674622040590256
Short name T1746
Test name
Test status
Simulation time 45555727 ps
CPU time 6.13 seconds
Started Nov 22 03:05:04 PM PST 23
Finished Nov 22 03:05:10 PM PST 23
Peak memory 552420 kb
Host smart-c66ce955-efce-4342-b301-c8aefce12da5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69010955618182667780189970824471325385036483545651668047188503674622040590256 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.69010955618182667780189970824471325385036483545651668047188503674622040590256
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all.93897096483668649252284830892354653210807840540682458732692235738736773624754
Short name T318
Test name
Test status
Simulation time 13992004073 ps
CPU time 554.25 seconds
Started Nov 22 03:05:21 PM PST 23
Finished Nov 22 03:14:36 PM PST 23
Peak memory 555784 kb
Host smart-936332a3-efb6-4801-a4af-ab7b58bdd509
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93897096483668649252284830892354653210807840540682458732692235738736773624754 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.93897096483668649252284830892354653210807840540682458732692235738736773624754
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.64357231288318698745336485913921777311701795989311541606759559385708358538268
Short name T1917
Test name
Test status
Simulation time 13999524073 ps
CPU time 490.33 seconds
Started Nov 22 03:05:21 PM PST 23
Finished Nov 22 03:13:32 PM PST 23
Peak memory 555768 kb
Host smart-e95f11c0-6c62-4b45-810c-a2c962ddc149
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64357231288318698745336485913921777311701795989311541606759559385708358538268 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.64357231288318698745336485913921777311701795989311541606759559385708358538268
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.52979067847142330115460906156285730165123489689782969853370791317280924109502
Short name T1079
Test name
Test status
Simulation time 4815189184 ps
CPU time 370.53 seconds
Started Nov 22 03:05:40 PM PST 23
Finished Nov 22 03:11:51 PM PST 23
Peak memory 557268 kb
Host smart-e1d48029-9178-4ec6-837f-001f56364b8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52979067847142330115460906156285730165123489689782969853370791317280924109502 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.52979067847142330115460906156285730165123489689782969853370791
317280924109502
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.110774662474504033371378042423793129736824589370517194451709453642133149558310
Short name T1593
Test name
Test status
Simulation time 4815189184 ps
CPU time 319.27 seconds
Started Nov 22 03:05:21 PM PST 23
Finished Nov 22 03:10:41 PM PST 23
Peak memory 559592 kb
Host smart-43365530-ca5c-40d6-a2bb-bf9835c2ad04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110774662474504033371378042423793129736824589370517194451709453642133149558310 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.11077466247450403337137804242379312973682458937051719445170
9453642133149558310
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.25565286558607493131631781085342572013726720992325275774847448972211420809243
Short name T474
Test name
Test status
Simulation time 1176995727 ps
CPU time 42.4 seconds
Started Nov 22 03:05:16 PM PST 23
Finished Nov 22 03:05:59 PM PST 23
Peak memory 553668 kb
Host smart-8d039b00-a35f-4d3f-8dd5-dfc435739094
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25565286558607493131631781085342572013726720992325275774847448972211420809243 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.25565286558607493131631781085342572013726720992325275774847448972211420809243
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.chip_tl_errors.86280190501949032209573928030625313316228076851730707732531053744343454498313
Short name T876
Test name
Test status
Simulation time 3069924257 ps
CPU time 175.18 seconds
Started Nov 22 03:05:40 PM PST 23
Finished Nov 22 03:08:36 PM PST 23
Peak memory 580436 kb
Host smart-1fa1a73e-6197-4efb-bab5-2f725498c2d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86280190501949032209573928030625313316228076851730707732531053744343454498313 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.86280190501949032209573928030625313316228076851730707732531053744343454498313
Directory /workspace/21.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device.56885486502894679376763427967819015946554646265317567607767355723560499479032
Short name T982
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.21 seconds
Started Nov 22 03:05:21 PM PST 23
Finished Nov 22 03:07:09 PM PST 23
Peak memory 554756 kb
Host smart-8a5144ab-b718-450a-b853-4a8b55ba67a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56885486502894679376763427967819015946554646265317567607767355723560499479032 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.56885486502894679376763427967819015946554646265317567607767355723560499479032
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.18266200569012885608380880049311641250129876004088532530457339898931554027040
Short name T1116
Test name
Test status
Simulation time 115195295727 ps
CPU time 1997.94 seconds
Started Nov 22 03:05:08 PM PST 23
Finished Nov 22 03:38:26 PM PST 23
Peak memory 554804 kb
Host smart-bef303be-838c-4556-a1d0-140da3013526
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18266200569012885608380880049311641250129876004088532530457339898931554027040 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.18266200569012885608380880049311641250129876004088532530457339898931554027040
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.51868914287267488382270797701909158507105770839450195050937243730961480268891
Short name T326
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.9 seconds
Started Nov 22 03:05:22 PM PST 23
Finished Nov 22 03:06:07 PM PST 23
Peak memory 553444 kb
Host smart-ff70e3ee-1ebf-4448-bcf7-0a5db42f628e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51868914287267488382270797701909158507105770839450195050937243730961480268891 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.51868914287267488382270797701909158507105770839450195050937243730961480268891
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_random.31656061192893249118824137622238319284096077468967035671286344194450900637440
Short name T913
Test name
Test status
Simulation time 2231375727 ps
CPU time 70.73 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:06:55 PM PST 23
Peak memory 553528 kb
Host smart-21102df8-16bd-48a7-ade4-21c29f8b7f35
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31656061192893249118824137622238319284096077468967035671286344194450900637440 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 21.xbar_error_random.31656061192893249118824137622238319284096077468967035671286344194450900637440
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random.32714049386255343613136120942844167878742228924632855445635006169764041906778
Short name T1616
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.25 seconds
Started Nov 22 03:05:41 PM PST 23
Finished Nov 22 03:06:59 PM PST 23
Peak memory 553680 kb
Host smart-8227f7ad-d174-4283-832e-c52da56a6d1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32714049386255343613136120942844167878742228924632855445635006169764041906778 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 21.xbar_random.32714049386255343613136120942844167878742228924632855445635006169764041906778
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.62258158611247428099570904606735465349635767593314790862363777614928588329828
Short name T284
Test name
Test status
Simulation time 97702135727 ps
CPU time 1142.58 seconds
Started Nov 22 03:05:21 PM PST 23
Finished Nov 22 03:24:24 PM PST 23
Peak memory 553656 kb
Host smart-e01110c7-06c8-40dc-b1cf-16a9862df941
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62258158611247428099570904606735465349635767593314790862363777614928588329828 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.62258158611247428099570904606735465349635767593314790862363777614928588329828
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.77091824474999595736026783750287871639640067362056477251590762569876611406594
Short name T265
Test name
Test status
Simulation time 60576345727 ps
CPU time 1029.78 seconds
Started Nov 22 03:05:41 PM PST 23
Finished Nov 22 03:22:51 PM PST 23
Peak memory 553628 kb
Host smart-883c0f7a-ba77-4b46-b889-695449b0a352
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77091824474999595736026783750287871639640067362056477251590762569876611406594 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.77091824474999595736026783750287871639640067362056477251590762569876611406594
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.44269900051096055723002986207624636106050704711258947584373868464960432345731
Short name T1687
Test name
Test status
Simulation time 556965727 ps
CPU time 42.52 seconds
Started Nov 22 03:05:13 PM PST 23
Finished Nov 22 03:05:56 PM PST 23
Peak memory 553664 kb
Host smart-1e73ffae-b55f-4ec6-86fb-35c6f8036cda
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44269900051096055723002986207624636106050704711258947584373868464960432345731 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.44269900051096055723002986207624636106050704711258947584373868464960432345731
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_same_source.3250722592754768689426809208250901758168517491092804825236751146589999530156
Short name T1653
Test name
Test status
Simulation time 2498784073 ps
CPU time 70.67 seconds
Started Nov 22 03:05:22 PM PST 23
Finished Nov 22 03:06:33 PM PST 23
Peak memory 553712 kb
Host smart-05cbed80-7a8d-4afe-9ee6-e2fbfc14a128
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250722592754768689426809208250901758168517491092804825236751146589999530156 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3250722592754768689426809208250901758168517491092804825236751146589999530156
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke.59980475835912804049328354124768000274390528090782589319233248199568564110988
Short name T220
Test name
Test status
Simulation time 196985727 ps
CPU time 8.62 seconds
Started Nov 22 03:05:37 PM PST 23
Finished Nov 22 03:05:46 PM PST 23
Peak memory 552368 kb
Host smart-d74feb1f-33d6-4bd2-8229-4cc97fbe738d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59980475835912804049328354124768000274390528090782589319233248199568564110988 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 21.xbar_smoke.59980475835912804049328354124768000274390528090782589319233248199568564110988
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.24108268815594253576749554514582179695759695463015801008865952541997293879578
Short name T619
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.62 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:07:18 PM PST 23
Peak memory 552424 kb
Host smart-074504d7-a3da-4722-99db-f9a3ab23e46f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24108268815594253576749554514582179695759695463015801008865952541997293879578 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.24108268815594253576749554514582179695759695463015801008865952541997293879578
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.73446556495808474890067222187461649937449172735545798078103250526578423427493
Short name T1868
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.6 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 552420 kb
Host smart-2562aea5-d8e8-4e40-9f90-3894da8f657c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73446556495808474890067222187461649937449172735545798078103250526578423427493 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.73446556495808474890067222187461649937449172735545798078103250526578423427493
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.49643633571475540885939633783276443596333267474906422836285714590766742726127
Short name T492
Test name
Test status
Simulation time 45555727 ps
CPU time 6.07 seconds
Started Nov 22 03:05:24 PM PST 23
Finished Nov 22 03:05:30 PM PST 23
Peak memory 552276 kb
Host smart-5bb24022-87fa-4889-bbcd-75da8739ffeb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49643633571475540885939633783276443596333267474906422836285714590766742726127 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.49643633571475540885939633783276443596333267474906422836285714590766742726127
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all.110421881557440903158907403085430374161689328650922475596670095111465610889556
Short name T1377
Test name
Test status
Simulation time 13992004073 ps
CPU time 608.49 seconds
Started Nov 22 03:05:36 PM PST 23
Finished Nov 22 03:15:45 PM PST 23
Peak memory 555932 kb
Host smart-acf4ef63-6ce8-4558-93c3-9fc52bc082f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110421881557440903158907403085430374161689328650922475596670095111465610889556 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.110421881557440903158907403085430374161689328650922475596670095111465610889556
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.101875286978201130989080379259649464578612795281126733078640233185220144813109
Short name T264
Test name
Test status
Simulation time 13999524073 ps
CPU time 528.6 seconds
Started Nov 22 03:05:41 PM PST 23
Finished Nov 22 03:14:30 PM PST 23
Peak memory 555736 kb
Host smart-0e2c14e4-a7cd-497a-91d2-572e0fb8561b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101875286978201130989080379259649464578612795281126733078640233185220144813109 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.101875286978201130989080379259649464578612795281126733078640233185220144813109
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.24416053213512709065370633569824367848148566810454196971457328507820383622878
Short name T1354
Test name
Test status
Simulation time 4815189184 ps
CPU time 369.64 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:11:54 PM PST 23
Peak memory 557248 kb
Host smart-bb1a08c9-71e7-4578-9f9f-38f333ade9b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416053213512709065370633569824367848148566810454196971457328507820383622878 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.24416053213512709065370633569824367848148566810454196971457328
507820383622878
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.103378420465190327071168953696391169063844342444084446236726366443317974117050
Short name T551
Test name
Test status
Simulation time 4815189184 ps
CPU time 313.84 seconds
Started Nov 22 03:05:22 PM PST 23
Finished Nov 22 03:10:36 PM PST 23
Peak memory 559628 kb
Host smart-8588a708-3afe-4b7e-92bf-7e32de6b4b2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103378420465190327071168953696391169063844342444084446236726366443317974117050 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.10337842046519032707116895369639116906384434244408444623672
6366443317974117050
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.28000620198438323447721154138097578507020272021162431424056360639899591184813
Short name T759
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.02 seconds
Started Nov 22 03:05:56 PM PST 23
Finished Nov 22 03:06:43 PM PST 23
Peak memory 553716 kb
Host smart-05c35843-daf8-424f-aad4-a44b02191ba6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28000620198438323447721154138097578507020272021162431424056360639899591184813 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.28000620198438323447721154138097578507020272021162431424056360639899591184813
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.chip_tl_errors.110718109942339282241020159948145447973108324196711272628404648842316400761933
Short name T740
Test name
Test status
Simulation time 3069924257 ps
CPU time 194.24 seconds
Started Nov 22 03:05:09 PM PST 23
Finished Nov 22 03:08:24 PM PST 23
Peak memory 580524 kb
Host smart-c12c3c26-cebf-4341-9ee1-ea583283ffc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110718109942339282241020159948145447973108324196711272628404648842316400761933 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.110718109942339282241020159948145447973108324196711272628404648842316400761933
Directory /workspace/22.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device.92105710714273547871499921310135318137361267121463591076993774970603358563468
Short name T738
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.88 seconds
Started Nov 22 03:05:17 PM PST 23
Finished Nov 22 03:07:08 PM PST 23
Peak memory 554780 kb
Host smart-ff81d2ca-938a-4bee-a1e6-38f8d178227e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92105710714273547871499921310135318137361267121463591076993774970603358563468 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.92105710714273547871499921310135318137361267121463591076993774970603358563468
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.29810027522265738853411687489023962573828393128751966802182711241361397478333
Short name T447
Test name
Test status
Simulation time 115195295727 ps
CPU time 1916.51 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:37:39 PM PST 23
Peak memory 554700 kb
Host smart-f0599326-4b85-4d48-84f6-7a2c6ce30be5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29810027522265738853411687489023962573828393128751966802182711241361397478333 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.29810027522265738853411687489023962573828393128751966802182711241361397478333
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.74351975280290809587771354102690694148677609133727670527208740655493629395982
Short name T1290
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.76 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:06:32 PM PST 23
Peak memory 553496 kb
Host smart-8916714a-9da8-4665-b94b-09f44c8e9a67
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74351975280290809587771354102690694148677609133727670527208740655493629395982 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.74351975280290809587771354102690694148677609133727670527208740655493629395982
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_random.93333169478389929363514782948800969125324318065101439294810643389349510838614
Short name T1823
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.62 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:06:57 PM PST 23
Peak memory 553620 kb
Host smart-ea54f10a-b430-4d78-b6df-a2305628f704
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93333169478389929363514782948800969125324318065101439294810643389349510838614 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 22.xbar_error_random.93333169478389929363514782948800969125324318065101439294810643389349510838614
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random.95214867023032889466009278607999712940327334189011534974210521245389408441250
Short name T1038
Test name
Test status
Simulation time 2231375727 ps
CPU time 76 seconds
Started Nov 22 03:05:16 PM PST 23
Finished Nov 22 03:06:33 PM PST 23
Peak memory 553780 kb
Host smart-569e930c-aca1-4cdf-9a0a-d08d79c3121a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95214867023032889466009278607999712940327334189011534974210521245389408441250 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 22.xbar_random.95214867023032889466009278607999712940327334189011534974210521245389408441250
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.19224911454974343034153629495869698095206790782458591237322043483870662243858
Short name T822
Test name
Test status
Simulation time 97702135727 ps
CPU time 1102.45 seconds
Started Nov 22 03:05:17 PM PST 23
Finished Nov 22 03:23:40 PM PST 23
Peak memory 553692 kb
Host smart-625b3408-d118-463a-bed9-0eec18848321
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19224911454974343034153629495869698095206790782458591237322043483870662243858 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.19224911454974343034153629495869698095206790782458591237322043483870662243858
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.49358285188135489000522028121331484826617088322671450028791827927118417847292
Short name T675
Test name
Test status
Simulation time 60576345727 ps
CPU time 1101.62 seconds
Started Nov 22 03:05:30 PM PST 23
Finished Nov 22 03:23:52 PM PST 23
Peak memory 553676 kb
Host smart-926d6842-88c7-4db8-b035-7036822183a2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49358285188135489000522028121331484826617088322671450028791827927118417847292 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.49358285188135489000522028121331484826617088322671450028791827927118417847292
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.100601441761108562352922158630261940888099840121022291324481757158134245483219
Short name T1765
Test name
Test status
Simulation time 556965727 ps
CPU time 42.75 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:06:42 PM PST 23
Peak memory 553676 kb
Host smart-b2fdcd12-73a6-49d6-a416-f6a42073f8e3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100601441761108562352922158630261940888099840121022291324481757158134245483219 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.100601441761108562352922158630261940888099840121022291324481757158134245483219
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_same_source.5362845150879713726514879811024156773335078707885454691892246640917099621540
Short name T1096
Test name
Test status
Simulation time 2498784073 ps
CPU time 79.74 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:07:07 PM PST 23
Peak memory 553768 kb
Host smart-582c5f11-6114-4b57-b3b5-cbcfceacfddf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5362845150879713726514879811024156773335078707885454691892246640917099621540 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.5362845150879713726514879811024156773335078707885454691892246640917099621540
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke.74331293371642815383644471820147881473693520603771695552950353044678815034324
Short name T960
Test name
Test status
Simulation time 196985727 ps
CPU time 8.46 seconds
Started Nov 22 03:05:41 PM PST 23
Finished Nov 22 03:05:50 PM PST 23
Peak memory 552292 kb
Host smart-517e0f99-fc0a-4cf4-baff-356609f74d8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74331293371642815383644471820147881473693520603771695552950353044678815034324 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 22.xbar_smoke.74331293371642815383644471820147881473693520603771695552950353044678815034324
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.5056718736516848781471933120576617150455523617877531594608089364427656586558
Short name T1190
Test name
Test status
Simulation time 7758585727 ps
CPU time 93.44 seconds
Started Nov 22 03:05:17 PM PST 23
Finished Nov 22 03:06:51 PM PST 23
Peak memory 552392 kb
Host smart-730d5a3a-2a96-40a4-9ab3-555e8858be59
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5056718736516848781471933120576617150455523617877531594608089364427656586558 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.5056718736516848781471933120576617150455523617877531594608089364427656586558
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.77905021708318716830967685146822573393458557626229186114919560895395093539327
Short name T1686
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.76 seconds
Started Nov 22 03:05:35 PM PST 23
Finished Nov 22 03:07:05 PM PST 23
Peak memory 552376 kb
Host smart-db5c0ea4-5c44-4aae-be49-1913637664af
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77905021708318716830967685146822573393458557626229186114919560895395093539327 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.77905021708318716830967685146822573393458557626229186114919560895395093539327
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.73335422245940190341202954859980253229878520590378508602280911824721705965433
Short name T1368
Test name
Test status
Simulation time 45555727 ps
CPU time 6.04 seconds
Started Nov 22 03:05:41 PM PST 23
Finished Nov 22 03:05:48 PM PST 23
Peak memory 552284 kb
Host smart-d24a303a-3292-4f8e-a219-02f02d01393e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73335422245940190341202954859980253229878520590378508602280911824721705965433 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.73335422245940190341202954859980253229878520590378508602280911824721705965433
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all.95701639982772216896803592835482906711788572438373875508053472971530164622865
Short name T499
Test name
Test status
Simulation time 13992004073 ps
CPU time 541.32 seconds
Started Nov 22 03:05:22 PM PST 23
Finished Nov 22 03:14:24 PM PST 23
Peak memory 555828 kb
Host smart-129267e9-2597-49eb-b32f-0ca06b893273
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95701639982772216896803592835482906711788572438373875508053472971530164622865 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.95701639982772216896803592835482906711788572438373875508053472971530164622865
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.64908041540904464683559324888321349397809383322342275675289318298557578147732
Short name T919
Test name
Test status
Simulation time 13999524073 ps
CPU time 498.44 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:14:03 PM PST 23
Peak memory 555724 kb
Host smart-420b734c-e584-41da-8ee3-6e854e0dcce4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64908041540904464683559324888321349397809383322342275675289318298557578147732 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.64908041540904464683559324888321349397809383322342275675289318298557578147732
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.109469975910050234312746920240202513991447460540943981987482213786000282955776
Short name T470
Test name
Test status
Simulation time 4815189184 ps
CPU time 365.27 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:11:48 PM PST 23
Peak memory 557224 kb
Host smart-802b05d1-c089-4cca-a784-fa656f5ef917
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109469975910050234312746920240202513991447460540943981987482213786000282955776 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1094699759100502343127469202402025139914474605409439819874822
13786000282955776
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.107451960685101925681500017166709393826786242275985055320020669819396762030111
Short name T661
Test name
Test status
Simulation time 4815189184 ps
CPU time 314.27 seconds
Started Nov 22 03:05:19 PM PST 23
Finished Nov 22 03:10:34 PM PST 23
Peak memory 559728 kb
Host smart-6d60f805-1c96-4cfe-bf51-5fb297be191a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107451960685101925681500017166709393826786242275985055320020669819396762030111 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.10745196068510192568150001716670939382678624227598505532002
0669819396762030111
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.164914556986096412369568578824929341785065152773103616243453858462416473862
Short name T424
Test name
Test status
Simulation time 1176995727 ps
CPU time 41.25 seconds
Started Nov 22 03:05:18 PM PST 23
Finished Nov 22 03:06:00 PM PST 23
Peak memory 553692 kb
Host smart-e47215cb-1cd1-4d4e-a389-44e5c16fb7e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164914556986096412369568578824929341785065152773103616243453858462416473862 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.164914556986096412369568578824929341785065152773103616243453858462416473862
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device.11002914534809576511477367706435849368633561736149284279674387515893994175463
Short name T1092
Test name
Test status
Simulation time 2590995727 ps
CPU time 113.48 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:41 PM PST 23
Peak memory 554760 kb
Host smart-110260e8-91b5-43a9-87f1-9b2d1a7b5ad2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11002914534809576511477367706435849368633561736149284279674387515893994175463 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.11002914534809576511477367706435849368633561736149284279674387515893994175463
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.8791745073574624838261954620191696305235873221696543867310430949134034815810
Short name T1833
Test name
Test status
Simulation time 115195295727 ps
CPU time 1838.59 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:36:26 PM PST 23
Peak memory 554744 kb
Host smart-4c0382e6-1a52-4807-b098-0897ba72f9d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8791745073574624838261954620191696305235873221696543867310430949134034815810 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.8791745073574624838261954620191696305235873221696543867310430949134034815810
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.104891298397421288415841516952414646987696239231953793353499651601089067409565
Short name T1668
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.1 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:06:33 PM PST 23
Peak memory 553480 kb
Host smart-fe8e77cb-e02c-4469-8fd4-9b02f968f5e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104891298397421288415841516952414646987696239231953793353499651601089067409565 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.104891298397421288415841516952414646987696239231953793353499651601089067409565
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_random.455943625916230480592271784427432133344326145679916290962384268133092885669
Short name T1636
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.98 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:07:03 PM PST 23
Peak memory 553540 kb
Host smart-1a0f1862-4cfe-4b2e-8454-885a67a6c6db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455943625916230480592271784427432133344326145679916290962384268133092885669 -assert nopostproc +UVM_T
ESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 23.xbar_error_random.455943625916230480592271784427432133344326145679916290962384268133092885669
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random.45258474927455816965183797364744162260994208937538473840608884793291513755309
Short name T117
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.81 seconds
Started Nov 22 03:05:50 PM PST 23
Finished Nov 22 03:07:07 PM PST 23
Peak memory 553748 kb
Host smart-2b9cd164-c063-457f-9da3-89f7535d08ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45258474927455816965183797364744162260994208937538473840608884793291513755309 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 23.xbar_random.45258474927455816965183797364744162260994208937538473840608884793291513755309
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.49246920408582562693387683791605518707452288897271402828057654638915551244958
Short name T598
Test name
Test status
Simulation time 97702135727 ps
CPU time 1170.19 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:25:17 PM PST 23
Peak memory 553664 kb
Host smart-dd488362-2a68-4e6f-a1c5-27aada1c5496
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49246920408582562693387683791605518707452288897271402828057654638915551244958 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.49246920408582562693387683791605518707452288897271402828057654638915551244958
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.46223676920231194321243934286344513300436309476711661452520351527459330722381
Short name T607
Test name
Test status
Simulation time 60576345727 ps
CPU time 1041.98 seconds
Started Nov 22 03:05:52 PM PST 23
Finished Nov 22 03:23:14 PM PST 23
Peak memory 553760 kb
Host smart-39bc5d54-1591-49de-a1d6-b5e8ed2d1d87
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46223676920231194321243934286344513300436309476711661452520351527459330722381 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.46223676920231194321243934286344513300436309476711661452520351527459330722381
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.93443352203445760188269397312185808328541244011493108032459833361933153624745
Short name T907
Test name
Test status
Simulation time 556965727 ps
CPU time 44.26 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:06:23 PM PST 23
Peak memory 553708 kb
Host smart-21d78b8f-e078-4b92-8f20-19aacee941c6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93443352203445760188269397312185808328541244011493108032459833361933153624745 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.93443352203445760188269397312185808328541244011493108032459833361933153624745
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_same_source.30743818823483506069600545910361290108466695777240758628577225307774724737320
Short name T1752
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.99 seconds
Started Nov 22 03:05:52 PM PST 23
Finished Nov 22 03:07:05 PM PST 23
Peak memory 553756 kb
Host smart-66f87c3f-330d-4c1f-b54b-b042ffcf5f5d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30743818823483506069600545910361290108466695777240758628577225307774724737320 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.30743818823483506069600545910361290108466695777240758628577225307774724737320
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke.49002797228827885613225218751561604615884195285404067588336736538911817123179
Short name T223
Test name
Test status
Simulation time 196985727 ps
CPU time 8.37 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:05:52 PM PST 23
Peak memory 552292 kb
Host smart-0ed918c7-77cf-45d5-812c-12f56bc2e50c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49002797228827885613225218751561604615884195285404067588336736538911817123179 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 23.xbar_smoke.49002797228827885613225218751561604615884195285404067588336736538911817123179
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.30355446639783019156055916903845688834170947341263884126483216226736534676894
Short name T1285
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.69 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:16 PM PST 23
Peak memory 552384 kb
Host smart-30a4fe60-c821-46a9-8a99-32c58fd73d56
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355446639783019156055916903845688834170947341263884126483216226736534676894 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.30355446639783019156055916903845688834170947341263884126483216226736534676894
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.97044373758405057006473166791377849576059132963058824347858705589912789850504
Short name T1690
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.21 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:17 PM PST 23
Peak memory 552324 kb
Host smart-38142e53-32bd-45a7-85ca-19e7fb1182bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97044373758405057006473166791377849576059132963058824347858705589912789850504 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.97044373758405057006473166791377849576059132963058824347858705589912789850504
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.40877550143791971253076328250756839615933108916691189092215111251605587316457
Short name T1021
Test name
Test status
Simulation time 45555727 ps
CPU time 5.76 seconds
Started Nov 22 03:05:36 PM PST 23
Finished Nov 22 03:05:43 PM PST 23
Peak memory 552316 kb
Host smart-08305254-640d-46c4-9e4a-a4d42a9f391d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877550143791971253076328250756839615933108916691189092215111251605587316457 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.40877550143791971253076328250756839615933108916691189092215111251605587316457
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all.6797854305627043987695181478436828360153969876885859641326967641934116213250
Short name T226
Test name
Test status
Simulation time 13992004073 ps
CPU time 522.85 seconds
Started Nov 22 03:05:50 PM PST 23
Finished Nov 22 03:14:34 PM PST 23
Peak memory 555896 kb
Host smart-95e12657-37b2-498c-bea8-d817152abffd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6797854305627043987695181478436828360153969876885859641326967641934116213250 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.6797854305627043987695181478436828360153969876885859641326967641934116213250
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.81589631645254708292868559076781938317765796246023148872104127710773805215013
Short name T1903
Test name
Test status
Simulation time 13999524073 ps
CPU time 463.7 seconds
Started Nov 22 03:05:32 PM PST 23
Finished Nov 22 03:13:17 PM PST 23
Peak memory 555708 kb
Host smart-93a9bf48-3184-4e67-ae0b-a0b7c60ba712
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81589631645254708292868559076781938317765796246023148872104127710773805215013 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.81589631645254708292868559076781938317765796246023148872104127710773805215013
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.87525883604990154197714532991770718190383315852055370252310817459888229324876
Short name T1877
Test name
Test status
Simulation time 4815189184 ps
CPU time 352.08 seconds
Started Nov 22 03:05:33 PM PST 23
Finished Nov 22 03:11:26 PM PST 23
Peak memory 557236 kb
Host smart-87112369-a1df-4471-bffd-258cf763f4d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87525883604990154197714532991770718190383315852055370252310817459888229324876 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.87525883604990154197714532991770718190383315852055370252310817
459888229324876
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.106828443789050166042331510849503544954008586006253292388188207537738062806031
Short name T1251
Test name
Test status
Simulation time 4815189184 ps
CPU time 302.86 seconds
Started Nov 22 03:05:36 PM PST 23
Finished Nov 22 03:10:40 PM PST 23
Peak memory 559808 kb
Host smart-0d4fd9a0-941c-46ae-a38c-106b4bb8cd51
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106828443789050166042331510849503544954008586006253292388188207537738062806031 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.10682844378905016604233151084950354495400858600625329238818
8207537738062806031
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.34957689066874517034325217512176542285341078687563051886121328062083466057751
Short name T66
Test name
Test status
Simulation time 1176995727 ps
CPU time 53.52 seconds
Started Nov 22 03:05:45 PM PST 23
Finished Nov 22 03:06:39 PM PST 23
Peak memory 553776 kb
Host smart-7f656f3d-8998-4561-a2fc-39f96cec0eff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957689066874517034325217512176542285341078687563051886121328062083466057751 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.34957689066874517034325217512176542285341078687563051886121328062083466057751
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.chip_tl_errors.86303718661316741757186531992166174894296920982063682884287338645852952134507
Short name T1721
Test name
Test status
Simulation time 3069924257 ps
CPU time 165.18 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:08:30 PM PST 23
Peak memory 580480 kb
Host smart-b1d31f73-b2e8-423e-9f3e-d5ed4667cc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86303718661316741757186531992166174894296920982063682884287338645852952134507 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.86303718661316741757186531992166174894296920982063682884287338645852952134507
Directory /workspace/24.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device.82536988346064771155785901789112676057787562592224830476821092563602926787472
Short name T1249
Test name
Test status
Simulation time 2590995727 ps
CPU time 110.19 seconds
Started Nov 22 03:05:31 PM PST 23
Finished Nov 22 03:07:21 PM PST 23
Peak memory 554704 kb
Host smart-3bf3f2a9-0c40-4640-8fb3-b412d6d4c9e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82536988346064771155785901789112676057787562592224830476821092563602926787472 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.82536988346064771155785901789112676057787562592224830476821092563602926787472
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.71022260574183362795126246823465677209497666734586077753498739878550155511865
Short name T315
Test name
Test status
Simulation time 115195295727 ps
CPU time 1946.45 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:38:10 PM PST 23
Peak memory 554740 kb
Host smart-c8032983-03af-44c0-90be-bbbec03a1b3e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71022260574183362795126246823465677209497666734586077753498739878550155511865 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.71022260574183362795126246823465677209497666734586077753498739878550155511865
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.83909960767398517278605908854620902812406006350967764593430160017760329342756
Short name T127
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.54 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:06:30 PM PST 23
Peak memory 553468 kb
Host smart-2c2af074-9091-4711-a50f-4ffde6823bbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83909960767398517278605908854620902812406006350967764593430160017760329342756 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.83909960767398517278605908854620902812406006350967764593430160017760329342756
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_random.83140211314983322407794940227327304849958344296422975566489396449408805530401
Short name T1155
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.05 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 553464 kb
Host smart-87f36702-11e0-4ea1-84df-6ccad1ab37d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83140211314983322407794940227327304849958344296422975566489396449408805530401 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 24.xbar_error_random.83140211314983322407794940227327304849958344296422975566489396449408805530401
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random.23850488633040092033872126401264275765200922404149440990240506988190172353960
Short name T440
Test name
Test status
Simulation time 2231375727 ps
CPU time 70.53 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:06:53 PM PST 23
Peak memory 553680 kb
Host smart-96318d7f-5a99-4b82-8714-6c81ddd3b8de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23850488633040092033872126401264275765200922404149440990240506988190172353960 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 24.xbar_random.23850488633040092033872126401264275765200922404149440990240506988190172353960
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.64870965981572178879894653933498729207860038608737348027104943254178850498032
Short name T1628
Test name
Test status
Simulation time 97702135727 ps
CPU time 1066.38 seconds
Started Nov 22 03:05:34 PM PST 23
Finished Nov 22 03:23:21 PM PST 23
Peak memory 553652 kb
Host smart-02b7212e-5dd6-4814-bcfd-72f4a011491e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64870965981572178879894653933498729207860038608737348027104943254178850498032 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.64870965981572178879894653933498729207860038608737348027104943254178850498032
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.10502740569966761873372298941562375373069437142384443982946982441706489586068
Short name T693
Test name
Test status
Simulation time 60576345727 ps
CPU time 1085.2 seconds
Started Nov 22 03:05:40 PM PST 23
Finished Nov 22 03:23:46 PM PST 23
Peak memory 553712 kb
Host smart-566af977-f185-4011-9a89-e72f987b4587
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502740569966761873372298941562375373069437142384443982946982441706489586068 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.10502740569966761873372298941562375373069437142384443982946982441706489586068
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.32859488419737019964126329745390824312399323642373253113104517208471145536862
Short name T1827
Test name
Test status
Simulation time 556965727 ps
CPU time 47.04 seconds
Started Nov 22 03:05:31 PM PST 23
Finished Nov 22 03:06:18 PM PST 23
Peak memory 553652 kb
Host smart-aefacffc-ab45-40de-93d6-6d6387dde4eb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32859488419737019964126329745390824312399323642373253113104517208471145536862 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.32859488419737019964126329745390824312399323642373253113104517208471145536862
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_same_source.6358997603901178792404201724357863488342264676849643633110429738426250503201
Short name T1206
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.3 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:07:12 PM PST 23
Peak memory 553712 kb
Host smart-c6e37168-fcca-40eb-a0c8-f5a8ef18d716
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6358997603901178792404201724357863488342264676849643633110429738426250503201 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.6358997603901178792404201724357863488342264676849643633110429738426250503201
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke.100314742531065300905165435134370200674239001579520615650878864847683404105615
Short name T1534
Test name
Test status
Simulation time 196985727 ps
CPU time 8.23 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:05:52 PM PST 23
Peak memory 552332 kb
Host smart-65baceac-95e2-4ed5-a2b0-26efc9d4f938
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100314742531065300905165435134370200674239001579520615650878864847683404105615 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 24.xbar_smoke.100314742531065300905165435134370200674239001579520615650878864847683404105615
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.98211240140027883648693937125326093855616116935855966258359662153313977113170
Short name T1252
Test name
Test status
Simulation time 7758585727 ps
CPU time 85.41 seconds
Started Nov 22 03:05:33 PM PST 23
Finished Nov 22 03:06:59 PM PST 23
Peak memory 552412 kb
Host smart-94f86c75-8c3f-45dd-90b4-5d3bf7ef51bf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98211240140027883648693937125326093855616116935855966258359662153313977113170 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.98211240140027883648693937125326093855616116935855966258359662153313977113170
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.5812610728621778314178900696754363607704706735284544303038778282417125676011
Short name T519
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.65 seconds
Started Nov 22 03:05:30 PM PST 23
Finished Nov 22 03:06:59 PM PST 23
Peak memory 552416 kb
Host smart-363337a0-7b76-4b9f-bc9b-7918ffb91c1e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5812610728621778314178900696754363607704706735284544303038778282417125676011 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.5812610728621778314178900696754363607704706735284544303038778282417125676011
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.107375389480266304963873377592703806964972496738615266398188000677882840993518
Short name T1611
Test name
Test status
Simulation time 45555727 ps
CPU time 6.12 seconds
Started Nov 22 03:05:56 PM PST 23
Finished Nov 22 03:06:03 PM PST 23
Peak memory 552348 kb
Host smart-84965eef-09ec-4027-9447-c47da74a7a68
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107375389480266304963873377592703806964972496738615266398188000677882840993518 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.107375389480266304963873377592703806964972496738615266398188000677882840993518
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all.86210541072864557370406037761231829760216698093211449887975064133069389649750
Short name T1119
Test name
Test status
Simulation time 13992004073 ps
CPU time 541.91 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:14:50 PM PST 23
Peak memory 555872 kb
Host smart-edf2a936-cfd4-4ddf-9285-2db292a7fe1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86210541072864557370406037761231829760216698093211449887975064133069389649750 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.86210541072864557370406037761231829760216698093211449887975064133069389649750
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.79735996609006670143958165045727236988755305656406376485328045318816828084349
Short name T76
Test name
Test status
Simulation time 13999524073 ps
CPU time 515.71 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:14:19 PM PST 23
Peak memory 555816 kb
Host smart-d8a145f3-5893-40a1-8067-704b566aa65b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79735996609006670143958165045727236988755305656406376485328045318816828084349 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.79735996609006670143958165045727236988755305656406376485328045318816828084349
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.103310578505635094203852428245741220428521792737716985804623215130966662583402
Short name T1325
Test name
Test status
Simulation time 4815189184 ps
CPU time 355.23 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:11:39 PM PST 23
Peak memory 557256 kb
Host smart-9333054b-ea62-4935-9101-d5b23df40371
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103310578505635094203852428245741220428521792737716985804623215130966662583402 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1033105785056350942038524282457412204285217927377169858046232
15130966662583402
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.59380776562895001860875308525986142864004872213302042257421050290159283893417
Short name T1214
Test name
Test status
Simulation time 4815189184 ps
CPU time 300.49 seconds
Started Nov 22 03:05:45 PM PST 23
Finished Nov 22 03:10:46 PM PST 23
Peak memory 559720 kb
Host smart-cbd8c88c-f0aa-4509-a1ce-ab86e2478da0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59380776562895001860875308525986142864004872213302042257421050290159283893417 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.593807765628950018608753085259861428640048722133020422574210
50290159283893417
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.76364957351226409439055983180752622856538284541581652347836109646156217546078
Short name T1040
Test name
Test status
Simulation time 1176995727 ps
CPU time 52.15 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:06:36 PM PST 23
Peak memory 553808 kb
Host smart-4497a8f8-f820-4ec5-acc5-24a4d01e5577
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76364957351226409439055983180752622856538284541581652347836109646156217546078 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.76364957351226409439055983180752622856538284541581652347836109646156217546078
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device.113693466875275119832560091584865444565313799464417460922267391580179820128601
Short name T343
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.49 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:07:29 PM PST 23
Peak memory 554776 kb
Host smart-655e689f-9c6e-4578-a2d9-ef664016610f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113693466875275119832560091584865444565313799464417460922267391580179820128601 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.113693466875275119832560091584865444565313799464417460922267391580179820128601
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3534190736668330095672507030353316680495670060093428606764224363869724468284
Short name T304
Test name
Test status
Simulation time 115195295727 ps
CPU time 1918.07 seconds
Started Nov 22 03:05:45 PM PST 23
Finished Nov 22 03:37:44 PM PST 23
Peak memory 554744 kb
Host smart-646eec7b-476e-4582-960d-39c8a085b139
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534190736668330095672507030353316680495670060093428606764224363869724468284 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.3534190736668330095672507030353316680495670060093428606764224363869724468284
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.87161479320413003678217697984838175969963333214042179257374045524952017083978
Short name T1159
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.27 seconds
Started Nov 22 03:05:49 PM PST 23
Finished Nov 22 03:06:31 PM PST 23
Peak memory 553480 kb
Host smart-1577d986-c5a8-42a5-8683-223b65918e25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87161479320413003678217697984838175969963333214042179257374045524952017083978 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.87161479320413003678217697984838175969963333214042179257374045524952017083978
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_random.49792359971195345856914229088031915502941301179107058350533327686304543207934
Short name T1564
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.72 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:07:01 PM PST 23
Peak memory 553536 kb
Host smart-ec8fa149-ca61-4ba2-aca5-4b81c3d44224
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49792359971195345856914229088031915502941301179107058350533327686304543207934 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 25.xbar_error_random.49792359971195345856914229088031915502941301179107058350533327686304543207934
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random.82857490935738457233127968325661465376165971439273238791371138860813727130680
Short name T148
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.67 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:07:03 PM PST 23
Peak memory 553768 kb
Host smart-090e9ca6-b760-4bd1-8809-6fd5672adeb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82857490935738457233127968325661465376165971439273238791371138860813727130680 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 25.xbar_random.82857490935738457233127968325661465376165971439273238791371138860813727130680
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.69230729666980876332156489529926456895025181970299609383844270181487420174675
Short name T1712
Test name
Test status
Simulation time 97702135727 ps
CPU time 1121.1 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:24:20 PM PST 23
Peak memory 553596 kb
Host smart-b91b0265-e206-4057-aa7e-ec184dbf1a83
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69230729666980876332156489529926456895025181970299609383844270181487420174675 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.69230729666980876332156489529926456895025181970299609383844270181487420174675
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.51077813298237579041543846152372097022867711877442328232350748902817944713699
Short name T1416
Test name
Test status
Simulation time 60576345727 ps
CPU time 1080.78 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:23:48 PM PST 23
Peak memory 553672 kb
Host smart-fa80f451-7c02-43fe-87bd-b14bd241ff2d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51077813298237579041543846152372097022867711877442328232350748902817944713699 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.51077813298237579041543846152372097022867711877442328232350748902817944713699
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.85243513088656282059588925573238677359083595408464208977220129635349203326972
Short name T828
Test name
Test status
Simulation time 556965727 ps
CPU time 43.35 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:06:27 PM PST 23
Peak memory 553672 kb
Host smart-a8a80aab-8555-4a33-bec0-3245eeacd4dc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85243513088656282059588925573238677359083595408464208977220129635349203326972 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.85243513088656282059588925573238677359083595408464208977220129635349203326972
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_same_source.110281096929681309085327003012897545024094700304640126599854785334253193327144
Short name T1181
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.33 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:00 PM PST 23
Peak memory 553704 kb
Host smart-bd20784a-4741-4da7-9a11-9b3dbf2bbd57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110281096929681309085327003012897545024094700304640126599854785334253193327144 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.110281096929681309085327003012897545024094700304640126599854785334253193327144
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke.59184636400143811171669926401995876062681409072483350541569416105763602329959
Short name T582
Test name
Test status
Simulation time 196985727 ps
CPU time 9.47 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:05:53 PM PST 23
Peak memory 552456 kb
Host smart-f9c042fa-0de1-4f5a-876c-5c9436264aeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59184636400143811171669926401995876062681409072483350541569416105763602329959 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 25.xbar_smoke.59184636400143811171669926401995876062681409072483350541569416105763602329959
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.13797526665913150146674720297352001829561072449799197009952791032002491888098
Short name T903
Test name
Test status
Simulation time 7758585727 ps
CPU time 86.58 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:07:11 PM PST 23
Peak memory 552376 kb
Host smart-ec244ed2-1b7e-42f8-93e6-c6278c62117a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13797526665913150146674720297352001829561072449799197009952791032002491888098 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.13797526665913150146674720297352001829561072449799197009952791032002491888098
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.77555332921702612009741660594902638289777524329955286040305652241373576783581
Short name T552
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.97 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:07:08 PM PST 23
Peak memory 552360 kb
Host smart-fc718c16-53d5-4d5a-be00-e3734717a1b7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77555332921702612009741660594902638289777524329955286040305652241373576783581 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.77555332921702612009741660594902638289777524329955286040305652241373576783581
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.84329290780635203932625669432756733095493783579956741883149256617661867540111
Short name T702
Test name
Test status
Simulation time 45555727 ps
CPU time 5.82 seconds
Started Nov 22 03:05:56 PM PST 23
Finished Nov 22 03:06:02 PM PST 23
Peak memory 552360 kb
Host smart-52aa9f7f-973e-46ca-8f37-e1bde9921a14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84329290780635203932625669432756733095493783579956741883149256617661867540111 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.84329290780635203932625669432756733095493783579956741883149256617661867540111
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all.64330268081900012975513649652718148068718951320991015988938825634794664281136
Short name T746
Test name
Test status
Simulation time 13992004073 ps
CPU time 511.96 seconds
Started Nov 22 03:05:49 PM PST 23
Finished Nov 22 03:14:21 PM PST 23
Peak memory 555908 kb
Host smart-50be4726-6df2-47ce-9016-13711a13900b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64330268081900012975513649652718148068718951320991015988938825634794664281136 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.64330268081900012975513649652718148068718951320991015988938825634794664281136
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.37428853641978571671444922003338905069585881079884197785458694649268801938069
Short name T380
Test name
Test status
Simulation time 13999524073 ps
CPU time 466.17 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:13:46 PM PST 23
Peak memory 555712 kb
Host smart-1ed25884-03a5-4669-a8d6-9da55ef7ab56
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37428853641978571671444922003338905069585881079884197785458694649268801938069 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.37428853641978571671444922003338905069585881079884197785458694649268801938069
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2224604095026173770295053478596501721808347934368071964624660685889136472100
Short name T711
Test name
Test status
Simulation time 4815189184 ps
CPU time 364.2 seconds
Started Nov 22 03:06:00 PM PST 23
Finished Nov 22 03:12:04 PM PST 23
Peak memory 557220 kb
Host smart-48714841-40dd-43ce-af3e-09d2ceacce85
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224604095026173770295053478596501721808347934368071964624660685889136472100 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.222460409502617377029505347859650172180834793436807196462466068
5889136472100
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.33917058691998141764841923792288048093846506643394446041741816978878948258376
Short name T623
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.84 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:06:36 PM PST 23
Peak memory 553724 kb
Host smart-32fe5b34-e7e3-4780-9534-56026df73b54
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33917058691998141764841923792288048093846506643394446041741816978878948258376 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.33917058691998141764841923792288048093846506643394446041741816978878948258376
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.chip_tl_errors.36181468523105321581038101645265600592608295036522460198602217191180907819234
Short name T1805
Test name
Test status
Simulation time 3069924257 ps
CPU time 170.72 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:08:42 PM PST 23
Peak memory 580568 kb
Host smart-730c65fc-616b-4bcf-a7a4-ce5fa88cfb6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36181468523105321581038101645265600592608295036522460198602217191180907819234 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.36181468523105321581038101645265600592608295036522460198602217191180907819234
Directory /workspace/26.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device.35322931669183832394640734913674350810128996678205202313452766592532915833559
Short name T1169
Test name
Test status
Simulation time 2590995727 ps
CPU time 113.41 seconds
Started Nov 22 03:05:52 PM PST 23
Finished Nov 22 03:07:46 PM PST 23
Peak memory 554796 kb
Host smart-a04cdb10-5a3f-4ac1-bb17-9ce0f6b68650
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35322931669183832394640734913674350810128996678205202313452766592532915833559 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.35322931669183832394640734913674350810128996678205202313452766592532915833559
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.36098192261824130107882272317662636023391470993531945371023819054259853338844
Short name T270
Test name
Test status
Simulation time 115195295727 ps
CPU time 2017.6 seconds
Started Nov 22 03:05:52 PM PST 23
Finished Nov 22 03:39:31 PM PST 23
Peak memory 554784 kb
Host smart-96cf9675-877f-49dc-9045-3aeeb8e29e3f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098192261824130107882272317662636023391470993531945371023819054259853338844 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.36098192261824130107882272317662636023391470993531945371023819054259853338844
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.25805080104136458648944386706299438549479687109043354983172343819312362079973
Short name T250
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.3 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:06:29 PM PST 23
Peak memory 553368 kb
Host smart-fbbb7a20-3ebf-495a-8b8a-f74591b55758
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805080104136458648944386706299438549479687109043354983172343819312362079973 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.25805080104136458648944386706299438549479687109043354983172343819312362079973
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_random.86109142477475025524493992767317854171444767269281523459050103399257138194394
Short name T896
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.58 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:07:09 PM PST 23
Peak memory 553540 kb
Host smart-0b0a442d-7b9d-403d-b79b-068a925ca1db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86109142477475025524493992767317854171444767269281523459050103399257138194394 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 26.xbar_error_random.86109142477475025524493992767317854171444767269281523459050103399257138194394
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random.78756962353304061593773353196516636400261983201257759899288253578617166706800
Short name T581
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.21 seconds
Started Nov 22 03:05:53 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 553776 kb
Host smart-faf73a26-d3a5-405d-b4f1-5c96d55215d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78756962353304061593773353196516636400261983201257759899288253578617166706800 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 26.xbar_random.78756962353304061593773353196516636400261983201257759899288253578617166706800
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.49969410953018579977604937595787712338219674329109411580993957348847126598065
Short name T114
Test name
Test status
Simulation time 97702135727 ps
CPU time 1121.11 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:24:36 PM PST 23
Peak memory 553688 kb
Host smart-8c7b7b35-b18d-4df8-a52d-08ac5358eedf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49969410953018579977604937595787712338219674329109411580993957348847126598065 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.49969410953018579977604937595787712338219674329109411580993957348847126598065
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.84835504408453628388354122535867820439235403826934673704288064533924304966698
Short name T156
Test name
Test status
Simulation time 60576345727 ps
CPU time 1082.34 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:23:46 PM PST 23
Peak memory 553704 kb
Host smart-7708faf5-e379-4af9-bf53-f004478ba07b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84835504408453628388354122535867820439235403826934673704288064533924304966698 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.84835504408453628388354122535867820439235403826934673704288064533924304966698
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.92961043416769198535660219113921904903172042487832600523708067485824800845393
Short name T460
Test name
Test status
Simulation time 556965727 ps
CPU time 44.29 seconds
Started Nov 22 03:05:53 PM PST 23
Finished Nov 22 03:06:38 PM PST 23
Peak memory 553732 kb
Host smart-c629eaae-d1f5-4cd0-9cdb-52b498b0722f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92961043416769198535660219113921904903172042487832600523708067485824800845393 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.92961043416769198535660219113921904903172042487832600523708067485824800845393
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_same_source.87632074507745844022813482292616868942918121635059462284537713747440251006053
Short name T1790
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.38 seconds
Started Nov 22 03:05:39 PM PST 23
Finished Nov 22 03:06:52 PM PST 23
Peak memory 553312 kb
Host smart-98399020-3c4c-4df7-8c99-4462802aa584
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87632074507745844022813482292616868942918121635059462284537713747440251006053 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.87632074507745844022813482292616868942918121635059462284537713747440251006053
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke.22941636363567299546233551795187578647416431794205667206948279557433657844724
Short name T546
Test name
Test status
Simulation time 196985727 ps
CPU time 8.48 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:06:00 PM PST 23
Peak memory 552392 kb
Host smart-8b4b475f-34e9-4602-bad8-1a1457f0c4df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22941636363567299546233551795187578647416431794205667206948279557433657844724 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 26.xbar_smoke.22941636363567299546233551795187578647416431794205667206948279557433657844724
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.9415694301891180788373627143917769711810556183427138103562118126329279304119
Short name T1081
Test name
Test status
Simulation time 7758585727 ps
CPU time 86.02 seconds
Started Nov 22 03:05:53 PM PST 23
Finished Nov 22 03:07:19 PM PST 23
Peak memory 552408 kb
Host smart-eb293c3b-b964-4f96-b857-2e9ca6440453
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9415694301891180788373627143917769711810556183427138103562118126329279304119 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.9415694301891180788373627143917769711810556183427138103562118126329279304119
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.103515111228212985751977418397495869343253648856289187504259216538647628485384
Short name T1740
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.15 seconds
Started Nov 22 03:05:53 PM PST 23
Finished Nov 22 03:07:17 PM PST 23
Peak memory 552408 kb
Host smart-2c8eb775-07ff-49e3-a442-008820b7bcda
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103515111228212985751977418397495869343253648856289187504259216538647628485384 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.103515111228212985751977418397495869343253648856289187504259216538647628485384
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.79585770832354769513299475196639953858728307177375339402411428838279989005114
Short name T516
Test name
Test status
Simulation time 45555727 ps
CPU time 5.88 seconds
Started Nov 22 03:05:50 PM PST 23
Finished Nov 22 03:05:57 PM PST 23
Peak memory 552380 kb
Host smart-8e29e535-b126-4f2f-bcab-16e5ca6d453b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79585770832354769513299475196639953858728307177375339402411428838279989005114 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.79585770832354769513299475196639953858728307177375339402411428838279989005114
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all.41286913555003593428216566686419135529155894932068118165633150855318171905026
Short name T1008
Test name
Test status
Simulation time 13992004073 ps
CPU time 544.71 seconds
Started Nov 22 03:05:40 PM PST 23
Finished Nov 22 03:14:46 PM PST 23
Peak memory 555912 kb
Host smart-01601da6-57b6-4a21-bbfb-b83ba496a6ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41286913555003593428216566686419135529155894932068118165633150855318171905026 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.41286913555003593428216566686419135529155894932068118165633150855318171905026
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.52421290191423660855801902070634445800831019892779742925658825138650379776324
Short name T1516
Test name
Test status
Simulation time 13999524073 ps
CPU time 500.36 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:14:09 PM PST 23
Peak memory 555736 kb
Host smart-c617c576-a4c2-4c19-a7e7-e6ddef35789a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52421290191423660855801902070634445800831019892779742925658825138650379776324 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.52421290191423660855801902070634445800831019892779742925658825138650379776324
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.73904076371753052169528525705549105337371141886494575721885388011890197133622
Short name T589
Test name
Test status
Simulation time 4815189184 ps
CPU time 369.11 seconds
Started Nov 22 03:05:52 PM PST 23
Finished Nov 22 03:12:02 PM PST 23
Peak memory 557256 kb
Host smart-81956b14-e652-48cb-8ac8-304ed0d7d3f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73904076371753052169528525705549105337371141886494575721885388011890197133622 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.73904076371753052169528525705549105337371141886494575721885388
011890197133622
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.97364208123938841410331381708514570706028289290454773628158143332437654541737
Short name T1203
Test name
Test status
Simulation time 4815189184 ps
CPU time 301.48 seconds
Started Nov 22 03:05:37 PM PST 23
Finished Nov 22 03:10:39 PM PST 23
Peak memory 559664 kb
Host smart-95dd1288-f07e-409e-a2f9-859f395df843
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97364208123938841410331381708514570706028289290454773628158143332437654541737 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.973642081239388414103313817085145707060282892904547736281581
43332437654541737
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.75577772627958602532459753517986137463002469501629424428343872122892684150233
Short name T305
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.91 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:06:41 PM PST 23
Peak memory 553716 kb
Host smart-cc296cc1-34b6-4fd9-82a9-121bad93e055
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75577772627958602532459753517986137463002469501629424428343872122892684150233 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.75577772627958602532459753517986137463002469501629424428343872122892684150233
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.chip_tl_errors.51914879289197636761753974082574676634482146833342944108927288189680669820756
Short name T1872
Test name
Test status
Simulation time 3069924257 ps
CPU time 171.51 seconds
Started Nov 22 03:05:56 PM PST 23
Finished Nov 22 03:08:48 PM PST 23
Peak memory 580512 kb
Host smart-e9cf7c2f-9641-4ccb-931e-d7a28dcc9fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51914879289197636761753974082574676634482146833342944108927288189680669820756 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.51914879289197636761753974082574676634482146833342944108927288189680669820756
Directory /workspace/27.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device.5509012536536281981969127218563793287752670811628976698668024423392617042165
Short name T1399
Test name
Test status
Simulation time 2590995727 ps
CPU time 92.78 seconds
Started Nov 22 03:05:33 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 554768 kb
Host smart-eeb200ed-1c62-4569-b1ca-18f461e93c5d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5509012536536281981969127218563793287752670811628976698668024423392617042165 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.5509012536536281981969127218563793287752670811628976698668024423392617042165
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.77384536829828765854287040562409861545424127194011960564663993073439830670871
Short name T1321
Test name
Test status
Simulation time 115195295727 ps
CPU time 2036.13 seconds
Started Nov 22 03:05:30 PM PST 23
Finished Nov 22 03:39:27 PM PST 23
Peak memory 554776 kb
Host smart-41baf0f5-ae8d-4c61-ace7-5cefe6b00a08
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77384536829828765854287040562409861545424127194011960564663993073439830670871 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.77384536829828765854287040562409861545424127194011960564663993073439830670871
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.114648557984217653337185207411951469875566974525926121444657308985150523868144
Short name T204
Test name
Test status
Simulation time 1171215727 ps
CPU time 48.65 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:06:37 PM PST 23
Peak memory 553452 kb
Host smart-a54e7a06-8dba-4e12-b915-602f5fd37942
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114648557984217653337185207411951469875566974525926121444657308985150523868144 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.114648557984217653337185207411951469875566974525926121444657308985150523868144
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_random.67126696352949183363677594925345117661056504754548117313724007466665713427559
Short name T75
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.06 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:03 PM PST 23
Peak memory 553464 kb
Host smart-cc24bbf0-46ae-49c3-9407-3aec99d3a17e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67126696352949183363677594925345117661056504754548117313724007466665713427559 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 27.xbar_error_random.67126696352949183363677594925345117661056504754548117313724007466665713427559
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random.67291750486147602799822557614254787373932248762777363240653563657772131919109
Short name T1580
Test name
Test status
Simulation time 2231375727 ps
CPU time 85.5 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:07:14 PM PST 23
Peak memory 553768 kb
Host smart-7237f9de-7679-4523-9894-4626852dda02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67291750486147602799822557614254787373932248762777363240653563657772131919109 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 27.xbar_random.67291750486147602799822557614254787373932248762777363240653563657772131919109
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.36571181177845019442591549187927749687579084660089155589236362695877465577430
Short name T1568
Test name
Test status
Simulation time 60576345727 ps
CPU time 1043.7 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:23:09 PM PST 23
Peak memory 553704 kb
Host smart-b677b584-1db7-4635-840c-0af1d40135f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36571181177845019442591549187927749687579084660089155589236362695877465577430 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.36571181177845019442591549187927749687579084660089155589236362695877465577430
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.86315616973967810139985901570288713242260098843696194273957831852255715909764
Short name T1250
Test name
Test status
Simulation time 556965727 ps
CPU time 42.31 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:06:38 PM PST 23
Peak memory 553704 kb
Host smart-65ef3e39-2e36-46fe-81f2-9a8b7c866477
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86315616973967810139985901570288713242260098843696194273957831852255715909764 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.86315616973967810139985901570288713242260098843696194273957831852255715909764
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_same_source.99276690348209758918403931200461754205533421564114250173300160949402987180022
Short name T831
Test name
Test status
Simulation time 2498784073 ps
CPU time 70.6 seconds
Started Nov 22 03:05:36 PM PST 23
Finished Nov 22 03:06:47 PM PST 23
Peak memory 553684 kb
Host smart-e87875bd-63bc-4c0a-a773-fa050c72775d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99276690348209758918403931200461754205533421564114250173300160949402987180022 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.99276690348209758918403931200461754205533421564114250173300160949402987180022
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke.104321882483032434929841908600870375479601021665535951554787428024043626635106
Short name T1275
Test name
Test status
Simulation time 196985727 ps
CPU time 8.48 seconds
Started Nov 22 03:05:36 PM PST 23
Finished Nov 22 03:05:45 PM PST 23
Peak memory 552460 kb
Host smart-dc517a89-8012-4a1f-8c53-1da7f702c5f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104321882483032434929841908600870375479601021665535951554787428024043626635106 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 27.xbar_smoke.104321882483032434929841908600870375479601021665535951554787428024043626635106
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.42102341253703079162385984051586218764321402402801801393700254765165791590212
Short name T1375
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.5 seconds
Started Nov 22 03:05:29 PM PST 23
Finished Nov 22 03:06:58 PM PST 23
Peak memory 552336 kb
Host smart-01dd122e-fd48-4d26-a76a-68e1e1f5d3d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42102341253703079162385984051586218764321402402801801393700254765165791590212 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.42102341253703079162385984051586218764321402402801801393700254765165791590212
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.57174936195357488581436345520119818966133062915334628596826953875234524850604
Short name T608
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.6 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:07:13 PM PST 23
Peak memory 552408 kb
Host smart-bf6ce7cf-f388-43cf-9829-4ce04fd6930a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57174936195357488581436345520119818966133062915334628596826953875234524850604 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.57174936195357488581436345520119818966133062915334628596826953875234524850604
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.86283779164904459112606300998210100017854426807281987769034478727492949297401
Short name T1225
Test name
Test status
Simulation time 45555727 ps
CPU time 6.11 seconds
Started Nov 22 03:05:36 PM PST 23
Finished Nov 22 03:05:43 PM PST 23
Peak memory 552348 kb
Host smart-ae21f967-0d27-493e-83c3-d75168ca0191
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86283779164904459112606300998210100017854426807281987769034478727492949297401 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.86283779164904459112606300998210100017854426807281987769034478727492949297401
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all.111065500379966433023981512719133979158276878953307742322657750746936449748596
Short name T1310
Test name
Test status
Simulation time 13992004073 ps
CPU time 548.72 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:14:47 PM PST 23
Peak memory 555932 kb
Host smart-8344255a-e59b-43d9-b63b-7366b7ab60f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111065500379966433023981512719133979158276878953307742322657750746936449748596 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.111065500379966433023981512719133979158276878953307742322657750746936449748596
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.18633851337787781571590842659164256680133859812939778979500468982992990169006
Short name T1883
Test name
Test status
Simulation time 13999524073 ps
CPU time 541.92 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:14:49 PM PST 23
Peak memory 555660 kb
Host smart-58ebba2d-fd6b-4bf5-9a0d-cd4787a86654
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18633851337787781571590842659164256680133859812939778979500468982992990169006 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.18633851337787781571590842659164256680133859812939778979500468982992990169006
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.22037874759791361490503907903468038098366881781331333882163707528639131479486
Short name T269
Test name
Test status
Simulation time 4815189184 ps
CPU time 376.89 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:12:08 PM PST 23
Peak memory 557308 kb
Host smart-17b5d735-d5eb-43a4-a553-c27bd73da345
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037874759791361490503907903468038098366881781331333882163707528639131479486 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.22037874759791361490503907903468038098366881781331333882163707
528639131479486
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.14960022312600375951748868717296372553703331417148369466849665980641247879236
Short name T1766
Test name
Test status
Simulation time 4815189184 ps
CPU time 319.86 seconds
Started Nov 22 03:05:50 PM PST 23
Finished Nov 22 03:11:10 PM PST 23
Peak memory 559708 kb
Host smart-266b0e9a-8c17-48ef-947f-1bcf6e26c41b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960022312600375951748868717296372553703331417148369466849665980641247879236 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.149600223126003759517488687172963725537033314171483694668496
65980641247879236
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.47016743557660126472837563674764845561261509575997521016913011673336278887822
Short name T894
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.42 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:06:32 PM PST 23
Peak memory 553720 kb
Host smart-c1586603-0d0d-4226-8072-a5ed04feaf20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47016743557660126472837563674764845561261509575997521016913011673336278887822 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.47016743557660126472837563674764845561261509575997521016913011673336278887822
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.chip_tl_errors.36083635130443675225995637503385111751010673376332718282430877158587080387200
Short name T55
Test name
Test status
Simulation time 3069924257 ps
CPU time 201.52 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:09:09 PM PST 23
Peak memory 580524 kb
Host smart-f12d31c9-753e-4613-8283-c45c63c3cdff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36083635130443675225995637503385111751010673376332718282430877158587080387200 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.36083635130443675225995637503385111751010673376332718282430877158587080387200
Directory /workspace/28.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device.100309215377795955471048076181569920974399750202427547598079885037358446593597
Short name T323
Test name
Test status
Simulation time 2590995727 ps
CPU time 100.46 seconds
Started Nov 22 03:05:58 PM PST 23
Finished Nov 22 03:07:39 PM PST 23
Peak memory 554600 kb
Host smart-b6228a66-f117-4905-aa3e-b073f381dd2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100309215377795955471048076181569920974399750202427547598079885037358446593597 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.100309215377795955471048076181569920974399750202427547598079885037358446593597
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.9418154724008372216938165733593832294149281287546796753470902658037310448341
Short name T1835
Test name
Test status
Simulation time 115195295727 ps
CPU time 2044.54 seconds
Started Nov 22 03:05:50 PM PST 23
Finished Nov 22 03:39:56 PM PST 23
Peak memory 554780 kb
Host smart-fb942f7f-f33d-4e5a-851c-efe0c3e25f24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9418154724008372216938165733593832294149281287546796753470902658037310448341 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.9418154724008372216938165733593832294149281287546796753470902658037310448341
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.14814762296432420420562083853173619152680868200907722891797727851544099844398
Short name T275
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.94 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:06:38 PM PST 23
Peak memory 553508 kb
Host smart-08a41a57-a25a-4ad0-ad9d-0f2c54d64c33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814762296432420420562083853173619152680868200907722891797727851544099844398 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.14814762296432420420562083853173619152680868200907722891797727851544099844398
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_random.80774888877491237080754290330504217959720504492277752675142411359721493330969
Short name T198
Test name
Test status
Simulation time 2231375727 ps
CPU time 70.27 seconds
Started Nov 22 03:05:57 PM PST 23
Finished Nov 22 03:07:08 PM PST 23
Peak memory 553544 kb
Host smart-c91063b7-6b01-423a-a018-e6e742883cf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80774888877491237080754290330504217959720504492277752675142411359721493330969 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 28.xbar_error_random.80774888877491237080754290330504217959720504492277752675142411359721493330969
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random.35050743562245725941535840896457072517210938928228888210301749637502069253699
Short name T823
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.43 seconds
Started Nov 22 03:05:37 PM PST 23
Finished Nov 22 03:06:53 PM PST 23
Peak memory 553704 kb
Host smart-78274bc0-8630-4988-ba89-6b432b06bd92
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35050743562245725941535840896457072517210938928228888210301749637502069253699 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 28.xbar_random.35050743562245725941535840896457072517210938928228888210301749637502069253699
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2116268760890253983895883991892142823739755487270880519720558468703031437811
Short name T314
Test name
Test status
Simulation time 97702135727 ps
CPU time 1114.39 seconds
Started Nov 22 03:05:57 PM PST 23
Finished Nov 22 03:24:32 PM PST 23
Peak memory 553676 kb
Host smart-d0ab8490-9502-4e5a-a0da-c9b744f1aaf6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116268760890253983895883991892142823739755487270880519720558468703031437811 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2116268760890253983895883991892142823739755487270880519720558468703031437811
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.71540168961642693255152124815519719519239199816387182746282461590425702402442
Short name T629
Test name
Test status
Simulation time 60576345727 ps
CPU time 1043.15 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:23:23 PM PST 23
Peak memory 553688 kb
Host smart-25740af8-4c54-440b-8bd6-30d9a7019208
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71540168961642693255152124815519719519239199816387182746282461590425702402442 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.71540168961642693255152124815519719519239199816387182746282461590425702402442
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.35886951390638675827790759663476322744760814321167283351444185068787878469006
Short name T1344
Test name
Test status
Simulation time 556965727 ps
CPU time 49.65 seconds
Started Nov 22 03:05:58 PM PST 23
Finished Nov 22 03:06:48 PM PST 23
Peak memory 553420 kb
Host smart-724921cb-a8d0-4e19-ab35-9d4e0bf0beea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35886951390638675827790759663476322744760814321167283351444185068787878469006 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.35886951390638675827790759663476322744760814321167283351444185068787878469006
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_same_source.72829457023342317767378976075080629800317808446808764316160201130374453951373
Short name T149
Test name
Test status
Simulation time 2498784073 ps
CPU time 78.32 seconds
Started Nov 22 03:05:49 PM PST 23
Finished Nov 22 03:07:08 PM PST 23
Peak memory 553728 kb
Host smart-a2247c61-2481-4bb6-b2cd-6e8891b354c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72829457023342317767378976075080629800317808446808764316160201130374453951373 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.72829457023342317767378976075080629800317808446808764316160201130374453951373
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke.91529177446418132145089530651147318781808135112696557396285377114230796999313
Short name T395
Test name
Test status
Simulation time 196985727 ps
CPU time 8.56 seconds
Started Nov 22 03:05:57 PM PST 23
Finished Nov 22 03:06:06 PM PST 23
Peak memory 552380 kb
Host smart-b3eb1d40-e50d-4054-8f8a-00b2086f5094
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91529177446418132145089530651147318781808135112696557396285377114230796999313 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 28.xbar_smoke.91529177446418132145089530651147318781808135112696557396285377114230796999313
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.82964757485374145554306778642384800793043362073755517989958462620893598516917
Short name T1385
Test name
Test status
Simulation time 7758585727 ps
CPU time 86.45 seconds
Started Nov 22 03:05:45 PM PST 23
Finished Nov 22 03:07:12 PM PST 23
Peak memory 552356 kb
Host smart-2c0223f7-f13d-4fcd-84ac-160542446807
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82964757485374145554306778642384800793043362073755517989958462620893598516917 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.82964757485374145554306778642384800793043362073755517989958462620893598516917
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.11557242110814128532433472565349903588623677301524837656341792523882186213161
Short name T522
Test name
Test status
Simulation time 4856075727 ps
CPU time 82.79 seconds
Started Nov 22 03:05:57 PM PST 23
Finished Nov 22 03:07:21 PM PST 23
Peak memory 552408 kb
Host smart-a86dc41b-832e-42dc-a787-4218accd09ec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11557242110814128532433472565349903588623677301524837656341792523882186213161 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.11557242110814128532433472565349903588623677301524837656341792523882186213161
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.109790507012041864580103308965535693603683448781456625236874491204675648897072
Short name T138
Test name
Test status
Simulation time 45555727 ps
CPU time 5.85 seconds
Started Nov 22 03:05:50 PM PST 23
Finished Nov 22 03:05:57 PM PST 23
Peak memory 552284 kb
Host smart-54257264-4bd3-4368-afef-baf89edc50af
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109790507012041864580103308965535693603683448781456625236874491204675648897072 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.109790507012041864580103308965535693603683448781456625236874491204675648897072
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all.28110216456563800959618939116639974294672605258178048660787599354750596282183
Short name T605
Test name
Test status
Simulation time 13992004073 ps
CPU time 518.88 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:14:39 PM PST 23
Peak memory 555888 kb
Host smart-ffae5a0e-e86f-4980-9813-8d9c5f305a01
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28110216456563800959618939116639974294672605258178048660787599354750596282183 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.28110216456563800959618939116639974294672605258178048660787599354750596282183
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.90213712482595784377051508360059141430066106107360120479927725507417452087810
Short name T1515
Test name
Test status
Simulation time 13999524073 ps
CPU time 494.87 seconds
Started Nov 22 03:05:59 PM PST 23
Finished Nov 22 03:14:15 PM PST 23
Peak memory 555712 kb
Host smart-6b1cbb1b-7c8c-43d4-bf40-d46b8feedd87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90213712482595784377051508360059141430066106107360120479927725507417452087810 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.90213712482595784377051508360059141430066106107360120479927725507417452087810
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.95263170900112911968545819531358939534421694586351665257878106652246312818849
Short name T321
Test name
Test status
Simulation time 4815189184 ps
CPU time 361.85 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:11:56 PM PST 23
Peak memory 557276 kb
Host smart-7cdafa55-78ef-4f57-b5c1-dfa896e5be3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95263170900112911968545819531358939534421694586351665257878106652246312818849 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.95263170900112911968545819531358939534421694586351665257878106
652246312818849
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.52422048583917353958228292346506855933201402910577239117584380949007005023620
Short name T1479
Test name
Test status
Simulation time 4815189184 ps
CPU time 324.65 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:11:14 PM PST 23
Peak memory 559712 kb
Host smart-53c61b83-4efb-4861-990e-4613ad431306
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52422048583917353958228292346506855933201402910577239117584380949007005023620 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.524220485839173539582282923465068559332014029105772391175843
80949007005023620
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.90843986409107496340533619615323197501621924502224304209886173493346440355602
Short name T1689
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.94 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:06:37 PM PST 23
Peak memory 553764 kb
Host smart-f41636a3-d68e-460d-a6a2-9424f7b99d27
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90843986409107496340533619615323197501621924502224304209886173493346440355602 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.90843986409107496340533619615323197501621924502224304209886173493346440355602
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.chip_tl_errors.81207207444331417119647828254025598268452271936896190475422583925003721607518
Short name T1071
Test name
Test status
Simulation time 3069924257 ps
CPU time 174.34 seconds
Started Nov 22 03:05:48 PM PST 23
Finished Nov 22 03:08:43 PM PST 23
Peak memory 580508 kb
Host smart-45279d30-edf9-4d86-9cd8-aebeb5dd2729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81207207444331417119647828254025598268452271936896190475422583925003721607518 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.81207207444331417119647828254025598268452271936896190475422583925003721607518
Directory /workspace/29.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device.35122267997967608547989784484637075393330486414728936161497518912315596754810
Short name T834
Test name
Test status
Simulation time 2590995727 ps
CPU time 103.5 seconds
Started Nov 22 03:05:40 PM PST 23
Finished Nov 22 03:07:24 PM PST 23
Peak memory 554744 kb
Host smart-2a774ce7-c504-45fb-a7f7-c619c80d3c1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35122267997967608547989784484637075393330486414728936161497518912315596754810 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.35122267997967608547989784484637075393330486414728936161497518912315596754810
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.48984259220576799365207481157248772863507612691889534763678562690615276961087
Short name T1920
Test name
Test status
Simulation time 115195295727 ps
CPU time 2015.47 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:39:24 PM PST 23
Peak memory 554792 kb
Host smart-162db911-9659-4074-8542-635c25b6a059
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48984259220576799365207481157248772863507612691889534763678562690615276961087 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.48984259220576799365207481157248772863507612691889534763678562690615276961087
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.34194823998737606075581502667880549457387382112224471924772639404882095792879
Short name T497
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.98 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:06:36 PM PST 23
Peak memory 553544 kb
Host smart-c7d10132-93c3-4d3a-9e32-86f6b3e63447
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34194823998737606075581502667880549457387382112224471924772639404882095792879 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.34194823998737606075581502667880549457387382112224471924772639404882095792879
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_random.67404201084079608177632397328354802336776229913669430633534297066785350245240
Short name T641
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.05 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:02 PM PST 23
Peak memory 553516 kb
Host smart-4937fb2a-00f6-46bd-95da-81357ffdb55b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67404201084079608177632397328354802336776229913669430633534297066785350245240 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 29.xbar_error_random.67404201084079608177632397328354802336776229913669430633534297066785350245240
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random.8898922453998570286355752337380577218759113484623893663912290823049121989291
Short name T1701
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.13 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 553748 kb
Host smart-ac97f80e-6fcd-461d-9722-97807c4ce6ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8898922453998570286355752337380577218759113484623893663912290823049121989291 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 29.xbar_random.8898922453998570286355752337380577218759113484623893663912290823049121989291
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.61990083345922328201809341765553106435162867599612076790766652809566472994372
Short name T954
Test name
Test status
Simulation time 97702135727 ps
CPU time 1170.88 seconds
Started Nov 22 03:05:50 PM PST 23
Finished Nov 22 03:25:21 PM PST 23
Peak memory 553660 kb
Host smart-067afa5f-36b5-4572-b1e6-24fbb60d1b25
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61990083345922328201809341765553106435162867599612076790766652809566472994372 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.61990083345922328201809341765553106435162867599612076790766652809566472994372
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.107729591675053697681931631901233087638651572064793720295153701268412682276409
Short name T490
Test name
Test status
Simulation time 60576345727 ps
CPU time 1132.24 seconds
Started Nov 22 03:05:41 PM PST 23
Finished Nov 22 03:24:34 PM PST 23
Peak memory 553688 kb
Host smart-b0398e67-5196-42d3-bfcc-93021957bb6c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107729591675053697681931631901233087638651572064793720295153701268412682276409 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.107729591675053697681931631901233087638651572064793720295153701268412682276409
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.60716077703699365368520265579080053725670579248124723807359900346821081194785
Short name T704
Test name
Test status
Simulation time 556965727 ps
CPU time 44.65 seconds
Started Nov 22 03:05:42 PM PST 23
Finished Nov 22 03:06:27 PM PST 23
Peak memory 553588 kb
Host smart-a9da0385-1149-44ea-863f-0b7de1dcac0e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60716077703699365368520265579080053725670579248124723807359900346821081194785 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.60716077703699365368520265579080053725670579248124723807359900346821081194785
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_same_source.4709883812628951052841082390077091887332686133309159242765106360619932271463
Short name T1554
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.88 seconds
Started Nov 22 03:05:40 PM PST 23
Finished Nov 22 03:06:57 PM PST 23
Peak memory 553676 kb
Host smart-78442db6-f381-44c8-b31d-6f2168cbd809
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4709883812628951052841082390077091887332686133309159242765106360619932271463 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4709883812628951052841082390077091887332686133309159242765106360619932271463
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke.47166468021305999685729661208448640400013525232090267159160399944526767117658
Short name T898
Test name
Test status
Simulation time 196985727 ps
CPU time 8.21 seconds
Started Nov 22 03:05:49 PM PST 23
Finished Nov 22 03:05:57 PM PST 23
Peak memory 552364 kb
Host smart-b1c6b6b6-c629-49f7-afa8-491668d8158a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47166468021305999685729661208448640400013525232090267159160399944526767117658 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 29.xbar_smoke.47166468021305999685729661208448640400013525232090267159160399944526767117658
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.34674458685745398974984530890460870289387339385177029441781419148645753160840
Short name T640
Test name
Test status
Simulation time 7758585727 ps
CPU time 86.43 seconds
Started Nov 22 03:05:58 PM PST 23
Finished Nov 22 03:07:25 PM PST 23
Peak memory 552392 kb
Host smart-c693a6f5-c7a8-418a-9201-0af09cbfc837
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674458685745398974984530890460870289387339385177029441781419148645753160840 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.34674458685745398974984530890460870289387339385177029441781419148645753160840
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.89683041827545974920760271323859286516686979831299840901052332756970409224618
Short name T324
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.36 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:07:09 PM PST 23
Peak memory 552372 kb
Host smart-445eabc4-3b64-43e1-b97f-551304b2d54a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89683041827545974920760271323859286516686979831299840901052332756970409224618 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.89683041827545974920760271323859286516686979831299840901052332756970409224618
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.72040361944242719754726379911509260570019439007041971289073698552584452744560
Short name T736
Test name
Test status
Simulation time 45555727 ps
CPU time 5.84 seconds
Started Nov 22 03:05:38 PM PST 23
Finished Nov 22 03:05:45 PM PST 23
Peak memory 552300 kb
Host smart-000c210f-7f65-49d4-b03f-04555d4397e6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72040361944242719754726379911509260570019439007041971289073698552584452744560 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.72040361944242719754726379911509260570019439007041971289073698552584452744560
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all.98881645548430835517886652988091603564312762323963306476864764008106178483370
Short name T1032
Test name
Test status
Simulation time 13992004073 ps
CPU time 511.33 seconds
Started Nov 22 03:05:51 PM PST 23
Finished Nov 22 03:14:23 PM PST 23
Peak memory 555928 kb
Host smart-73c6f682-8fcb-41bf-94a9-b52dadff287d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98881645548430835517886652988091603564312762323963306476864764008106178483370 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.98881645548430835517886652988091603564312762323963306476864764008106178483370
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.55491645040538854975488243901499014722981369483435711382563267357504917062673
Short name T1338
Test name
Test status
Simulation time 13999524073 ps
CPU time 534.33 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:14:51 PM PST 23
Peak memory 555752 kb
Host smart-3830203c-8b47-4d19-b312-19aa63daed23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55491645040538854975488243901499014722981369483435711382563267357504917062673 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.55491645040538854975488243901499014722981369483435711382563267357504917062673
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.95932208039034063308909061129730562779195561291749452638659564070163194456876
Short name T1084
Test name
Test status
Simulation time 4815189184 ps
CPU time 346.54 seconds
Started Nov 22 03:05:43 PM PST 23
Finished Nov 22 03:11:30 PM PST 23
Peak memory 557256 kb
Host smart-8cf849bb-ec17-473d-8a30-c6868d55d49c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95932208039034063308909061129730562779195561291749452638659564070163194456876 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.95932208039034063308909061129730562779195561291749452638659564
070163194456876
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.21084466189645809421035428262092854548625680646204643251255367089674267403136
Short name T1003
Test name
Test status
Simulation time 4815189184 ps
CPU time 309.75 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:11:06 PM PST 23
Peak memory 559744 kb
Host smart-b97562bc-83b9-45ec-b6ee-5a9d4d7cf9f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21084466189645809421035428262092854548625680646204643251255367089674267403136 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.210844661896458094210354282620928545486256806462046432512553
67089674267403136
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.55173289480967511577820179034576519311941390578116929375116700966549351046529
Short name T878
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.64 seconds
Started Nov 22 03:05:46 PM PST 23
Finished Nov 22 03:06:38 PM PST 23
Peak memory 553724 kb
Host smart-b49cbec5-0082-4365-b992-54c346d4028e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55173289480967511577820179034576519311941390578116929375116700966549351046529 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.55173289480967511577820179034576519311941390578116929375116700966549351046529
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.24210315891335126769158062272937697869656934150918061448767130919091028073788
Short name T48
Test name
Test status
Simulation time 72959944675 ps
CPU time 9909.63 seconds
Started Nov 22 03:03:28 PM PST 23
Finished Nov 22 05:48:39 PM PST 23
Peak memory 625312 kb
Host smart-1ac2daa5-d795-4055-a8e2-40a79dca08a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421031589133512676915806227293769786965693415091
8061448767130919091028073788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_aliasing.242103158913351267691580622729376978696569341
50918061448767130919091028073788
Directory /workspace/3.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.36811827461333637582828661625182212517561776853673887568615460053577966251001
Short name T22
Test name
Test status
Simulation time 7954924257 ps
CPU time 771.24 seconds
Started Nov 22 03:03:08 PM PST 23
Finished Nov 22 03:16:01 PM PST 23
Peak memory 580540 kb
Host smart-64884250-9d15-4f1f-86c6-9de98ad0df8b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368118274613336375828286616251
82212517561776853673887568615460053577966251001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.36811827461333637582828661
625182212517561776853673887568615460053577966251001
Directory /workspace/3.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.15896968426889996484204638255434002189931697646476896932943257848190167859469
Short name T872
Test name
Test status
Simulation time 7234930891 ps
CPU time 343.83 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:09:25 PM PST 23
Peak memory 622528 kb
Host smart-5de57d34-f004-470c-91bd-6f39c523945c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589696842688999648420463825543
4002189931697646476896932943257848190167859469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.1589696842688
9996484204638255434002189931697646476896932943257848190167859469
Directory /workspace/3.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_rw.91138506722066961033193530054393357661259153647366957521620771079681520644380
Short name T1402
Test name
Test status
Simulation time 5924944675 ps
CPU time 600.85 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 03:13:35 PM PST 23
Peak memory 580528 kb
Host smart-ae94b75e-80ef-480c-993a-493fe867947e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91138506722066961033193530054393357661259153647366957521620771079681520644380 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.91138506722066961033193530054393357661259153647366957521620771079681520644380
Directory /workspace/3.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.85192784835131942305269209360010252341939777681093089781324937611419538411223
Short name T1755
Test name
Test status
Simulation time 30604932618 ps
CPU time 3066.32 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:54:51 PM PST 23
Peak memory 580520 kb
Host smart-68507416-664b-49f1-b0cc-fc3626066d46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8519278483513194230526920936001025234
1939777681093089781324937611419538411223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.8519278483513194230526920
9360010252341939777681093089781324937611419538411223
Directory /workspace/3.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.chip_tl_errors.78304913536953359952669046840394687827733040492485334612065868317702945711687
Short name T1825
Test name
Test status
Simulation time 3069924257 ps
CPU time 205.63 seconds
Started Nov 22 03:03:48 PM PST 23
Finished Nov 22 03:07:15 PM PST 23
Peak memory 580520 kb
Host smart-93f7a475-12f6-4225-a787-7cf8f06f1903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78304913536953359952669046840394687827733040492485334612065868317702945711687 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.78304913536953359952669046840394687827733040492485334612065868317702945711687
Directory /workspace/3.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device.19065836686336723067950029164618900181056346538592040985421060942103159076627
Short name T234
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.11 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:05:18 PM PST 23
Peak memory 554800 kb
Host smart-519ec53a-329a-4bbe-95ec-ece394f6e825
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19065836686336723067950029164618900181056346538592040985421060942103159076627 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.19065836686336723067950029164618900181056346538592040985421060942103159076627
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.86239777577655109701203915472951124882533987183341571678733225541064669966358
Short name T1831
Test name
Test status
Simulation time 115195295727 ps
CPU time 1848.1 seconds
Started Nov 22 03:03:39 PM PST 23
Finished Nov 22 03:34:27 PM PST 23
Peak memory 554796 kb
Host smart-01ea27c4-838a-4950-91fd-9631f1f11448
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86239777577655109701203915472951124882533987183341571678733225541064669966358 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.86239777577655109701203915472951124882533987183341571678733225541064669966358
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.40789168242748923197228558694341048232315101117415172322347880066118239123996
Short name T1499
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.87 seconds
Started Nov 22 03:03:11 PM PST 23
Finished Nov 22 03:03:58 PM PST 23
Peak memory 553488 kb
Host smart-283d2745-3f0c-4d90-b3fc-d2cab49c4b1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40789168242748923197228558694341048232315101117415172322347880066118239123996 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.40789168242748923197228558694341048232315101117415172322347880066118239123996
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_random.3000530388714861704791896600856303828693859572737150812150428397480846900766
Short name T1729
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.55 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:04:51 PM PST 23
Peak memory 553344 kb
Host smart-4e43850c-f545-49ba-9ce1-a2f75133a75d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000530388714861704791896600856303828693859572737150812150428397480846900766 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.xbar_error_random.3000530388714861704791896600856303828693859572737150812150428397480846900766
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random.36197676582999698809700217950598947650127756529305211179089942116234940664833
Short name T1363
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.2 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:04:54 PM PST 23
Peak memory 553560 kb
Host smart-d2f1ef6a-62ad-42af-b0c3-5cab4503a2c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197676582999698809700217950598947650127756529305211179089942116234940664833 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.xbar_random.36197676582999698809700217950598947650127756529305211179089942116234940664833
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.25899934704183951216396871377929419109386575143644724233339057100951148935860
Short name T1695
Test name
Test status
Simulation time 97702135727 ps
CPU time 1125.25 seconds
Started Nov 22 03:03:27 PM PST 23
Finished Nov 22 03:22:13 PM PST 23
Peak memory 553624 kb
Host smart-c2bf0e7d-8cd7-4b43-b144-3122a11b4bd2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899934704183951216396871377929419109386575143644724233339057100951148935860 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.25899934704183951216396871377929419109386575143644724233339057100951148935860
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.82225752269106502262836942459481831843856167577681917725982056261373253173343
Short name T1449
Test name
Test status
Simulation time 60576345727 ps
CPU time 1021.72 seconds
Started Nov 22 03:03:31 PM PST 23
Finished Nov 22 03:20:34 PM PST 23
Peak memory 553692 kb
Host smart-28f5e53a-5a23-417c-a266-a30b24455a61
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82225752269106502262836942459481831843856167577681917725982056261373253173343 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.82225752269106502262836942459481831843856167577681917725982056261373253173343
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.53440872550143852663407045244020017583289864853607601335050053575777700860321
Short name T1315
Test name
Test status
Simulation time 556965727 ps
CPU time 44.58 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:04:26 PM PST 23
Peak memory 553760 kb
Host smart-048c6fab-8984-4fb1-9d38-b8c393e27fff
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53440872550143852663407045244020017583289864853607601335050053575777700860321 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.53440872550143852663407045244020017583289864853607601335050053575777700860321
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_same_source.62614083553261160842969905489115303330187050529052872430148354350954629719025
Short name T256
Test name
Test status
Simulation time 2498784073 ps
CPU time 70.17 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 03:04:44 PM PST 23
Peak memory 553784 kb
Host smart-00aced9b-6363-49c1-aa78-fd036e5075e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62614083553261160842969905489115303330187050529052872430148354350954629719025 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.62614083553261160842969905489115303330187050529052872430148354350954629719025
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke.23602743991619006520886131314999903295947137860246334493403049735662775632606
Short name T521
Test name
Test status
Simulation time 196985727 ps
CPU time 7.95 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:03:43 PM PST 23
Peak memory 552372 kb
Host smart-87760598-369d-4610-9126-7723e4eb43d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602743991619006520886131314999903295947137860246334493403049735662775632606 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.xbar_smoke.23602743991619006520886131314999903295947137860246334493403049735662775632606
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.97568477832697799305077105108184168966184773698580862455479863702295582137668
Short name T1132
Test name
Test status
Simulation time 7758585727 ps
CPU time 87.37 seconds
Started Nov 22 03:03:54 PM PST 23
Finished Nov 22 03:05:22 PM PST 23
Peak memory 552412 kb
Host smart-a4ce8b4a-9e28-498d-a07b-bffb6d2036d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97568477832697799305077105108184168966184773698580862455479863702295582137668 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.97568477832697799305077105108184168966184773698580862455479863702295582137668
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.70631332495050676373773969249831717012067288045452359471941824093501945775980
Short name T190
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.24 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:04:56 PM PST 23
Peak memory 552384 kb
Host smart-f21ffdb8-5acf-46f8-8ea0-6d2cfbc9904b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70631332495050676373773969249831717012067288045452359471941824093501945775980 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.70631332495050676373773969249831717012067288045452359471941824093501945775980
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.103529877366374240787207898039825778317611878091855998112678449526865519243199
Short name T377
Test name
Test status
Simulation time 45555727 ps
CPU time 5.62 seconds
Started Nov 22 03:03:27 PM PST 23
Finished Nov 22 03:03:33 PM PST 23
Peak memory 552360 kb
Host smart-50aa86f6-b55e-43d1-ac49-f67bd69eb3f4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103529877366374240787207898039825778317611878091855998112678449526865519243199 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.103529877366374240787207898039825778317611878091855998112678449526865519243199
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all.12833674222172809602403915176699051232765613411960578998004443852119103901859
Short name T1060
Test name
Test status
Simulation time 13992004073 ps
CPU time 488.39 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:11:43 PM PST 23
Peak memory 555916 kb
Host smart-3c692a3c-6596-42f6-8050-e99443e5c6cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833674222172809602403915176699051232765613411960578998004443852119103901859 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.12833674222172809602403915176699051232765613411960578998004443852119103901859
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.51874208990563939580578020115435350632837910252567720025838741906167981183156
Short name T1102
Test name
Test status
Simulation time 13999524073 ps
CPU time 513.08 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:12:06 PM PST 23
Peak memory 555736 kb
Host smart-160a27e5-9fdb-40d9-91c0-0456ba7f2de7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51874208990563939580578020115435350632837910252567720025838741906167981183156 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.51874208990563939580578020115435350632837910252567720025838741906167981183156
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.71385080561088501191694052979732682599071824817461117408935077773878030395257
Short name T351
Test name
Test status
Simulation time 4815189184 ps
CPU time 385.29 seconds
Started Nov 22 03:03:07 PM PST 23
Finished Nov 22 03:09:36 PM PST 23
Peak memory 557164 kb
Host smart-c502c4fa-56c5-422b-a1bc-b5b865dbf93f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71385080561088501191694052979732682599071824817461117408935077773878030395257 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.713850805610885011916940529797326825990718248174611174089350777
73878030395257
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.85298573949838897747283050643130758002806114785916346427937521372421004147374
Short name T621
Test name
Test status
Simulation time 4815189184 ps
CPU time 299.53 seconds
Started Nov 22 03:03:31 PM PST 23
Finished Nov 22 03:08:31 PM PST 23
Peak memory 559584 kb
Host smart-17e663b6-309c-4c8b-938f-e046582047e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85298573949838897747283050643130758002806114785916346427937521372421004147374 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.8529857394983889774728305064313075800280611478591634642793752
1372421004147374
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.90721207795669062443903493466181008299040511262418956925742438181346627853390
Short name T1425
Test name
Test status
Simulation time 1176995727 ps
CPU time 40.86 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:04:23 PM PST 23
Peak memory 553720 kb
Host smart-8742bb0e-1976-4ef3-94cb-fa5836dba967
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90721207795669062443903493466181008299040511262418956925742438181346627853390 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.90721207795669062443903493466181008299040511262418956925742438181346627853390
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device.109823828768647558183382825281239876210260904567943960881490736024605390478127
Short name T1297
Test name
Test status
Simulation time 2590995727 ps
CPU time 112.06 seconds
Started Nov 22 03:05:49 PM PST 23
Finished Nov 22 03:07:42 PM PST 23
Peak memory 554808 kb
Host smart-cc909ba1-8f6a-48af-8829-5e1656ee55d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109823828768647558183382825281239876210260904567943960881490736024605390478127 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.109823828768647558183382825281239876210260904567943960881490736024605390478127
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.37643325369579724208009712744045538528724117577390074306801403707464321884914
Short name T944
Test name
Test status
Simulation time 115195295727 ps
CPU time 2062.33 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:40:11 PM PST 23
Peak memory 554852 kb
Host smart-d3bdf342-2d76-42aa-a4aa-b900ff432fcb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37643325369579724208009712744045538528724117577390074306801403707464321884914 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.37643325369579724208009712744045538528724117577390074306801403707464321884914
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.99013266948858444520438598304544506575780055285468719071994946459598676151768
Short name T1644
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.63 seconds
Started Nov 22 03:05:53 PM PST 23
Finished Nov 22 03:06:37 PM PST 23
Peak memory 553500 kb
Host smart-58415303-3904-4afb-aab5-4fcae5f72980
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99013266948858444520438598304544506575780055285468719071994946459598676151768 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.99013266948858444520438598304544506575780055285468719071994946459598676151768
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_random.10156889458607579104876895955057009553529261126917348619832031337960534878215
Short name T288
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.88 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:07:12 PM PST 23
Peak memory 553520 kb
Host smart-d8993703-b908-4daf-8c52-e728621d8f7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10156889458607579104876895955057009553529261126917348619832031337960534878215 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 30.xbar_error_random.10156889458607579104876895955057009553529261126917348619832031337960534878215
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random.75607924840605681376500325048711042435256813166397345545793764014662215039934
Short name T404
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.87 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:07:14 PM PST 23
Peak memory 553784 kb
Host smart-3258faa3-6288-47f2-ac80-1f87f114d9f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75607924840605681376500325048711042435256813166397345545793764014662215039934 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 30.xbar_random.75607924840605681376500325048711042435256813166397345545793764014662215039934
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.67137889032470458433786867715566101778249077777735359901681261948709240945313
Short name T398
Test name
Test status
Simulation time 97702135727 ps
CPU time 1145.99 seconds
Started Nov 22 03:05:49 PM PST 23
Finished Nov 22 03:24:55 PM PST 23
Peak memory 553712 kb
Host smart-65138915-3ffe-4ed7-b51c-acedd62c30bf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67137889032470458433786867715566101778249077777735359901681261948709240945313 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.67137889032470458433786867715566101778249077777735359901681261948709240945313
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.105489796827101365970207496717735677447427045102366455660864164247450620377974
Short name T1348
Test name
Test status
Simulation time 60576345727 ps
CPU time 1054.67 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:23:23 PM PST 23
Peak memory 553708 kb
Host smart-891fc2b3-2684-48f3-869e-0c4f241ad079
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105489796827101365970207496717735677447427045102366455660864164247450620377974 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.105489796827101365970207496717735677447427045102366455660864164247450620377974
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.63496400222761341792348990201762243219664244874466196725460245606112434461890
Short name T1803
Test name
Test status
Simulation time 556965727 ps
CPU time 47.42 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:06:35 PM PST 23
Peak memory 553660 kb
Host smart-b856eece-068e-4bd7-9f73-8b9713e53f33
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63496400222761341792348990201762243219664244874466196725460245606112434461890 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.63496400222761341792348990201762243219664244874466196725460245606112434461890
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_same_source.34746469852633596321324142783079718685631381925232459883370496798343837451707
Short name T855
Test name
Test status
Simulation time 2498784073 ps
CPU time 77.18 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:07:13 PM PST 23
Peak memory 553712 kb
Host smart-573eda4c-0f8e-4803-9650-81ada46fcb97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34746469852633596321324142783079718685631381925232459883370496798343837451707 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.34746469852633596321324142783079718685631381925232459883370496798343837451707
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke.81085372819484960655251979273189920244227844811878634184828230790998232553570
Short name T1894
Test name
Test status
Simulation time 196985727 ps
CPU time 8.33 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:06:04 PM PST 23
Peak memory 552396 kb
Host smart-f35dfe33-229f-49ef-aba4-9bec0f8ee6b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81085372819484960655251979273189920244227844811878634184828230790998232553570 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 30.xbar_smoke.81085372819484960655251979273189920244227844811878634184828230790998232553570
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.81998671304750658250712133433418220859532735052008188360507249683780590872168
Short name T1797
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.28 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:07:27 PM PST 23
Peak memory 552408 kb
Host smart-0864a0cd-7c60-4445-b92f-7fa48efbc455
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81998671304750658250712133433418220859532735052008188360507249683780590872168 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.81998671304750658250712133433418220859532735052008188360507249683780590872168
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.89515177754175536679039402896892024573280406858705474710527486748537963040785
Short name T1359
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.89 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:07:13 PM PST 23
Peak memory 552372 kb
Host smart-9bb43dbc-fea1-4e2d-8389-aba484dbba0d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89515177754175536679039402896892024573280406858705474710527486748537963040785 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.89515177754175536679039402896892024573280406858705474710527486748537963040785
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.62880029634808587983638476100582414667913224392435953842155037276250500595930
Short name T145
Test name
Test status
Simulation time 45555727 ps
CPU time 6.3 seconds
Started Nov 22 03:05:44 PM PST 23
Finished Nov 22 03:05:50 PM PST 23
Peak memory 552368 kb
Host smart-c5ceaacc-de6b-4be9-9f91-3d4df9adbf5c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62880029634808587983638476100582414667913224392435953842155037276250500595930 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.62880029634808587983638476100582414667913224392435953842155037276250500595930
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all.26715333494992232398309229132704484285229755078069898856843909824949953326692
Short name T929
Test name
Test status
Simulation time 13992004073 ps
CPU time 460.61 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:13:29 PM PST 23
Peak memory 555916 kb
Host smart-56282d98-0f67-493c-8a16-53065e1f41b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26715333494992232398309229132704484285229755078069898856843909824949953326692 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.26715333494992232398309229132704484285229755078069898856843909824949953326692
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.75707684005787792554778103192166196588607903190830407504553585930991654980773
Short name T1681
Test name
Test status
Simulation time 13999524073 ps
CPU time 521.69 seconds
Started Nov 22 03:05:47 PM PST 23
Finished Nov 22 03:14:29 PM PST 23
Peak memory 555728 kb
Host smart-7755b36a-7f4a-448f-bf7b-fc2cc4732b1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75707684005787792554778103192166196588607903190830407504553585930991654980773 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.75707684005787792554778103192166196588607903190830407504553585930991654980773
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.17095304192878839743030664143789548324554585178986510048468795725887425251503
Short name T1847
Test name
Test status
Simulation time 4815189184 ps
CPU time 374.34 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:12:11 PM PST 23
Peak memory 557232 kb
Host smart-d2579bc9-71b7-4566-992f-aca188f5ce5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095304192878839743030664143789548324554585178986510048468795725887425251503 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.17095304192878839743030664143789548324554585178986510048468795
725887425251503
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.30537793160507867029025679098674515721430976185492812058211995438440222730083
Short name T1142
Test name
Test status
Simulation time 4815189184 ps
CPU time 325.42 seconds
Started Nov 22 03:05:57 PM PST 23
Finished Nov 22 03:11:23 PM PST 23
Peak memory 559800 kb
Host smart-4394e766-0624-4c1c-9004-3ef2f88e8173
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30537793160507867029025679098674515721430976185492812058211995438440222730083 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.305377931605078670290256790986745157214309761854928120582119
95438440222730083
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.115564506654227346411479218615541839326520729145199363463061556579696558604642
Short name T1018
Test name
Test status
Simulation time 1176995727 ps
CPU time 44.27 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:06:40 PM PST 23
Peak memory 553696 kb
Host smart-a323083c-307d-4717-b615-19bffde36222
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115564506654227346411479218615541839326520729145199363463061556579696558604642 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.115564506654227346411479218615541839326520729145199363463061556579696558604642
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device.8340236621156431552020337841729459558587596078602599773128916523137510904006
Short name T841
Test name
Test status
Simulation time 2590995727 ps
CPU time 100.46 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:07:36 PM PST 23
Peak memory 554804 kb
Host smart-202490f6-ce84-464a-8612-03306daf534e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8340236621156431552020337841729459558587596078602599773128916523137510904006 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.8340236621156431552020337841729459558587596078602599773128916523137510904006
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.11009879242172594153285545843898973128347621658732984583432269207179732810938
Short name T537
Test name
Test status
Simulation time 115195295727 ps
CPU time 2083.81 seconds
Started Nov 22 03:06:13 PM PST 23
Finished Nov 22 03:40:58 PM PST 23
Peak memory 554600 kb
Host smart-ea30c014-fd77-4950-9021-d0de4887130f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009879242172594153285545843898973128347621658732984583432269207179732810938 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.11009879242172594153285545843898973128347621658732984583432269207179732810938
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.42756794715691143712429110900187430356515829175243426009567272187769947630208
Short name T1528
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.98 seconds
Started Nov 22 03:06:03 PM PST 23
Finished Nov 22 03:06:49 PM PST 23
Peak memory 553472 kb
Host smart-0d4fd8ae-97db-4bae-ab66-52be9289e333
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42756794715691143712429110900187430356515829175243426009567272187769947630208 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.42756794715691143712429110900187430356515829175243426009567272187769947630208
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_random.92549143921699482229740088492193833601482665555544466573365332028040659248878
Short name T1283
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.65 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:07:10 PM PST 23
Peak memory 553472 kb
Host smart-d80548c6-7c81-4d23-a340-c9f772c5ba8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92549143921699482229740088492193833601482665555544466573365332028040659248878 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 31.xbar_error_random.92549143921699482229740088492193833601482665555544466573365332028040659248878
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random.25483847309411211394662888167910779078114904941393132473416326487264387488072
Short name T1244
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.49 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:07:15 PM PST 23
Peak memory 553792 kb
Host smart-8ca19655-ccbf-4b7c-b748-525f0ba1e484
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25483847309411211394662888167910779078114904941393132473416326487264387488072 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 31.xbar_random.25483847309411211394662888167910779078114904941393132473416326487264387488072
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.108016929642492130297089459907457324357912990188903801950585357307225050455239
Short name T290
Test name
Test status
Simulation time 97702135727 ps
CPU time 1194.09 seconds
Started Nov 22 03:06:13 PM PST 23
Finished Nov 22 03:26:08 PM PST 23
Peak memory 553488 kb
Host smart-7e5bb5de-b5fd-4661-bf32-56be247b842f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108016929642492130297089459907457324357912990188903801950585357307225050455239 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.108016929642492130297089459907457324357912990188903801950585357307225050455239
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.34906427407911672865887646223206959817796273835028085808389931200269907869658
Short name T1589
Test name
Test status
Simulation time 60576345727 ps
CPU time 1048.05 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:23:23 PM PST 23
Peak memory 553632 kb
Host smart-7aa4c917-ad33-480e-bb7a-da221b07771f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34906427407911672865887646223206959817796273835028085808389931200269907869658 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.34906427407911672865887646223206959817796273835028085808389931200269907869658
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.104231732284626768666912885933729314875012847124498113055384986125984162185492
Short name T1560
Test name
Test status
Simulation time 556965727 ps
CPU time 43.89 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:06:38 PM PST 23
Peak memory 553704 kb
Host smart-68881581-be2a-4760-a715-147cf41f59a2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104231732284626768666912885933729314875012847124498113055384986125984162185492 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.104231732284626768666912885933729314875012847124498113055384986125984162185492
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_same_source.63867805730234103983405285467965960205189541063612071073913961010628453246049
Short name T765
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.78 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:07:10 PM PST 23
Peak memory 553756 kb
Host smart-fd4f2231-e9c4-4804-a7e1-4ffd12c0de84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63867805730234103983405285467965960205189541063612071073913961010628453246049 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.63867805730234103983405285467965960205189541063612071073913961010628453246049
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke.61979152733658914311823340245625689455849347064598764755718436660485962658126
Short name T1177
Test name
Test status
Simulation time 196985727 ps
CPU time 8.46 seconds
Started Nov 22 03:06:02 PM PST 23
Finished Nov 22 03:06:12 PM PST 23
Peak memory 552356 kb
Host smart-be31f463-6dc4-44be-bd52-1e0fde26b002
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61979152733658914311823340245625689455849347064598764755718436660485962658126 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 31.xbar_smoke.61979152733658914311823340245625689455849347064598764755718436660485962658126
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.110550171603414078841781117786804756576797493424306739467325544565691422985589
Short name T646
Test name
Test status
Simulation time 7758585727 ps
CPU time 93.72 seconds
Started Nov 22 03:06:13 PM PST 23
Finished Nov 22 03:07:48 PM PST 23
Peak memory 552192 kb
Host smart-7999cec7-067b-4867-bb5d-1372d4de8ef9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110550171603414078841781117786804756576797493424306739467325544565691422985589 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.110550171603414078841781117786804756576797493424306739467325544565691422985589
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.48789525966360175602933164598063463949693186541670568078884224865906151727033
Short name T1770
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.44 seconds
Started Nov 22 03:05:56 PM PST 23
Finished Nov 22 03:07:27 PM PST 23
Peak memory 552332 kb
Host smart-471bc294-7af6-4666-a8bd-9d6b96da62a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48789525966360175602933164598063463949693186541670568078884224865906151727033 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.48789525966360175602933164598063463949693186541670568078884224865906151727033
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.94316078207677347886026877407334448881531296426711673464496398709137803497052
Short name T809
Test name
Test status
Simulation time 45555727 ps
CPU time 5.97 seconds
Started Nov 22 03:06:04 PM PST 23
Finished Nov 22 03:06:15 PM PST 23
Peak memory 552420 kb
Host smart-baadc1ed-4d68-4752-a024-937bd306c9f2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94316078207677347886026877407334448881531296426711673464496398709137803497052 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.94316078207677347886026877407334448881531296426711673464496398709137803497052
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all.102765174306539459556126514060733169661141578939414127701972390705694437535087
Short name T1170
Test name
Test status
Simulation time 13992004073 ps
CPU time 536.76 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:14:53 PM PST 23
Peak memory 555888 kb
Host smart-d8c2ab2e-4161-4de0-914c-1fbd76cf9786
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102765174306539459556126514060733169661141578939414127701972390705694437535087 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.102765174306539459556126514060733169661141578939414127701972390705694437535087
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.93203293361171750166128450890945467010715617140358791248125768759532664717788
Short name T430
Test name
Test status
Simulation time 13999524073 ps
CPU time 542.34 seconds
Started Nov 22 03:06:13 PM PST 23
Finished Nov 22 03:15:16 PM PST 23
Peak memory 555548 kb
Host smart-eef1fb53-6992-4422-b478-8077834305c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93203293361171750166128450890945467010715617140358791248125768759532664717788 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.93203293361171750166128450890945467010715617140358791248125768759532664717788
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.84253438814460937654397108470506126918220625834603427923924914892062080032808
Short name T1896
Test name
Test status
Simulation time 4815189184 ps
CPU time 400.33 seconds
Started Nov 22 03:06:14 PM PST 23
Finished Nov 22 03:12:55 PM PST 23
Peak memory 557072 kb
Host smart-b45968ad-170c-4593-a42c-c021801e0a4b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84253438814460937654397108470506126918220625834603427923924914892062080032808 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.84253438814460937654397108470506126918220625834603427923924914
892062080032808
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.77005499167947255952673282305362780214144450750817167323613681652528483137601
Short name T1566
Test name
Test status
Simulation time 4815189184 ps
CPU time 321 seconds
Started Nov 22 03:06:03 PM PST 23
Finished Nov 22 03:11:28 PM PST 23
Peak memory 559696 kb
Host smart-0cdc5e28-0b18-49f2-9f5b-64cb84624d17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77005499167947255952673282305362780214144450750817167323613681652528483137601 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.770054991679472559526732823053627802141444507508171673236136
81652528483137601
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.60722707541244226773354863154488513657618253114882573810057338509613290072062
Short name T393
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.86 seconds
Started Nov 22 03:05:54 PM PST 23
Finished Nov 22 03:06:43 PM PST 23
Peak memory 553544 kb
Host smart-62131961-7328-4e36-8139-7667b68b8358
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60722707541244226773354863154488513657618253114882573810057338509613290072062 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.60722707541244226773354863154488513657618253114882573810057338509613290072062
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device.103779314961795353535191739375310936083971775831132776731911451525640595708090
Short name T1492
Test name
Test status
Simulation time 2590995727 ps
CPU time 120.81 seconds
Started Nov 22 03:06:19 PM PST 23
Finished Nov 22 03:08:20 PM PST 23
Peak memory 554800 kb
Host smart-7d6b8cce-8d6a-4d4a-819f-ea1cecdad486
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103779314961795353535191739375310936083971775831132776731911451525640595708090 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.103779314961795353535191739375310936083971775831132776731911451525640595708090
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.8547755078987027874431769475095602608996181688090848965615041375079773602070
Short name T387
Test name
Test status
Simulation time 115195295727 ps
CPU time 1914.69 seconds
Started Nov 22 03:06:05 PM PST 23
Finished Nov 22 03:38:04 PM PST 23
Peak memory 554752 kb
Host smart-8da02a69-9e7f-4657-bff2-1292dee2b9ae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8547755078987027874431769475095602608996181688090848965615041375079773602070 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.8547755078987027874431769475095602608996181688090848965615041375079773602070
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.28552588980602529129273264025294885302066067008038746233803434937962661465414
Short name T557
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.2 seconds
Started Nov 22 03:06:06 PM PST 23
Finished Nov 22 03:06:54 PM PST 23
Peak memory 553488 kb
Host smart-f3ac2057-a3d7-417f-aa24-2aa2d41fd741
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28552588980602529129273264025294885302066067008038746233803434937962661465414 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.28552588980602529129273264025294885302066067008038746233803434937962661465414
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_random.104001956225759101302730490320908352185486630483212988228611354372437542601708
Short name T1317
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.46 seconds
Started Nov 22 03:06:13 PM PST 23
Finished Nov 22 03:07:27 PM PST 23
Peak memory 553536 kb
Host smart-50a9e700-9130-48ae-af2a-0a4daa3356d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104001956225759101302730490320908352185486630483212988228611354372437542601708 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 32.xbar_error_random.104001956225759101302730490320908352185486630483212988228611354372437542601708
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random.62217250913201775662347865991008929782467689241342012325971402657855089724916
Short name T1473
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.6 seconds
Started Nov 22 03:06:22 PM PST 23
Finished Nov 22 03:07:42 PM PST 23
Peak memory 553684 kb
Host smart-ba3bc810-3bb8-420b-8013-35ca06f34274
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62217250913201775662347865991008929782467689241342012325971402657855089724916 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 32.xbar_random.62217250913201775662347865991008929782467689241342012325971402657855089724916
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.41021875217838060375368667557985349595751216016759366789859808257448227672317
Short name T1334
Test name
Test status
Simulation time 97702135727 ps
CPU time 1142.83 seconds
Started Nov 22 03:06:04 PM PST 23
Finished Nov 22 03:25:12 PM PST 23
Peak memory 553648 kb
Host smart-8e039396-7655-4f02-9a72-3d988a6c89f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41021875217838060375368667557985349595751216016759366789859808257448227672317 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.41021875217838060375368667557985349595751216016759366789859808257448227672317
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.88335315552676828802013034634730409971696678036351509359436087872606621847370
Short name T523
Test name
Test status
Simulation time 60576345727 ps
CPU time 1114.77 seconds
Started Nov 22 03:06:17 PM PST 23
Finished Nov 22 03:24:53 PM PST 23
Peak memory 553616 kb
Host smart-bd981d3d-c164-429f-aa69-d35f79153305
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88335315552676828802013034634730409971696678036351509359436087872606621847370 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.88335315552676828802013034634730409971696678036351509359436087872606621847370
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.114130864246023747709157841580358744970955080294600708276876128975267152389989
Short name T1719
Test name
Test status
Simulation time 556965727 ps
CPU time 47.27 seconds
Started Nov 22 03:06:04 PM PST 23
Finished Nov 22 03:06:56 PM PST 23
Peak memory 553704 kb
Host smart-1b795c0d-f15c-4e15-848b-717661b40369
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114130864246023747709157841580358744970955080294600708276876128975267152389989 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.114130864246023747709157841580358744970955080294600708276876128975267152389989
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_same_source.56746510402188595971986628959337974726904203116855588614638178978163440483452
Short name T1901
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.67 seconds
Started Nov 22 03:06:07 PM PST 23
Finished Nov 22 03:07:25 PM PST 23
Peak memory 553728 kb
Host smart-046c6f5b-398f-4761-9c6b-89aff10e7cf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56746510402188595971986628959337974726904203116855588614638178978163440483452 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.56746510402188595971986628959337974726904203116855588614638178978163440483452
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke.14854951790790779061208636007505295313389872663065524913913670152078141748479
Short name T1462
Test name
Test status
Simulation time 196985727 ps
CPU time 8.57 seconds
Started Nov 22 03:05:55 PM PST 23
Finished Nov 22 03:06:05 PM PST 23
Peak memory 552384 kb
Host smart-04b132fa-d56a-4153-972a-ff22c8b67774
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14854951790790779061208636007505295313389872663065524913913670152078141748479 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 32.xbar_smoke.14854951790790779061208636007505295313389872663065524913913670152078141748479
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.69774251791490852028347830411314571359238238414176085142644119919257196660731
Short name T1882
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.22 seconds
Started Nov 22 03:06:10 PM PST 23
Finished Nov 22 03:07:43 PM PST 23
Peak memory 552380 kb
Host smart-90b2b559-f0fc-4421-ad18-2ab5539f0a0c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69774251791490852028347830411314571359238238414176085142644119919257196660731 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.69774251791490852028347830411314571359238238414176085142644119919257196660731
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.96421542664406216948270342105169283671687591094814207028788335945054560506332
Short name T1700
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.91 seconds
Started Nov 22 03:06:20 PM PST 23
Finished Nov 22 03:07:45 PM PST 23
Peak memory 552416 kb
Host smart-ce36b4be-d7a4-4ef5-95d4-d5a892a5c1b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96421542664406216948270342105169283671687591094814207028788335945054560506332 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.96421542664406216948270342105169283671687591094814207028788335945054560506332
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.112722939459303458967887655586447476179321605770947328585804499135353309908801
Short name T577
Test name
Test status
Simulation time 45555727 ps
CPU time 6.05 seconds
Started Nov 22 03:06:01 PM PST 23
Finished Nov 22 03:06:08 PM PST 23
Peak memory 552348 kb
Host smart-9fce3d7f-5d4f-409d-90e6-7ab688ea6f11
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112722939459303458967887655586447476179321605770947328585804499135353309908801 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.112722939459303458967887655586447476179321605770947328585804499135353309908801
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all.96980319112493113932127114904229500569978453838154125790773085634576299567462
Short name T383
Test name
Test status
Simulation time 13992004073 ps
CPU time 535.3 seconds
Started Nov 22 03:06:19 PM PST 23
Finished Nov 22 03:15:15 PM PST 23
Peak memory 555788 kb
Host smart-4811c377-144a-40db-b514-f03551a0f565
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96980319112493113932127114904229500569978453838154125790773085634576299567462 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.96980319112493113932127114904229500569978453838154125790773085634576299567462
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.74081071275951774058432920363169657123046909641393915130541611730366272635266
Short name T1739
Test name
Test status
Simulation time 13999524073 ps
CPU time 538.79 seconds
Started Nov 22 03:06:18 PM PST 23
Finished Nov 22 03:15:18 PM PST 23
Peak memory 555672 kb
Host smart-ccc39382-459e-44df-9721-501e10778487
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74081071275951774058432920363169657123046909641393915130541611730366272635266 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.74081071275951774058432920363169657123046909641393915130541611730366272635266
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.48213026808163024023007927855510022465078444194543376601583566570076464015153
Short name T266
Test name
Test status
Simulation time 4815189184 ps
CPU time 385.35 seconds
Started Nov 22 03:06:08 PM PST 23
Finished Nov 22 03:12:35 PM PST 23
Peak memory 557188 kb
Host smart-5037adc7-56f1-477a-a2f5-353f82218fdb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48213026808163024023007927855510022465078444194543376601583566570076464015153 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.48213026808163024023007927855510022465078444194543376601583566
570076464015153
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.100453267912809660535567660788082234963229285939400367915163298913244173379848
Short name T1199
Test name
Test status
Simulation time 4815189184 ps
CPU time 309.33 seconds
Started Nov 22 03:06:11 PM PST 23
Finished Nov 22 03:11:22 PM PST 23
Peak memory 559716 kb
Host smart-ec23c50d-c5d3-40df-910a-d86c5405b81f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100453267912809660535567660788082234963229285939400367915163298913244173379848 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.10045326791280966053556766078808223496322928593940036791516
3298913244173379848
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.92124333196097926509209739936146404357640972254558406247706202370767175807593
Short name T397
Test name
Test status
Simulation time 1176995727 ps
CPU time 53.79 seconds
Started Nov 22 03:06:18 PM PST 23
Finished Nov 22 03:07:13 PM PST 23
Peak memory 553720 kb
Host smart-48ccee30-a3f1-4e57-aec0-d8c4e59253f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92124333196097926509209739936146404357640972254558406247706202370767175807593 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.92124333196097926509209739936146404357640972254558406247706202370767175807593
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device.110372826687994867990010544309591645819513465315997115146355743292202332127654
Short name T591
Test name
Test status
Simulation time 2590995727 ps
CPU time 113.63 seconds
Started Nov 22 03:06:05 PM PST 23
Finished Nov 22 03:08:02 PM PST 23
Peak memory 554708 kb
Host smart-091be8ab-c00e-4b19-b96b-c9bebd187039
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110372826687994867990010544309591645819513465315997115146355743292202332127654 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.110372826687994867990010544309591645819513465315997115146355743292202332127654
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.42846842609633273065928642325840338351830198160416874836658236720703508773224
Short name T915
Test name
Test status
Simulation time 115195295727 ps
CPU time 2034.03 seconds
Started Nov 22 03:06:26 PM PST 23
Finished Nov 22 03:40:21 PM PST 23
Peak memory 554760 kb
Host smart-25c30ac0-49e0-4155-a979-8e2c8305a618
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42846842609633273065928642325840338351830198160416874836658236720703508773224 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.42846842609633273065928642325840338351830198160416874836658236720703508773224
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.51366743259161662247349583286596214591325305139727590869475741201795907609491
Short name T686
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.66 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:07:07 PM PST 23
Peak memory 553532 kb
Host smart-054406d7-ce21-4022-bc17-448aba6a14ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51366743259161662247349583286596214591325305139727590869475741201795907609491 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.51366743259161662247349583286596214591325305139727590869475741201795907609491
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_random.12489184886170827861603515737721793783321246629265936144229112957660616517458
Short name T995
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.82 seconds
Started Nov 22 03:06:19 PM PST 23
Finished Nov 22 03:07:34 PM PST 23
Peak memory 553628 kb
Host smart-7b72847f-9c32-4d1c-9ffd-e8332f6b7ac7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12489184886170827861603515737721793783321246629265936144229112957660616517458 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 33.xbar_error_random.12489184886170827861603515737721793783321246629265936144229112957660616517458
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random.22091811956814574066401986840418220488707329553304789098992676124453515463060
Short name T213
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.02 seconds
Started Nov 22 03:06:10 PM PST 23
Finished Nov 22 03:07:30 PM PST 23
Peak memory 553748 kb
Host smart-e601c5ca-947e-4c37-8ced-7a009caf919c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091811956814574066401986840418220488707329553304789098992676124453515463060 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 33.xbar_random.22091811956814574066401986840418220488707329553304789098992676124453515463060
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.37981470318948379771595353525298528241309334859066198842890816152757443401741
Short name T1783
Test name
Test status
Simulation time 97702135727 ps
CPU time 1199.79 seconds
Started Nov 22 03:06:13 PM PST 23
Finished Nov 22 03:26:14 PM PST 23
Peak memory 553664 kb
Host smart-e7d0d66b-1835-4f91-a87f-153d72435c9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37981470318948379771595353525298528241309334859066198842890816152757443401741 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.37981470318948379771595353525298528241309334859066198842890816152757443401741
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.36158983927518781942715718952376532846290108153590099536693116433597208802118
Short name T602
Test name
Test status
Simulation time 60576345727 ps
CPU time 1094.79 seconds
Started Nov 22 03:06:11 PM PST 23
Finished Nov 22 03:24:28 PM PST 23
Peak memory 553768 kb
Host smart-91b6930f-5a88-440c-915c-b4232dbb6c69
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36158983927518781942715718952376532846290108153590099536693116433597208802118 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.36158983927518781942715718952376532846290108153590099536693116433597208802118
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.16628791602299956859315436246171792930462364978841499594270399170724291172971
Short name T235
Test name
Test status
Simulation time 556965727 ps
CPU time 45.54 seconds
Started Nov 22 03:06:19 PM PST 23
Finished Nov 22 03:07:05 PM PST 23
Peak memory 553716 kb
Host smart-279c877e-c620-4114-b1ab-241fd41046c9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628791602299956859315436246171792930462364978841499594270399170724291172971 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.16628791602299956859315436246171792930462364978841499594270399170724291172971
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_same_source.37559126989538656688497130548710238872301299394276100839670112993244735888861
Short name T976
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.29 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:07:35 PM PST 23
Peak memory 553696 kb
Host smart-b19043b6-7073-4c1e-85a2-e1cc45cbdbf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559126989538656688497130548710238872301299394276100839670112993244735888861 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.37559126989538656688497130548710238872301299394276100839670112993244735888861
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke.111665378323669930639883098702190966378660435209591014112860674954621276701948
Short name T824
Test name
Test status
Simulation time 196985727 ps
CPU time 8.36 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:06:32 PM PST 23
Peak memory 552292 kb
Host smart-38b10e7f-ad54-40c3-bf69-05d1cc1c12d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111665378323669930639883098702190966378660435209591014112860674954621276701948 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 33.xbar_smoke.111665378323669930639883098702190966378660435209591014112860674954621276701948
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.22295278679117587718302568584268313889312442390055962611975904434443396707883
Short name T1666
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.23 seconds
Started Nov 22 03:06:06 PM PST 23
Finished Nov 22 03:07:40 PM PST 23
Peak memory 552384 kb
Host smart-74ab396f-c440-4c55-a10e-303dd4b02d59
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22295278679117587718302568584268313889312442390055962611975904434443396707883 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.22295278679117587718302568584268313889312442390055962611975904434443396707883
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.48762481844879877404131409819609418926258256184872757309892652635453384281882
Short name T659
Test name
Test status
Simulation time 4856075727 ps
CPU time 91.86 seconds
Started Nov 22 03:06:06 PM PST 23
Finished Nov 22 03:07:41 PM PST 23
Peak memory 552372 kb
Host smart-81de5b69-0246-47e7-b531-32d88df00ab1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48762481844879877404131409819609418926258256184872757309892652635453384281882 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.48762481844879877404131409819609418926258256184872757309892652635453384281882
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.4942847547815717795567687514517700578964409039857741909055275235987597419099
Short name T1857
Test name
Test status
Simulation time 45555727 ps
CPU time 6.46 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:06:34 PM PST 23
Peak memory 552412 kb
Host smart-30caa745-f3ee-4bc0-9294-c086f2cd515c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4942847547815717795567687514517700578964409039857741909055275235987597419099 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4942847547815717795567687514517700578964409039857741909055275235987597419099
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all.24404266399156461261688054964586779471039681713523062341038311096232444194889
Short name T261
Test name
Test status
Simulation time 13992004073 ps
CPU time 510.65 seconds
Started Nov 22 03:06:09 PM PST 23
Finished Nov 22 03:14:41 PM PST 23
Peak memory 555840 kb
Host smart-61867cb3-70cf-43f8-8bc7-d6b20a1a54a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24404266399156461261688054964586779471039681713523062341038311096232444194889 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.24404266399156461261688054964586779471039681713523062341038311096232444194889
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.107366873817615406014529598010941846647188800865174736795600608066615581893647
Short name T1330
Test name
Test status
Simulation time 13999524073 ps
CPU time 511.45 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:15:00 PM PST 23
Peak memory 555696 kb
Host smart-6f7d0cb1-3615-4e11-a850-ddb7bfcd6eed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107366873817615406014529598010941846647188800865174736795600608066615581893647 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.107366873817615406014529598010941846647188800865174736795600608066615581893647
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.79739983153946766488708565111714114107877022471004944381636933415031375226617
Short name T410
Test name
Test status
Simulation time 4815189184 ps
CPU time 387.73 seconds
Started Nov 22 03:06:11 PM PST 23
Finished Nov 22 03:12:41 PM PST 23
Peak memory 557288 kb
Host smart-c9f1c636-6a6a-48fb-9b41-78096812a91f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79739983153946766488708565111714114107877022471004944381636933415031375226617 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.79739983153946766488708565111714114107877022471004944381636933
415031375226617
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.51148872357979718094136787062308915778818112294407901613085464073902917190467
Short name T768
Test name
Test status
Simulation time 4815189184 ps
CPU time 300.8 seconds
Started Nov 22 03:06:20 PM PST 23
Finished Nov 22 03:11:22 PM PST 23
Peak memory 559732 kb
Host smart-01f8482f-fd39-4360-ad4f-e988b50c5c60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51148872357979718094136787062308915778818112294407901613085464073902917190467 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.511488723579797180941367870623089157788181122944079016130854
64073902917190467
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.80637072825912522514835754728832125376822176585731829870959536924557000347157
Short name T1422
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.01 seconds
Started Nov 22 03:06:03 PM PST 23
Finished Nov 22 03:06:53 PM PST 23
Peak memory 553696 kb
Host smart-6b827f2a-61fb-4b6f-9de3-2ca1f2efb2e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80637072825912522514835754728832125376822176585731829870959536924557000347157 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.80637072825912522514835754728832125376822176585731829870959536924557000347157
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device.42716401403826562582431377792286164152793383695374499089405600366415389557288
Short name T612
Test name
Test status
Simulation time 2590995727 ps
CPU time 110.64 seconds
Started Nov 22 03:06:18 PM PST 23
Finished Nov 22 03:08:10 PM PST 23
Peak memory 554736 kb
Host smart-db999c66-12a7-4565-9e0e-b2b3776737c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42716401403826562582431377792286164152793383695374499089405600366415389557288 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.42716401403826562582431377792286164152793383695374499089405600366415389557288
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.31556183704295099183226152727209075549690812890367654917820125431534580850599
Short name T480
Test name
Test status
Simulation time 115195295727 ps
CPU time 2028.2 seconds
Started Nov 22 03:06:13 PM PST 23
Finished Nov 22 03:40:02 PM PST 23
Peak memory 554776 kb
Host smart-8e4a8ebe-2c6a-490d-ac82-165e043d6d70
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31556183704295099183226152727209075549690812890367654917820125431534580850599 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.31556183704295099183226152727209075549690812890367654917820125431534580850599
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.99421006432207467644411422341869080972079338989020207634414015345096288275907
Short name T1573
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.63 seconds
Started Nov 22 03:06:24 PM PST 23
Finished Nov 22 03:07:11 PM PST 23
Peak memory 553484 kb
Host smart-37b95cce-20eb-432f-87a4-a584992a12f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99421006432207467644411422341869080972079338989020207634414015345096288275907 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.99421006432207467644411422341869080972079338989020207634414015345096288275907
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_random.17281766088923332483249144324043520269775054816693910402255475720427931443750
Short name T1262
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.66 seconds
Started Nov 22 03:06:19 PM PST 23
Finished Nov 22 03:07:37 PM PST 23
Peak memory 553532 kb
Host smart-4cde7184-df7f-4e31-bbef-4d9e53242ef7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17281766088923332483249144324043520269775054816693910402255475720427931443750 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 34.xbar_error_random.17281766088923332483249144324043520269775054816693910402255475720427931443750
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random.86051680880468440384958859410159153683988967399661520695440953694589828593966
Short name T594
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.14 seconds
Started Nov 22 03:06:21 PM PST 23
Finished Nov 22 03:07:42 PM PST 23
Peak memory 553768 kb
Host smart-354d1266-2aee-405e-9d7d-a94536449d7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86051680880468440384958859410159153683988967399661520695440953694589828593966 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 34.xbar_random.86051680880468440384958859410159153683988967399661520695440953694589828593966
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.78972418067027244697832720758367192332610642352398787482905435328598091448854
Short name T111
Test name
Test status
Simulation time 97702135727 ps
CPU time 1164.01 seconds
Started Nov 22 03:06:18 PM PST 23
Finished Nov 22 03:25:43 PM PST 23
Peak memory 553608 kb
Host smart-c024ee92-0e18-447f-8f79-7ae734fb47fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78972418067027244697832720758367192332610642352398787482905435328598091448854 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.78972418067027244697832720758367192332610642352398787482905435328598091448854
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.69016904303409489913120411933366258076359576455122719124228903151308439907008
Short name T912
Test name
Test status
Simulation time 60576345727 ps
CPU time 1081.03 seconds
Started Nov 22 03:06:09 PM PST 23
Finished Nov 22 03:24:12 PM PST 23
Peak memory 553712 kb
Host smart-817016b5-5276-4458-a9b3-0e846f9fa8f0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69016904303409489913120411933366258076359576455122719124228903151308439907008 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.69016904303409489913120411933366258076359576455122719124228903151308439907008
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.30443276073148564126686957356207420398282630145556796597485777651737524349649
Short name T365
Test name
Test status
Simulation time 556965727 ps
CPU time 48.79 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:07:18 PM PST 23
Peak memory 553680 kb
Host smart-69c5ac63-86b7-4848-81c7-522fa974c774
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30443276073148564126686957356207420398282630145556796597485777651737524349649 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.30443276073148564126686957356207420398282630145556796597485777651737524349649
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_same_source.81336296884842122154699380650399501439699583961778337217480168046904882316750
Short name T1077
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.77 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:07:43 PM PST 23
Peak memory 553736 kb
Host smart-c0b2f3ad-e4d6-4661-9cf3-172ef44ea56b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81336296884842122154699380650399501439699583961778337217480168046904882316750 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.81336296884842122154699380650399501439699583961778337217480168046904882316750
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke.104228076906639589715563937329663762805020255876608916837833071235695586252563
Short name T1296
Test name
Test status
Simulation time 196985727 ps
CPU time 8.96 seconds
Started Nov 22 03:06:24 PM PST 23
Finished Nov 22 03:06:34 PM PST 23
Peak memory 552364 kb
Host smart-c7704565-5bfc-4ba8-bc1e-022fd3b8c3c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104228076906639589715563937329663762805020255876608916837833071235695586252563 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 34.xbar_smoke.104228076906639589715563937329663762805020255876608916837833071235695586252563
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.60705719279484685664316277002939078193184442406732078627662251584748856688424
Short name T812
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.67 seconds
Started Nov 22 03:06:18 PM PST 23
Finished Nov 22 03:07:48 PM PST 23
Peak memory 552328 kb
Host smart-3ad21a25-917c-4a17-9eec-419bd80cec4a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60705719279484685664316277002939078193184442406732078627662251584748856688424 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.60705719279484685664316277002939078193184442406732078627662251584748856688424
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.50868170737635038012865502991692147615245940139574822339902344309503636749764
Short name T239
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.26 seconds
Started Nov 22 03:06:19 PM PST 23
Finished Nov 22 03:07:50 PM PST 23
Peak memory 552392 kb
Host smart-1a7c65a8-af5f-4011-9f1f-a4cdd7959d2b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50868170737635038012865502991692147615245940139574822339902344309503636749764 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.50868170737635038012865502991692147615245940139574822339902344309503636749764
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.93721593393234801812788996158055431061026140163767308005431028575847810704273
Short name T864
Test name
Test status
Simulation time 45555727 ps
CPU time 5.95 seconds
Started Nov 22 03:06:24 PM PST 23
Finished Nov 22 03:06:31 PM PST 23
Peak memory 552384 kb
Host smart-523de227-9434-4f12-9f92-bbb366201421
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93721593393234801812788996158055431061026140163767308005431028575847810704273 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.93721593393234801812788996158055431061026140163767308005431028575847810704273
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all.67987867482843802592635557814609277075676676774506198130073767195690085342800
Short name T468
Test name
Test status
Simulation time 13992004073 ps
CPU time 548.05 seconds
Started Nov 22 03:06:17 PM PST 23
Finished Nov 22 03:15:27 PM PST 23
Peak memory 555852 kb
Host smart-104f747e-f971-442e-920d-9633e1fa9a8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67987867482843802592635557814609277075676676774506198130073767195690085342800 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.67987867482843802592635557814609277075676676774506198130073767195690085342800
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.63543526641143217764214935157147846049406627901120119809317472598703881044668
Short name T1373
Test name
Test status
Simulation time 13999524073 ps
CPU time 468.56 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:14:17 PM PST 23
Peak memory 555732 kb
Host smart-941d5414-0769-4325-94f7-68fce5de732b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63543526641143217764214935157147846049406627901120119809317472598703881044668 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.63543526641143217764214935157147846049406627901120119809317472598703881044668
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.28640920305925085890230601733817153994509137868539441099212690471676167670073
Short name T1088
Test name
Test status
Simulation time 4815189184 ps
CPU time 370.09 seconds
Started Nov 22 03:06:36 PM PST 23
Finished Nov 22 03:12:47 PM PST 23
Peak memory 557192 kb
Host smart-2463594b-150b-4ffc-a673-c0a282c24f02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28640920305925085890230601733817153994509137868539441099212690471676167670073 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.28640920305925085890230601733817153994509137868539441099212690
471676167670073
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.85987886236021881233247364672095739212334817662813959252899466716339056354935
Short name T409
Test name
Test status
Simulation time 4815189184 ps
CPU time 324.32 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:11:48 PM PST 23
Peak memory 559740 kb
Host smart-2c8aa114-9772-492b-932b-86771a9488c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85987886236021881233247364672095739212334817662813959252899466716339056354935 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.859878862360218812332473646720957392123348176628139592528994
66716339056354935
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.82837699794119911309201212516886754296461968163215467788931744976444591038314
Short name T793
Test name
Test status
Simulation time 1176995727 ps
CPU time 52.07 seconds
Started Nov 22 03:06:22 PM PST 23
Finished Nov 22 03:07:15 PM PST 23
Peak memory 553732 kb
Host smart-352dbb35-fed8-4b8c-866b-a49bb4b424eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82837699794119911309201212516886754296461968163215467788931744976444591038314 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.82837699794119911309201212516886754296461968163215467788931744976444591038314
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device.105107364055979833741898967712784364885013101044046629056938310098192164960576
Short name T1078
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.35 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:08:16 PM PST 23
Peak memory 554668 kb
Host smart-070b8d18-70d4-4a41-8fc0-b91e04d60a48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105107364055979833741898967712784364885013101044046629056938310098192164960576 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.105107364055979833741898967712784364885013101044046629056938310098192164960576
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.82981245531379944280173297450286004438917249818180033463515096244819453420564
Short name T1710
Test name
Test status
Simulation time 115195295727 ps
CPU time 2029.88 seconds
Started Nov 22 03:06:26 PM PST 23
Finished Nov 22 03:40:17 PM PST 23
Peak memory 554748 kb
Host smart-9fa7aab9-4648-44a0-aa56-6ab2d44c9373
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82981245531379944280173297450286004438917249818180033463515096244819453420564 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.82981245531379944280173297450286004438917249818180033463515096244819453420564
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.75629978893435700363542847334937289025964367139093970931092000734599308733940
Short name T1057
Test name
Test status
Simulation time 1171215727 ps
CPU time 41.8 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:07:12 PM PST 23
Peak memory 553496 kb
Host smart-5ab17649-cb4b-4627-97f1-ca0edf15bc97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75629978893435700363542847334937289025964367139093970931092000734599308733940 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.75629978893435700363542847334937289025964367139093970931092000734599308733940
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_random.80459077319224859343207774445641627898282688629283430624564325974177948017050
Short name T396
Test name
Test status
Simulation time 2231375727 ps
CPU time 70.1 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:07:33 PM PST 23
Peak memory 553468 kb
Host smart-f452912b-4968-43bb-976a-6e116affcf08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80459077319224859343207774445641627898282688629283430624564325974177948017050 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 35.xbar_error_random.80459077319224859343207774445641627898282688629283430624564325974177948017050
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random.76640476450338777159872362188315796076225413787705548034114317846482021199610
Short name T683
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.8 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:07:48 PM PST 23
Peak memory 553628 kb
Host smart-1d931d87-159c-40ae-b975-adcf90fcd1a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76640476450338777159872362188315796076225413787705548034114317846482021199610 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 35.xbar_random.76640476450338777159872362188315796076225413787705548034114317846482021199610
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.83639396986616092922454740627365813171200128296665011597115030147126737174223
Short name T1050
Test name
Test status
Simulation time 97702135727 ps
CPU time 1173.55 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:26:02 PM PST 23
Peak memory 553668 kb
Host smart-757c2692-6abc-4cb6-b45d-d6accfd01609
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83639396986616092922454740627365813171200128296665011597115030147126737174223 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.83639396986616092922454740627365813171200128296665011597115030147126737174223
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.69210850077774235793192107024548198621775348642357067652819832734192970182009
Short name T1216
Test name
Test status
Simulation time 60576345727 ps
CPU time 1126.38 seconds
Started Nov 22 03:06:22 PM PST 23
Finished Nov 22 03:25:09 PM PST 23
Peak memory 553640 kb
Host smart-285c0b37-0270-461a-836d-70efbc234aac
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69210850077774235793192107024548198621775348642357067652819832734192970182009 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.69210850077774235793192107024548198621775348642357067652819832734192970182009
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.78912090471161567518937026077165819961380425478776103744721484082621484989065
Short name T1869
Test name
Test status
Simulation time 556965727 ps
CPU time 46.87 seconds
Started Nov 22 03:06:20 PM PST 23
Finished Nov 22 03:07:08 PM PST 23
Peak memory 553732 kb
Host smart-e3bea9d9-e277-411b-b2f9-be2d4cdb92db
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78912090471161567518937026077165819961380425478776103744721484082621484989065 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.78912090471161567518937026077165819961380425478776103744721484082621484989065
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_same_source.63801318804587916659057236906015822513248730316827280116615453110532105723600
Short name T283
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.85 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:07:44 PM PST 23
Peak memory 553680 kb
Host smart-24ecac8c-ab94-4bd1-a303-69a20f0fe796
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63801318804587916659057236906015822513248730316827280116615453110532105723600 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.63801318804587916659057236906015822513248730316827280116615453110532105723600
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke.1531376187743426425343689570989631447050062910901495932784031825789738936348
Short name T120
Test name
Test status
Simulation time 196985727 ps
CPU time 8.91 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:06:33 PM PST 23
Peak memory 552280 kb
Host smart-a938ca22-d913-4339-814a-1120ae6d96d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531376187743426425343689570989631447050062910901495932784031825789738936348 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 35.xbar_smoke.1531376187743426425343689570989631447050062910901495932784031825789738936348
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.42405435551097450191738092967380917963118242449983251064874876386956858519638
Short name T628
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.94 seconds
Started Nov 22 03:06:12 PM PST 23
Finished Nov 22 03:07:45 PM PST 23
Peak memory 552424 kb
Host smart-0eba952a-a5ea-473b-a01a-256ae2bdcd7b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42405435551097450191738092967380917963118242449983251064874876386956858519638 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.42405435551097450191738092967380917963118242449983251064874876386956858519638
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.47469184580834256707107663958210583880489445913735439672305827262488070100332
Short name T800
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.74 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:07:50 PM PST 23
Peak memory 552380 kb
Host smart-3046d46b-da79-48e8-8a7a-de6184de0bc0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47469184580834256707107663958210583880489445913735439672305827262488070100332 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.47469184580834256707107663958210583880489445913735439672305827262488070100332
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.82638940447357021753142057205628742757747113542955490543685748421054156283074
Short name T1526
Test name
Test status
Simulation time 45555727 ps
CPU time 5.91 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:06:33 PM PST 23
Peak memory 552312 kb
Host smart-1e21c294-940f-4bbe-8c60-6c4f1a68edd2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82638940447357021753142057205628742757747113542955490543685748421054156283074 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.82638940447357021753142057205628742757747113542955490543685748421054156283074
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all.44550441934850468415211695338383397203778629758462986696333267077738853692084
Short name T1768
Test name
Test status
Simulation time 13992004073 ps
CPU time 520.12 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:15:04 PM PST 23
Peak memory 555956 kb
Host smart-4a24a5f3-b130-4f13-b714-d439f9e9ef46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44550441934850468415211695338383397203778629758462986696333267077738853692084 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.44550441934850468415211695338383397203778629758462986696333267077738853692084
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.96785264473429140089627326006813652365583747883831819031955938264751509319886
Short name T328
Test name
Test status
Simulation time 13999524073 ps
CPU time 554.39 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:15:45 PM PST 23
Peak memory 555640 kb
Host smart-ae20930f-4f18-4c17-95d5-8f89cdc44f9b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96785264473429140089627326006813652365583747883831819031955938264751509319886 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.96785264473429140089627326006813652365583747883831819031955938264751509319886
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.101106192829824065865378235440137846983326541190200923317782686195210490185888
Short name T657
Test name
Test status
Simulation time 4815189184 ps
CPU time 359.34 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:12:30 PM PST 23
Peak memory 557268 kb
Host smart-3d5364e5-3173-4db9-99e8-ac4bf0b9c79c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101106192829824065865378235440137846983326541190200923317782686195210490185888 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1011061928298240658653782354401378469833265411902009233177826
86195210490185888
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.63307476432660381737076519678875451815882044588269053511694275370764602859347
Short name T1282
Test name
Test status
Simulation time 4815189184 ps
CPU time 312.79 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:11:43 PM PST 23
Peak memory 559704 kb
Host smart-b1a7f1f2-e970-4bfb-abf4-b1b42c8042d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63307476432660381737076519678875451815882044588269053511694275370764602859347 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.633074764326603817370765196788754518158820445882690535116942
75370764602859347
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.76335893622787507282088863995301524304539446561360524350887973149661441534828
Short name T295
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.13 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:07:19 PM PST 23
Peak memory 553732 kb
Host smart-a8721a9e-2fec-4d3d-80a4-aca6274142b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76335893622787507282088863995301524304539446561360524350887973149661441534828 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.76335893622787507282088863995301524304539446561360524350887973149661441534828
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device.63545284827190259101473976387988171557759733386368576477156756958156095553267
Short name T1780
Test name
Test status
Simulation time 2590995727 ps
CPU time 105.96 seconds
Started Nov 22 03:06:30 PM PST 23
Finished Nov 22 03:08:17 PM PST 23
Peak memory 554796 kb
Host smart-54725d4f-4bae-4a69-bad6-447c8fdfb5fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63545284827190259101473976387988171557759733386368576477156756958156095553267 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.63545284827190259101473976387988171557759733386368576477156756958156095553267
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.104008163504633790416980936477071792713233796089540107767213228544944856068873
Short name T219
Test name
Test status
Simulation time 115195295727 ps
CPU time 1913.8 seconds
Started Nov 22 03:06:30 PM PST 23
Finished Nov 22 03:38:25 PM PST 23
Peak memory 554744 kb
Host smart-e2771652-a3c0-4a0e-b432-e6f3085f869c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104008163504633790416980936477071792713233796089540107767213228544944856068873 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.104008163504633790416980936477071792713233796089540107767213228544944856068873
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.114508605221987442267528534548594618364275997325688236896116140040014536265354
Short name T405
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.87 seconds
Started Nov 22 03:06:42 PM PST 23
Finished Nov 22 03:07:26 PM PST 23
Peak memory 553480 kb
Host smart-9717a895-dc0a-417b-a028-e2d497013871
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114508605221987442267528534548594618364275997325688236896116140040014536265354 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.114508605221987442267528534548594618364275997325688236896116140040014536265354
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_random.64040385932309626347121948663228318368431829110352707336063990662671363974789
Short name T1826
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.09 seconds
Started Nov 22 03:06:30 PM PST 23
Finished Nov 22 03:07:44 PM PST 23
Peak memory 553544 kb
Host smart-a449ac2d-254f-4727-a477-e8ad9e5c667f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64040385932309626347121948663228318368431829110352707336063990662671363974789 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 36.xbar_error_random.64040385932309626347121948663228318368431829110352707336063990662671363974789
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random.92071131913180823019095044968079034080950747459053530946682316832186785898436
Short name T1140
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.63 seconds
Started Nov 22 03:06:24 PM PST 23
Finished Nov 22 03:07:41 PM PST 23
Peak memory 553596 kb
Host smart-e93b5295-d2c9-4181-a4a6-c07c4ee2cd19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92071131913180823019095044968079034080950747459053530946682316832186785898436 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 36.xbar_random.92071131913180823019095044968079034080950747459053530946682316832186785898436
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.12325138564304112199653138003888509353428756458243412132193042314442550818241
Short name T1407
Test name
Test status
Simulation time 97702135727 ps
CPU time 1175.56 seconds
Started Nov 22 03:06:25 PM PST 23
Finished Nov 22 03:26:01 PM PST 23
Peak memory 553584 kb
Host smart-af6f4649-b47d-463b-b9ea-d5a5051e2dbf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12325138564304112199653138003888509353428756458243412132193042314442550818241 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.12325138564304112199653138003888509353428756458243412132193042314442550818241
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.35136530399097755325704259556849947969634409742005844181132231377577616783310
Short name T1281
Test name
Test status
Simulation time 60576345727 ps
CPU time 1125.93 seconds
Started Nov 22 03:06:19 PM PST 23
Finished Nov 22 03:25:06 PM PST 23
Peak memory 553664 kb
Host smart-5df5d7ef-871c-422d-ad8b-401d71790579
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35136530399097755325704259556849947969634409742005844181132231377577616783310 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.35136530399097755325704259556849947969634409742005844181132231377577616783310
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.87491347618143848387658152394999498337373606448944297267692588019948732589669
Short name T1356
Test name
Test status
Simulation time 556965727 ps
CPU time 49.94 seconds
Started Nov 22 03:06:22 PM PST 23
Finished Nov 22 03:07:12 PM PST 23
Peak memory 553616 kb
Host smart-b881fc88-74a7-4e13-b19e-8aa2afde5b0b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87491347618143848387658152394999498337373606448944297267692588019948732589669 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.87491347618143848387658152394999498337373606448944297267692588019948732589669
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_same_source.85648353900264474197918849630826615233940844741581609529835387065608644490335
Short name T1671
Test name
Test status
Simulation time 2498784073 ps
CPU time 82.71 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:07:52 PM PST 23
Peak memory 553716 kb
Host smart-55f66322-c1eb-4c94-87cb-26227ddadb6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85648353900264474197918849630826615233940844741581609529835387065608644490335 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.85648353900264474197918849630826615233940844741581609529835387065608644490335
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke.107426657772564776697423062902375969539385301115933196409290924514907956192049
Short name T122
Test name
Test status
Simulation time 196985727 ps
CPU time 8.89 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:06:39 PM PST 23
Peak memory 552392 kb
Host smart-65ca405a-5f5b-4fd6-9fec-2ac7f1ab831a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107426657772564776697423062902375969539385301115933196409290924514907956192049 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 36.xbar_smoke.107426657772564776697423062902375969539385301115933196409290924514907956192049
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.41903675741350593552853431619036868004401730114841353080114763267239762622939
Short name T271
Test name
Test status
Simulation time 7758585727 ps
CPU time 94.4 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:08:04 PM PST 23
Peak memory 552376 kb
Host smart-3ab97568-2890-4268-91de-1fec5772862a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41903675741350593552853431619036868004401730114841353080114763267239762622939 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.41903675741350593552853431619036868004401730114841353080114763267239762622939
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.33643051141793130543807908102565172730670291886073968685398175038012727994953
Short name T1632
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.78 seconds
Started Nov 22 03:06:23 PM PST 23
Finished Nov 22 03:07:50 PM PST 23
Peak memory 552380 kb
Host smart-cf461cea-7bb0-4cc3-bb91-37cddfd76535
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33643051141793130543807908102565172730670291886073968685398175038012727994953 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.33643051141793130543807908102565172730670291886073968685398175038012727994953
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.37122839673451824260116632732560284886753832446946826285704679280245819251904
Short name T493
Test name
Test status
Simulation time 45555727 ps
CPU time 5.62 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:06:34 PM PST 23
Peak memory 552364 kb
Host smart-4d6e2e7f-e060-45c7-b472-414b8913e695
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37122839673451824260116632732560284886753832446946826285704679280245819251904 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.37122839673451824260116632732560284886753832446946826285704679280245819251904
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all.23317541906751480762242813027093420160684605090071199370539307980988924751811
Short name T779
Test name
Test status
Simulation time 13992004073 ps
CPU time 579.24 seconds
Started Nov 22 03:06:30 PM PST 23
Finished Nov 22 03:16:10 PM PST 23
Peak memory 555916 kb
Host smart-291c263d-0e5b-4673-8e62-e555ea43ce4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23317541906751480762242813027093420160684605090071199370539307980988924751811 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.23317541906751480762242813027093420160684605090071199370539307980988924751811
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.49886823319392194251663071578767232300966633113859182157233647154316688240214
Short name T1669
Test name
Test status
Simulation time 13999524073 ps
CPU time 524.58 seconds
Started Nov 22 03:06:30 PM PST 23
Finished Nov 22 03:15:15 PM PST 23
Peak memory 555724 kb
Host smart-fffac276-7e4a-487c-968f-df3b0d2b528f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49886823319392194251663071578767232300966633113859182157233647154316688240214 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.49886823319392194251663071578767232300966633113859182157233647154316688240214
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.92804453886782812674864495386564097568695865017682286672327923883898306007409
Short name T1388
Test name
Test status
Simulation time 4815189184 ps
CPU time 392.48 seconds
Started Nov 22 03:06:27 PM PST 23
Finished Nov 22 03:13:01 PM PST 23
Peak memory 557256 kb
Host smart-651e4bc4-ebd4-447d-b8fe-abd69a0096fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92804453886782812674864495386564097568695865017682286672327923883898306007409 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.92804453886782812674864495386564097568695865017682286672327923
883898306007409
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1795729739514662070637240078744646644695870322544158050192227017717903102220
Short name T384
Test name
Test status
Simulation time 4815189184 ps
CPU time 313 seconds
Started Nov 22 03:06:24 PM PST 23
Finished Nov 22 03:11:38 PM PST 23
Peak memory 559568 kb
Host smart-3320b7ba-0548-4b93-bfcb-b3948bacb178
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795729739514662070637240078744646644695870322544158050192227017717903102220 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1795729739514662070637240078744646644695870322544158050192227
017717903102220
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.19036557405200843277465504170562514899959180569981023250791679800967185875436
Short name T1156
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.76 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:07:18 PM PST 23
Peak memory 553644 kb
Host smart-b601c65d-c91a-4308-8c68-27177644a06d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19036557405200843277465504170562514899959180569981023250791679800967185875436 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.19036557405200843277465504170562514899959180569981023250791679800967185875436
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device.67927244793993255471757771138784721853621076782248738274189216661538045087841
Short name T971
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.21 seconds
Started Nov 22 03:06:39 PM PST 23
Finished Nov 22 03:08:29 PM PST 23
Peak memory 554832 kb
Host smart-1832f99e-25c1-4bf3-9070-d3a4d1fbf45c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67927244793993255471757771138784721853621076782248738274189216661538045087841 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.67927244793993255471757771138784721853621076782248738274189216661538045087841
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.90223575888961158486177446154961355362912329804828408465153526857368947193452
Short name T92
Test name
Test status
Simulation time 115195295727 ps
CPU time 1931.71 seconds
Started Nov 22 03:06:39 PM PST 23
Finished Nov 22 03:38:51 PM PST 23
Peak memory 554440 kb
Host smart-ad4c9a22-1bbc-4a17-b046-cef81f2c5a97
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90223575888961158486177446154961355362912329804828408465153526857368947193452 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.90223575888961158486177446154961355362912329804828408465153526857368947193452
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.22115438663364605117596174483987361308528241654394243561715510913027858074567
Short name T201
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.26 seconds
Started Nov 22 03:06:35 PM PST 23
Finished Nov 22 03:07:21 PM PST 23
Peak memory 553584 kb
Host smart-07f04c4e-d13d-4f89-a441-c48a9ae83f6a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22115438663364605117596174483987361308528241654394243561715510913027858074567 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.22115438663364605117596174483987361308528241654394243561715510913027858074567
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_random.93652753629632949305825663650985122381240490530653820584894244133491234597117
Short name T1550
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.8 seconds
Started Nov 22 03:06:36 PM PST 23
Finished Nov 22 03:07:52 PM PST 23
Peak memory 553628 kb
Host smart-d7fcf5a1-918b-4728-bfe8-5a8092361951
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93652753629632949305825663650985122381240490530653820584894244133491234597117 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 37.xbar_error_random.93652753629632949305825663650985122381240490530653820584894244133491234597117
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random.84159690733771355581130003290898081146230400495565210726891495795588847073958
Short name T197
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.17 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:07:49 PM PST 23
Peak memory 553752 kb
Host smart-8b22326d-0817-454f-86dd-d51ef40281ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84159690733771355581130003290898081146230400495565210726891495795588847073958 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 37.xbar_random.84159690733771355581130003290898081146230400495565210726891495795588847073958
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.38343319254784269492763277864772326985485581454277974086174227612294841323545
Short name T1001
Test name
Test status
Simulation time 97702135727 ps
CPU time 1140.51 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:25:30 PM PST 23
Peak memory 553648 kb
Host smart-be200bb8-0899-4dca-93e7-106987dcb446
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38343319254784269492763277864772326985485581454277974086174227612294841323545 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.38343319254784269492763277864772326985485581454277974086174227612294841323545
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.106601736915429862320294936972385579947110039373448803835762122836971995748902
Short name T1678
Test name
Test status
Simulation time 60576345727 ps
CPU time 1059.88 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:24:09 PM PST 23
Peak memory 553732 kb
Host smart-5da061e6-9c23-4005-bbcf-fe6080b2a44c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106601736915429862320294936972385579947110039373448803835762122836971995748902 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.106601736915429862320294936972385579947110039373448803835762122836971995748902
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.62211098615307075459123858721104915670584971500914254257157010596104243201672
Short name T432
Test name
Test status
Simulation time 556965727 ps
CPU time 45.92 seconds
Started Nov 22 03:06:30 PM PST 23
Finished Nov 22 03:07:17 PM PST 23
Peak memory 553736 kb
Host smart-58af2ac6-1827-4c1e-9983-80f9ae5e42b9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62211098615307075459123858721104915670584971500914254257157010596104243201672 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.62211098615307075459123858721104915670584971500914254257157010596104243201672
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_same_source.63808332666818251703995557657626264607690733458173366573156419988137968271301
Short name T1629
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.55 seconds
Started Nov 22 03:06:39 PM PST 23
Finished Nov 22 03:07:55 PM PST 23
Peak memory 553328 kb
Host smart-592c4cb1-eb71-4997-ad09-53c62ef2ea2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63808332666818251703995557657626264607690733458173366573156419988137968271301 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.63808332666818251703995557657626264607690733458173366573156419988137968271301
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke.106202229261643723783374381494112750735213914581542638274831243324823300116814
Short name T355
Test name
Test status
Simulation time 196985727 ps
CPU time 9.22 seconds
Started Nov 22 03:06:24 PM PST 23
Finished Nov 22 03:06:34 PM PST 23
Peak memory 552368 kb
Host smart-b2ed2b8a-b0ba-4bf9-9749-552887e91a5b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106202229261643723783374381494112750735213914581542638274831243324823300116814 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 37.xbar_smoke.106202229261643723783374381494112750735213914581542638274831243324823300116814
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.32187301662284871292828612545375439716680756897781164581027039904352987452307
Short name T884
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.22 seconds
Started Nov 22 03:06:37 PM PST 23
Finished Nov 22 03:08:08 PM PST 23
Peak memory 552328 kb
Host smart-40ea6a34-720b-44fa-9fbf-6744e33d1c6d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32187301662284871292828612545375439716680756897781164581027039904352987452307 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.32187301662284871292828612545375439716680756897781164581027039904352987452307
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.90608303259215093847624274210224124952109914319677536593576148020681059106925
Short name T1312
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.23 seconds
Started Nov 22 03:06:35 PM PST 23
Finished Nov 22 03:08:05 PM PST 23
Peak memory 552208 kb
Host smart-62dc5cbc-a08d-4b60-9136-687d92d4beb6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90608303259215093847624274210224124952109914319677536593576148020681059106925 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.90608303259215093847624274210224124952109914319677536593576148020681059106925
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.82695845950784179948273980920603733936723240429125977984509238091746922960271
Short name T525
Test name
Test status
Simulation time 45555727 ps
CPU time 6.34 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:06:35 PM PST 23
Peak memory 552360 kb
Host smart-ddc3f8d4-436e-4bd5-853b-4bfe5a500b0e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82695845950784179948273980920603733936723240429125977984509238091746922960271 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.82695845950784179948273980920603733936723240429125977984509238091746922960271
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all.65757539568638142782465458507323138529742834266066524887582706900564234435074
Short name T1626
Test name
Test status
Simulation time 13992004073 ps
CPU time 559.23 seconds
Started Nov 22 03:06:31 PM PST 23
Finished Nov 22 03:15:51 PM PST 23
Peak memory 555876 kb
Host smart-2c5b9855-2324-4f2f-8989-390309625568
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65757539568638142782465458507323138529742834266066524887582706900564234435074 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.65757539568638142782465458507323138529742834266066524887582706900564234435074
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.94465256616891470825970729938804924382032145816739923763483823506818090551265
Short name T1781
Test name
Test status
Simulation time 13999524073 ps
CPU time 527.91 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:15:18 PM PST 23
Peak memory 555608 kb
Host smart-2fdbd007-4c1f-467c-82ee-f910b061c604
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94465256616891470825970729938804924382032145816739923763483823506818090551265 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.94465256616891470825970729938804924382032145816739923763483823506818090551265
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.110228739998740352677235693123123938169716168424265975692984466293808409076566
Short name T585
Test name
Test status
Simulation time 4815189184 ps
CPU time 354.48 seconds
Started Nov 22 03:06:41 PM PST 23
Finished Nov 22 03:12:36 PM PST 23
Peak memory 557252 kb
Host smart-82998b04-82cd-4e61-9440-07d12cfeaca2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110228739998740352677235693123123938169716168424265975692984466293808409076566 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.1102287399987403526772356931231239381697161684242659756929844
66293808409076566
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.18241452102006104475438127944568368230807894111952636816024641574683667810885
Short name T1476
Test name
Test status
Simulation time 4815189184 ps
CPU time 297.25 seconds
Started Nov 22 03:06:42 PM PST 23
Finished Nov 22 03:11:39 PM PST 23
Peak memory 559708 kb
Host smart-07fe51b6-5ebd-4fb7-87b7-e43642e59e1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18241452102006104475438127944568368230807894111952636816024641574683667810885 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.182414521020061044754381279445683682308078941119526368160246
41574683667810885
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.62017846166068211804915949463266450219479388738218067368904704570496811758608
Short name T802
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.71 seconds
Started Nov 22 03:06:30 PM PST 23
Finished Nov 22 03:07:19 PM PST 23
Peak memory 553700 kb
Host smart-1e0da268-4348-4314-aceb-49b91a72a3f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62017846166068211804915949463266450219479388738218067368904704570496811758608 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.62017846166068211804915949463266450219479388738218067368904704570496811758608
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device.85741728159824554668111771142294108300854442487782839552068666166038495214965
Short name T1621
Test name
Test status
Simulation time 2590995727 ps
CPU time 103.77 seconds
Started Nov 22 03:06:43 PM PST 23
Finished Nov 22 03:08:27 PM PST 23
Peak memory 554792 kb
Host smart-7c10f498-87fa-4951-891a-c3ea26347c7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85741728159824554668111771142294108300854442487782839552068666166038495214965 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.85741728159824554668111771142294108300854442487782839552068666166038495214965
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.46171834595989885643140048639767231854360424059972658979829569744223746527796
Short name T1642
Test name
Test status
Simulation time 115195295727 ps
CPU time 2024.02 seconds
Started Nov 22 03:06:36 PM PST 23
Finished Nov 22 03:40:21 PM PST 23
Peak memory 554788 kb
Host smart-aa20fc82-aa96-419f-91fc-73e7ab9ad0e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46171834595989885643140048639767231854360424059972658979829569744223746527796 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.46171834595989885643140048639767231854360424059972658979829569744223746527796
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4597166127338318729100742666319985150007236784849443869317085252394191884526
Short name T680
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.14 seconds
Started Nov 22 03:06:40 PM PST 23
Finished Nov 22 03:07:26 PM PST 23
Peak memory 553508 kb
Host smart-95a68010-9c7e-46ab-9495-968ec927efa4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4597166127338318729100742666319985150007236784849443869317085252394191884526 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.4597166127338318729100742666319985150007236784849443869317085252394191884526
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_random.73101480754993107868141283678200989569306100400449419947256500594571742171980
Short name T1147
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.59 seconds
Started Nov 22 03:06:45 PM PST 23
Finished Nov 22 03:08:04 PM PST 23
Peak memory 553612 kb
Host smart-cc86a8ea-d3af-4f81-bf93-a5f3a523a3bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73101480754993107868141283678200989569306100400449419947256500594571742171980 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 38.xbar_error_random.73101480754993107868141283678200989569306100400449419947256500594571742171980
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random.13538396768393214463803709396673399959651248562380974217497102321195352005470
Short name T1432
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.39 seconds
Started Nov 22 03:06:37 PM PST 23
Finished Nov 22 03:07:54 PM PST 23
Peak memory 553696 kb
Host smart-46f69127-a6d5-438d-bf18-7b06b844fd90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13538396768393214463803709396673399959651248562380974217497102321195352005470 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 38.xbar_random.13538396768393214463803709396673399959651248562380974217497102321195352005470
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.52150291857577304624555794185324558641927283865068909141535395590400941732088
Short name T560
Test name
Test status
Simulation time 97702135727 ps
CPU time 1170.49 seconds
Started Nov 22 03:06:28 PM PST 23
Finished Nov 22 03:25:59 PM PST 23
Peak memory 553640 kb
Host smart-d8d0c468-aafc-4a4e-8b51-f6063400a5df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52150291857577304624555794185324558641927283865068909141535395590400941732088 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.52150291857577304624555794185324558641927283865068909141535395590400941732088
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.65964904352756857694386645948169824363495805030439166712247073995290756365987
Short name T1782
Test name
Test status
Simulation time 60576345727 ps
CPU time 1087.24 seconds
Started Nov 22 03:06:39 PM PST 23
Finished Nov 22 03:24:47 PM PST 23
Peak memory 553768 kb
Host smart-2d838153-be0b-4713-ba44-a301389d85ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65964904352756857694386645948169824363495805030439166712247073995290756365987 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.65964904352756857694386645948169824363495805030439166712247073995290756365987
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.86783823147937028965821621252563394300517448133944054880822550369756929276643
Short name T1326
Test name
Test status
Simulation time 556965727 ps
CPU time 45.5 seconds
Started Nov 22 03:06:39 PM PST 23
Finished Nov 22 03:07:25 PM PST 23
Peak memory 553764 kb
Host smart-4405939c-5c7c-4c20-bdf4-1cd9ddf1249b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86783823147937028965821621252563394300517448133944054880822550369756929276643 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.86783823147937028965821621252563394300517448133944054880822550369756929276643
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_same_source.30474083026396146308033732612727449147789482244078722726548844467213344445801
Short name T49
Test name
Test status
Simulation time 2498784073 ps
CPU time 80.84 seconds
Started Nov 22 03:06:41 PM PST 23
Finished Nov 22 03:08:02 PM PST 23
Peak memory 553848 kb
Host smart-4f7468c1-f841-4f36-96b1-fad59318cd6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30474083026396146308033732612727449147789482244078722726548844467213344445801 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.30474083026396146308033732612727449147789482244078722726548844467213344445801
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke.30592784778629369268953373220550288433490878900513329096188281488208214117081
Short name T1477
Test name
Test status
Simulation time 196985727 ps
CPU time 8.82 seconds
Started Nov 22 03:06:42 PM PST 23
Finished Nov 22 03:06:51 PM PST 23
Peak memory 552364 kb
Host smart-7b3b820c-3803-4477-8403-d2faf341dc19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30592784778629369268953373220550288433490878900513329096188281488208214117081 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 38.xbar_smoke.30592784778629369268953373220550288433490878900513329096188281488208214117081
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.49722691005545163963571679319496233957749568373183676723244834566423453074786
Short name T1478
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.17 seconds
Started Nov 22 03:06:42 PM PST 23
Finished Nov 22 03:08:12 PM PST 23
Peak memory 552384 kb
Host smart-b3be016e-4deb-4e3c-8d3e-561760e5426f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49722691005545163963571679319496233957749568373183676723244834566423453074786 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.49722691005545163963571679319496233957749568373183676723244834566423453074786
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.48726097709664267679033276359991667949887572460935133581479154000530420651342
Short name T102
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.74 seconds
Started Nov 22 03:06:35 PM PST 23
Finished Nov 22 03:08:04 PM PST 23
Peak memory 552492 kb
Host smart-472d85bd-e309-4908-8020-888139e29a23
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48726097709664267679033276359991667949887572460935133581479154000530420651342 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.48726097709664267679033276359991667949887572460935133581479154000530420651342
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.51508272468324887810678327216299437654061369200726293373766141381490998274980
Short name T232
Test name
Test status
Simulation time 45555727 ps
CPU time 5.92 seconds
Started Nov 22 03:06:29 PM PST 23
Finished Nov 22 03:06:36 PM PST 23
Peak memory 552188 kb
Host smart-9165d434-5a11-4064-ae28-fb197a960379
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51508272468324887810678327216299437654061369200726293373766141381490998274980 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.51508272468324887810678327216299437654061369200726293373766141381490998274980
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all.55888781997467385253321370742301929968693721252200218347322666417984650398027
Short name T274
Test name
Test status
Simulation time 13992004073 ps
CPU time 580.23 seconds
Started Nov 22 03:06:37 PM PST 23
Finished Nov 22 03:16:18 PM PST 23
Peak memory 555920 kb
Host smart-a85e80b3-dcef-43f6-b094-caeb9276ced6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55888781997467385253321370742301929968693721252200218347322666417984650398027 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.55888781997467385253321370742301929968693721252200218347322666417984650398027
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.8795676922676705487079609525274256276261121410917786121472173574626287598886
Short name T245
Test name
Test status
Simulation time 13999524073 ps
CPU time 487.06 seconds
Started Nov 22 03:06:37 PM PST 23
Finished Nov 22 03:14:45 PM PST 23
Peak memory 555720 kb
Host smart-c2a2846f-e60d-447f-a0e4-fa4e3cea128a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8795676922676705487079609525274256276261121410917786121472173574626287598886 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.8795676922676705487079609525274256276261121410917786121472173574626287598886
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.97671754608502663367827864164755199315664967242278371540261109543744935616303
Short name T1428
Test name
Test status
Simulation time 4815189184 ps
CPU time 371.96 seconds
Started Nov 22 03:06:37 PM PST 23
Finished Nov 22 03:12:49 PM PST 23
Peak memory 557164 kb
Host smart-bf64370f-d569-47e6-b8b9-f42d98916c98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97671754608502663367827864164755199315664967242278371540261109543744935616303 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.97671754608502663367827864164755199315664967242278371540261109
543744935616303
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.82171937574578053027814085249934404707564730673574904140485220905470142071779
Short name T593
Test name
Test status
Simulation time 4815189184 ps
CPU time 334.89 seconds
Started Nov 22 03:06:39 PM PST 23
Finished Nov 22 03:12:14 PM PST 23
Peak memory 559636 kb
Host smart-62b0be12-9fc0-415e-8889-1d75928416c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82171937574578053027814085249934404707564730673574904140485220905470142071779 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.821719375745780530278140852499344047075647306735749041404852
20905470142071779
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.4688383329304755663645206414547954120843287991395112713682168168761538772851
Short name T332
Test name
Test status
Simulation time 1176995727 ps
CPU time 53.7 seconds
Started Nov 22 03:06:40 PM PST 23
Finished Nov 22 03:07:34 PM PST 23
Peak memory 553712 kb
Host smart-9de9b9b3-1334-4a2c-8ba1-b61e9c1413f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4688383329304755663645206414547954120843287991395112713682168168761538772851 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4688383329304755663645206414547954120843287991395112713682168168761538772851
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device.17034868402969641932791694703767476671806089421659615019520662033550423921685
Short name T1858
Test name
Test status
Simulation time 2590995727 ps
CPU time 119.92 seconds
Started Nov 22 03:06:48 PM PST 23
Finished Nov 22 03:08:48 PM PST 23
Peak memory 554780 kb
Host smart-8a06cc09-9563-491e-9890-16f7d39e0e52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034868402969641932791694703767476671806089421659615019520662033550423921685 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.17034868402969641932791694703767476671806089421659615019520662033550423921685
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.26467184248875365951991572175242109492620210429342128075023274546394503890985
Short name T1843
Test name
Test status
Simulation time 115195295727 ps
CPU time 2025.54 seconds
Started Nov 22 03:06:43 PM PST 23
Finished Nov 22 03:40:30 PM PST 23
Peak memory 554808 kb
Host smart-afdc3628-d9e1-4853-994d-ae3859f010bf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26467184248875365951991572175242109492620210429342128075023274546394503890985 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.26467184248875365951991572175242109492620210429342128075023274546394503890985
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.58740416927882523869260082914378252145527140139388439748583717218785963715488
Short name T446
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.24 seconds
Started Nov 22 03:06:43 PM PST 23
Finished Nov 22 03:07:28 PM PST 23
Peak memory 553500 kb
Host smart-1caf01ea-0056-46c8-a998-f2c8da2b05c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58740416927882523869260082914378252145527140139388439748583717218785963715488 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.58740416927882523869260082914378252145527140139388439748583717218785963715488
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_random.31038706016545829167826817946643397600978142990248877931517124778570365425805
Short name T1049
Test name
Test status
Simulation time 2231375727 ps
CPU time 69.31 seconds
Started Nov 22 03:06:44 PM PST 23
Finished Nov 22 03:07:54 PM PST 23
Peak memory 553644 kb
Host smart-8b9d8f9d-afd7-47a0-8142-48096f69a317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31038706016545829167826817946643397600978142990248877931517124778570365425805 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 39.xbar_error_random.31038706016545829167826817946643397600978142990248877931517124778570365425805
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random.12178059263919008344027662483090459387425759547655024156246281159664823853317
Short name T1645
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.82 seconds
Started Nov 22 03:06:47 PM PST 23
Finished Nov 22 03:08:07 PM PST 23
Peak memory 553756 kb
Host smart-f7d652b1-7873-4ada-ba79-c129703ea623
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12178059263919008344027662483090459387425759547655024156246281159664823853317 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 39.xbar_random.12178059263919008344027662483090459387425759547655024156246281159664823853317
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.85532642182363994283252449980349528095207355179667940226950275545253820185494
Short name T565
Test name
Test status
Simulation time 97702135727 ps
CPU time 1135.03 seconds
Started Nov 22 03:06:45 PM PST 23
Finished Nov 22 03:25:41 PM PST 23
Peak memory 553668 kb
Host smart-a0e6121f-4fd3-40db-981f-32f64eb46eaf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85532642182363994283252449980349528095207355179667940226950275545253820185494 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.85532642182363994283252449980349528095207355179667940226950275545253820185494
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.71344844773150496184666388198281866060335582704571335067058139238908291474323
Short name T287
Test name
Test status
Simulation time 556965727 ps
CPU time 45.69 seconds
Started Nov 22 03:06:46 PM PST 23
Finished Nov 22 03:07:32 PM PST 23
Peak memory 553660 kb
Host smart-61c355ec-5bd6-4345-bf1c-a9bd417dcf30
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71344844773150496184666388198281866060335582704571335067058139238908291474323 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.71344844773150496184666388198281866060335582704571335067058139238908291474323
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_same_source.4089026408427527308727061386782676602349942880820111148124190374155083954039
Short name T402
Test name
Test status
Simulation time 2498784073 ps
CPU time 74.15 seconds
Started Nov 22 03:06:45 PM PST 23
Finished Nov 22 03:08:00 PM PST 23
Peak memory 553824 kb
Host smart-fd0bdb13-2d02-479f-b7a1-2c2363365129
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089026408427527308727061386782676602349942880820111148124190374155083954039 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.4089026408427527308727061386782676602349942880820111148124190374155083954039
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke.44450304626812398356644014965416590991926488615561514937817963656889339165289
Short name T1663
Test name
Test status
Simulation time 196985727 ps
CPU time 8.93 seconds
Started Nov 22 03:06:37 PM PST 23
Finished Nov 22 03:06:47 PM PST 23
Peak memory 552348 kb
Host smart-f9ff8718-25f1-4a96-bafb-c5cc0d880782
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44450304626812398356644014965416590991926488615561514937817963656889339165289 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 39.xbar_smoke.44450304626812398356644014965416590991926488615561514937817963656889339165289
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.31845395436987329168939171941022188827220634820044617768144264849589020769038
Short name T1774
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.75 seconds
Started Nov 22 03:06:37 PM PST 23
Finished Nov 22 03:08:11 PM PST 23
Peak memory 552304 kb
Host smart-676d02f8-442b-49e7-959c-da232a186359
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31845395436987329168939171941022188827220634820044617768144264849589020769038 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.31845395436987329168939171941022188827220634820044617768144264849589020769038
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.110727723528848481328374633456436746194837702378201582697781036665878669306539
Short name T1292
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.68 seconds
Started Nov 22 03:06:38 PM PST 23
Finished Nov 22 03:08:08 PM PST 23
Peak memory 552360 kb
Host smart-10cdf042-5487-4aac-9443-699960e5b777
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110727723528848481328374633456436746194837702378201582697781036665878669306539 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.110727723528848481328374633456436746194837702378201582697781036665878669306539
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.37867718312614904275963583932842248849059764964678894325668441481056225600262
Short name T559
Test name
Test status
Simulation time 45555727 ps
CPU time 5.87 seconds
Started Nov 22 03:06:45 PM PST 23
Finished Nov 22 03:06:52 PM PST 23
Peak memory 552316 kb
Host smart-e05626c0-4562-4109-8e6c-32bf6ffdea49
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37867718312614904275963583932842248849059764964678894325668441481056225600262 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.37867718312614904275963583932842248849059764964678894325668441481056225600262
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all.110742943040722480508172305582846309219568619982678809334650819468600567043695
Short name T819
Test name
Test status
Simulation time 13992004073 ps
CPU time 542.79 seconds
Started Nov 22 03:07:00 PM PST 23
Finished Nov 22 03:16:03 PM PST 23
Peak memory 555860 kb
Host smart-3d5071e7-a421-441e-afc1-6bbdf713ea95
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110742943040722480508172305582846309219568619982678809334650819468600567043695 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.110742943040722480508172305582846309219568619982678809334650819468600567043695
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.82467175160215153458675969061578509898089156467173724195724307066847970736962
Short name T795
Test name
Test status
Simulation time 13999524073 ps
CPU time 499.25 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:15:19 PM PST 23
Peak memory 555712 kb
Host smart-eadfc4ac-b534-4e5f-a236-2095a17876f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82467175160215153458675969061578509898089156467173724195724307066847970736962 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.82467175160215153458675969061578509898089156467173724195724307066847970736962
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.77035018277859696129551916239903268838970245144062315140104922123522783314465
Short name T294
Test name
Test status
Simulation time 4815189184 ps
CPU time 392.06 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:13:31 PM PST 23
Peak memory 557252 kb
Host smart-ebe5167c-a54f-41b1-b78a-578d5a3bb51f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77035018277859696129551916239903268838970245144062315140104922123522783314465 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.77035018277859696129551916239903268838970245144062315140104922
123522783314465
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.107905235984897302046035779561083106360763947866943847712053772885632968701529
Short name T1026
Test name
Test status
Simulation time 4815189184 ps
CPU time 316.96 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:12:17 PM PST 23
Peak memory 559716 kb
Host smart-5ae6da53-61fe-414b-a9d1-6ba2724045b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107905235984897302046035779561083106360763947866943847712053772885632968701529 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.10790523598489730204603577956108310636076394786694384771205
3772885632968701529
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.49500373121824159083795272105910474718855798862069287605950686292566435194829
Short name T1107
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.65 seconds
Started Nov 22 03:06:47 PM PST 23
Finished Nov 22 03:07:38 PM PST 23
Peak memory 553708 kb
Host smart-ce948487-3376-460f-9538-ccf212b73c98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49500373121824159083795272105910474718855798862069287605950686292566435194829 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.49500373121824159083795272105910474718855798862069287605950686292566435194829
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.70181632591394732787577837601289161721503618625530848169858343207865202439812
Short name T1127
Test name
Test status
Simulation time 72959944675 ps
CPU time 9802.28 seconds
Started Nov 22 03:03:31 PM PST 23
Finished Nov 22 05:46:55 PM PST 23
Peak memory 625244 kb
Host smart-b6d1c973-aa2b-4b1b-9725-a0d065350dd5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7018163259139473278757783760128916172150361862553
0848169858343207865202439812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_aliasing.701816325913947327875778376012891617215036186
25530848169858343207865202439812
Directory /workspace/4.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.99974328999536182375690183332928215599979711356259553298413712140063033045379
Short name T837
Test name
Test status
Simulation time 7954924257 ps
CPU time 698.06 seconds
Started Nov 22 03:03:29 PM PST 23
Finished Nov 22 03:15:08 PM PST 23
Peak memory 580504 kb
Host smart-77e5d731-c625-4235-8645-56d4f4cc801c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999743289995361823756901833329
28215599979711356259553298413712140063033045379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.99974328999536182375690183
332928215599979711356259553298413712140063033045379
Directory /workspace/4.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3705002965859158375563887834342926139139387229149001761563293905135383290092
Short name T11
Test name
Test status
Simulation time 5984936856 ps
CPU time 357.49 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:09:30 PM PST 23
Peak memory 641876 kb
Host smart-3d2f268a-76f8-49b1-93e6-9ec2709604c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705002965859158375563887834342926139139387229149001761563293905135383290092 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_reset.3705002965859158375563887834342926139139387229149001761563293905135383290092
Directory /workspace/4.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.16087227670687203101209247606022689098499952274313689882528469443301219658939
Short name T1245
Test name
Test status
Simulation time 7234930891 ps
CPU time 311.69 seconds
Started Nov 22 03:03:36 PM PST 23
Finished Nov 22 03:08:48 PM PST 23
Peak memory 622600 kb
Host smart-fb00fb6d-bb62-47d0-98c6-8a51d78c0eab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608722767068720310120924760602
2689098499952274313689882528469443301219658939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.1608722767068
7203101209247606022689098499952274313689882528469443301219658939
Directory /workspace/4.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_rw.18293110986677996587385684507472217087880241446110804510921051175393734288968
Short name T1652
Test name
Test status
Simulation time 5924944675 ps
CPU time 529.25 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:12:28 PM PST 23
Peak memory 580524 kb
Host smart-a7b2dba7-414f-4c97-9e21-349b405a7513
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18293110986677996587385684507472217087880241446110804510921051175393734288968 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.18293110986677996587385684507472217087880241446110804510921051175393734288968
Directory /workspace/4.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.62566183093942014843792510282077724380952270806724537480681047280089171919941
Short name T1443
Test name
Test status
Simulation time 30604932618 ps
CPU time 2996.95 seconds
Started Nov 22 03:03:24 PM PST 23
Finished Nov 22 03:53:22 PM PST 23
Peak memory 580548 kb
Host smart-90613a8d-6e8b-4ab7-b66b-ce58448dea08
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6256618309394201484379251028207772438
0952270806724537480681047280089171919941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.6256618309394201484379251
0282077724380952270806724537480681047280089171919941
Directory /workspace/4.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.chip_tl_errors.53731280967346155884508849854662790495729082106746229987119283215201433724643
Short name T1444
Test name
Test status
Simulation time 3069924257 ps
CPU time 178.41 seconds
Started Nov 22 03:03:28 PM PST 23
Finished Nov 22 03:06:27 PM PST 23
Peak memory 580464 kb
Host smart-5b68160e-86e4-417b-adbb-ec08469d947a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53731280967346155884508849854662790495729082106746229987119283215201433724643 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.53731280967346155884508849854662790495729082106746229987119283215201433724643
Directory /workspace/4.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device.11471713398053003635459230266690855800011731252235194301255934196389936553863
Short name T6
Test name
Test status
Simulation time 2590995727 ps
CPU time 113.25 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:05:37 PM PST 23
Peak memory 554788 kb
Host smart-6ec19246-d273-4c87-af8e-400cf8f6ac05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471713398053003635459230266690855800011731252235194301255934196389936553863 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.11471713398053003635459230266690855800011731252235194301255934196389936553863
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.48306108208482804345150741740805710692701479578259593873373900654390519531973
Short name T1744
Test name
Test status
Simulation time 115195295727 ps
CPU time 1969.82 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:36:28 PM PST 23
Peak memory 554788 kb
Host smart-69574b94-7868-43cf-b7ed-65feaa0cbb52
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48306108208482804345150741740805710692701479578259593873373900654390519531973 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.48306108208482804345150741740805710692701479578259593873373900654390519531973
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.59418612915027967481735420246959165321727564001995273809390627833969718180329
Short name T511
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.98 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:04:14 PM PST 23
Peak memory 553280 kb
Host smart-3ddf0e10-c614-494f-a87f-80edcd25c34f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59418612915027967481735420246959165321727564001995273809390627833969718180329 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.59418612915027967481735420246959165321727564001995273809390627833969718180329
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_random.110483399719453494640364045648799392654413989498775167988362348376242649317742
Short name T1089
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.38 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:04:55 PM PST 23
Peak memory 553500 kb
Host smart-3acfc11a-37a6-451e-a52c-e1c83558e4de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110483399719453494640364045648799392654413989498775167988362348376242649317742 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.xbar_error_random.110483399719453494640364045648799392654413989498775167988362348376242649317742
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random.53021422408461002281560191946861263407985872703296445475081749950637018240122
Short name T1459
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.68 seconds
Started Nov 22 03:03:36 PM PST 23
Finished Nov 22 03:04:53 PM PST 23
Peak memory 553804 kb
Host smart-83ed2a1b-685f-4bc2-a3d0-aad63220639f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53021422408461002281560191946861263407985872703296445475081749950637018240122 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.xbar_random.53021422408461002281560191946861263407985872703296445475081749950637018240122
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.61915412484335701625648319889161725672661085564834006075015267285179702623329
Short name T1305
Test name
Test status
Simulation time 97702135727 ps
CPU time 1161.2 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:23:06 PM PST 23
Peak memory 553548 kb
Host smart-fcd18ef7-0b57-463c-ab76-0ed96b017545
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61915412484335701625648319889161725672661085564834006075015267285179702623329 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.61915412484335701625648319889161725672661085564834006075015267285179702623329
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.105928749703977489609366317271351475301518702590845573846555559272011019124771
Short name T1337
Test name
Test status
Simulation time 60576345727 ps
CPU time 1105.56 seconds
Started Nov 22 03:03:27 PM PST 23
Finished Nov 22 03:21:53 PM PST 23
Peak memory 553700 kb
Host smart-577f3114-10b1-438b-a07c-6d4351b90d49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105928749703977489609366317271351475301518702590845573846555559272011019124771 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.105928749703977489609366317271351475301518702590845573846555559272011019124771
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.49338830716230897960860680305890115129092215218716555744442433041399539660528
Short name T994
Test name
Test status
Simulation time 556965727 ps
CPU time 47.87 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:04:30 PM PST 23
Peak memory 553760 kb
Host smart-4db2ed05-0b09-4472-82a7-ac3e18af3c90
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49338830716230897960860680305890115129092215218716555744442433041399539660528 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.49338830716230897960860680305890115129092215218716555744442433041399539660528
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_same_source.111658971275532705799108798633101201389100629408896376362446142905866807772778
Short name T125
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.33 seconds
Started Nov 22 03:03:35 PM PST 23
Finished Nov 22 03:04:47 PM PST 23
Peak memory 553536 kb
Host smart-b1923b57-a1fa-4ef3-a866-afe62208036b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111658971275532705799108798633101201389100629408896376362446142905866807772778 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.111658971275532705799108798633101201389100629408896376362446142905866807772778
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke.58035671661550412648663297349095441375015525067334907073315697744781291762613
Short name T840
Test name
Test status
Simulation time 196985727 ps
CPU time 8.15 seconds
Started Nov 22 03:03:39 PM PST 23
Finished Nov 22 03:03:47 PM PST 23
Peak memory 552364 kb
Host smart-b3767705-f019-4358-8536-0b13be5aa547
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58035671661550412648663297349095441375015525067334907073315697744781291762613 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.xbar_smoke.58035671661550412648663297349095441375015525067334907073315697744781291762613
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.10834519657157038267001174755054956739597780558036420199947253813932264301504
Short name T718
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.23 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:05:10 PM PST 23
Peak memory 552388 kb
Host smart-a9660d97-5560-455b-be5f-151de8c79eda
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10834519657157038267001174755054956739597780558036420199947253813932264301504 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.10834519657157038267001174755054956739597780558036420199947253813932264301504
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.50658031557874457035149804520204429186869701198875137047154447328305106092450
Short name T1261
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.54 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:05:03 PM PST 23
Peak memory 552412 kb
Host smart-5e9a8de1-1eed-4cdb-87c5-4acecf68df8f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50658031557874457035149804520204429186869701198875137047154447328305106092450 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.50658031557874457035149804520204429186869701198875137047154447328305106092450
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.86127721978113769370653973635197525448167352820196712469975420988380776797390
Short name T955
Test name
Test status
Simulation time 45555727 ps
CPU time 5.67 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:03:36 PM PST 23
Peak memory 552316 kb
Host smart-84e8ac8d-2185-4a9b-8ab5-5d05f04f4a5b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86127721978113769370653973635197525448167352820196712469975420988380776797390 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.86127721978113769370653973635197525448167352820196712469975420988380776797390
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all.101366194320800516407638904698123868862966230770326331486828732825596824140555
Short name T1342
Test name
Test status
Simulation time 13992004073 ps
CPU time 556.7 seconds
Started Nov 22 03:03:51 PM PST 23
Finished Nov 22 03:13:08 PM PST 23
Peak memory 555900 kb
Host smart-1471bd22-5b86-48e2-a876-d8f4a12754bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101366194320800516407638904698123868862966230770326331486828732825596824140555 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.101366194320800516407638904698123868862966230770326331486828732825596824140555
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.111125381442971706966486877638536420109419873433843559712367362109557348386604
Short name T297
Test name
Test status
Simulation time 13999524073 ps
CPU time 480.47 seconds
Started Nov 22 03:03:31 PM PST 23
Finished Nov 22 03:11:33 PM PST 23
Peak memory 555796 kb
Host smart-b4397405-0f68-4ebd-9a33-1f4da96cdabe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111125381442971706966486877638536420109419873433843559712367362109557348386604 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.111125381442971706966486877638536420109419873433843559712367362109557348386604
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.73907369931799369684943373265713775575735252039407142356826863828524121603223
Short name T485
Test name
Test status
Simulation time 4815189184 ps
CPU time 380.74 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:09:55 PM PST 23
Peak memory 557264 kb
Host smart-cacf7173-fa3c-4026-ba02-4bbae8530e2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73907369931799369684943373265713775575735252039407142356826863828524121603223 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.739073699317993696849433732657137755757352520394071423568268638
28524121603223
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.48125601098022192938989757325198449494418308454139129009657484235890205728174
Short name T726
Test name
Test status
Simulation time 4815189184 ps
CPU time 302.79 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:08:40 PM PST 23
Peak memory 559804 kb
Host smart-b967f280-d22b-45cf-80cd-e5c609965fcc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48125601098022192938989757325198449494418308454139129009657484235890205728174 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.4812560109802219293898975732519844949441830845413912900965748
4235890205728174
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.62598322587773024756472701258302269556481797635004258293106457206067275928874
Short name T1541
Test name
Test status
Simulation time 1176995727 ps
CPU time 44.57 seconds
Started Nov 22 03:03:35 PM PST 23
Finished Nov 22 03:04:20 PM PST 23
Peak memory 553732 kb
Host smart-91ed7e63-71cc-475e-9f86-6f64249fa258
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62598322587773024756472701258302269556481797635004258293106457206067275928874 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.62598322587773024756472701258302269556481797635004258293106457206067275928874
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device.17816793959226578943040521525617514993267345341012104423382770349144647044979
Short name T707
Test name
Test status
Simulation time 2590995727 ps
CPU time 118.56 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:08:59 PM PST 23
Peak memory 554792 kb
Host smart-5d061c84-5a96-4b8c-b723-d287e88ffa70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17816793959226578943040521525617514993267345341012104423382770349144647044979 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.17816793959226578943040521525617514993267345341012104423382770349144647044979
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.80542314095510868747388250964986476534257937471026834389052404668403345377890
Short name T1565
Test name
Test status
Simulation time 115195295727 ps
CPU time 2072.44 seconds
Started Nov 22 03:07:02 PM PST 23
Finished Nov 22 03:41:35 PM PST 23
Peak memory 554700 kb
Host smart-6f4853f4-e081-4bf3-995b-80d1b1171fec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80542314095510868747388250964986476534257937471026834389052404668403345377890 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.80542314095510868747388250964986476534257937471026834389052404668403345377890
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.102464247445105940638004557100754155795824009856867152988851206351138033299830
Short name T90
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.48 seconds
Started Nov 22 03:07:00 PM PST 23
Finished Nov 22 03:07:48 PM PST 23
Peak memory 553488 kb
Host smart-1aaa9ce4-3a65-4bbb-8f08-c33503636c44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102464247445105940638004557100754155795824009856867152988851206351138033299830 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.102464247445105940638004557100754155795824009856867152988851206351138033299830
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_random.65321159908475821876806999948986784750679061887376288263344614045666705366340
Short name T699
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.49 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:08:19 PM PST 23
Peak memory 553564 kb
Host smart-9b20d2ae-baaf-49fb-906d-d89d9d370983
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65321159908475821876806999948986784750679061887376288263344614045666705366340 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 40.xbar_error_random.65321159908475821876806999948986784750679061887376288263344614045666705366340
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random.45965912968418066966603485228677738624391885574258509650613831450595392366004
Short name T816
Test name
Test status
Simulation time 2231375727 ps
CPU time 83.12 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:08:23 PM PST 23
Peak memory 553852 kb
Host smart-766bd047-1b40-4367-ba77-31eb62a9cc8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45965912968418066966603485228677738624391885574258509650613831450595392366004 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 40.xbar_random.45965912968418066966603485228677738624391885574258509650613831450595392366004
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3180460895483511057582954575082665148181186678000232087592448211815479055051
Short name T1128
Test name
Test status
Simulation time 97702135727 ps
CPU time 1175.83 seconds
Started Nov 22 03:07:01 PM PST 23
Finished Nov 22 03:26:37 PM PST 23
Peak memory 553592 kb
Host smart-ffb05063-b27e-40a0-a1a5-c0b3cc79c8e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180460895483511057582954575082665148181186678000232087592448211815479055051 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3180460895483511057582954575082665148181186678000232087592448211815479055051
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.11444254918809150259021394868201776475451960594125991893986980580589503583128
Short name T1176
Test name
Test status
Simulation time 60576345727 ps
CPU time 1113.2 seconds
Started Nov 22 03:07:03 PM PST 23
Finished Nov 22 03:25:37 PM PST 23
Peak memory 553724 kb
Host smart-311aac09-d617-489b-b854-4816d80accc3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11444254918809150259021394868201776475451960594125991893986980580589503583128 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.11444254918809150259021394868201776475451960594125991893986980580589503583128
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1530652610196481853999525764605820467065217863497780201471374205594191563664
Short name T1198
Test name
Test status
Simulation time 556965727 ps
CPU time 49.59 seconds
Started Nov 22 03:07:03 PM PST 23
Finished Nov 22 03:07:53 PM PST 23
Peak memory 553716 kb
Host smart-691ca02d-dfb5-458c-a198-a68fe61c85d8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530652610196481853999525764605820467065217863497780201471374205594191563664 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1530652610196481853999525764605820467065217863497780201471374205594191563664
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_same_source.111601114861747655566404359639070207612817970959198780848755925768117976806939
Short name T848
Test name
Test status
Simulation time 2498784073 ps
CPU time 74.85 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:08:14 PM PST 23
Peak memory 553728 kb
Host smart-1a1fe9f3-dbd6-4104-afad-ca5bedfc71bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111601114861747655566404359639070207612817970959198780848755925768117976806939 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.111601114861747655566404359639070207612817970959198780848755925768117976806939
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke.37418583046810244662181210797650118637406601758442200406588228111708131248982
Short name T1133
Test name
Test status
Simulation time 196985727 ps
CPU time 8.25 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:07:08 PM PST 23
Peak memory 552384 kb
Host smart-299fd872-bfa0-4fc0-9634-b50b6cef221e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418583046810244662181210797650118637406601758442200406588228111708131248982 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 40.xbar_smoke.37418583046810244662181210797650118637406601758442200406588228111708131248982
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.40170515140167680015783599585429303241563552649075501715751758043380856568762
Short name T1798
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.25 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:08:32 PM PST 23
Peak memory 552316 kb
Host smart-6ad64db5-5319-4cd7-a357-cf471ccd2c45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40170515140167680015783599585429303241563552649075501715751758043380856568762 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.40170515140167680015783599585429303241563552649075501715751758043380856568762
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.93461065088952580866700301885079757929311914223822444064800834099919983026246
Short name T742
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.92 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:08:30 PM PST 23
Peak memory 552400 kb
Host smart-24af9795-f0f9-4fcf-be20-7ea846939ed5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93461065088952580866700301885079757929311914223822444064800834099919983026246 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.93461065088952580866700301885079757929311914223822444064800834099919983026246
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.108961647506500302564337783153345344806663828963249868662546905250393449204096
Short name T656
Test name
Test status
Simulation time 45555727 ps
CPU time 6.48 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:07:06 PM PST 23
Peak memory 552336 kb
Host smart-b23ac541-1f45-4912-b9fe-350368ee70fa
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108961647506500302564337783153345344806663828963249868662546905250393449204096 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.108961647506500302564337783153345344806663828963249868662546905250393449204096
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all.51896779805999329573852384019413909012604356900145991680083389114811926923437
Short name T637
Test name
Test status
Simulation time 13992004073 ps
CPU time 524.19 seconds
Started Nov 22 03:06:57 PM PST 23
Finished Nov 22 03:15:42 PM PST 23
Peak memory 555940 kb
Host smart-20908614-2353-4759-82ff-bbe8678afc8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51896779805999329573852384019413909012604356900145991680083389114811926923437 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.51896779805999329573852384019413909012604356900145991680083389114811926923437
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.51696377067945132877876264946705064727396995853412309044295286102977966768371
Short name T882
Test name
Test status
Simulation time 13999524073 ps
CPU time 470.73 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:14:49 PM PST 23
Peak memory 555700 kb
Host smart-a52e0c41-f1bb-4f38-82a9-be883d1ec4f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51696377067945132877876264946705064727396995853412309044295286102977966768371 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.51696377067945132877876264946705064727396995853412309044295286102977966768371
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.29879124150281795926893272021056209722750360151553405290830135989981882735151
Short name T1039
Test name
Test status
Simulation time 4815189184 ps
CPU time 405.38 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:13:44 PM PST 23
Peak memory 557232 kb
Host smart-1ad66e9f-03a5-4dd2-941a-3bd96636bddb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29879124150281795926893272021056209722750360151553405290830135989981882735151 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.29879124150281795926893272021056209722750360151553405290830135
989981882735151
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.103534428534621130778467768984518032161977393927347801659590203074537935446642
Short name T526
Test name
Test status
Simulation time 4815189184 ps
CPU time 320.35 seconds
Started Nov 22 03:07:03 PM PST 23
Finished Nov 22 03:12:24 PM PST 23
Peak memory 559772 kb
Host smart-1ccaf4e1-4012-4a25-8bfd-dc58bea28827
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103534428534621130778467768984518032161977393927347801659590203074537935446642 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.10353442853462113077846776898451803216197739392734780165959
0203074537935446642
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.13604598313765588832553347186585266113079947107657068463542783369964393704583
Short name T381
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.66 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:07:48 PM PST 23
Peak memory 553668 kb
Host smart-c614cba9-b8a6-405e-8787-7336b85dfb11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13604598313765588832553347186585266113079947107657068463542783369964393704583 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.13604598313765588832553347186585266113079947107657068463542783369964393704583
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device.111203661020241763106415856408924326690166461725362883836277174446455881894589
Short name T1188
Test name
Test status
Simulation time 2590995727 ps
CPU time 121.5 seconds
Started Nov 22 03:07:04 PM PST 23
Finished Nov 22 03:09:06 PM PST 23
Peak memory 554912 kb
Host smart-2c183d5c-8bb3-4079-b475-bdfe6d8e2b83
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111203661020241763106415856408924326690166461725362883836277174446455881894589 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.111203661020241763106415856408924326690166461725362883836277174446455881894589
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.72675698626430219911210575827779907845157033090979613030423019354159872485982
Short name T900
Test name
Test status
Simulation time 115195295727 ps
CPU time 2000.79 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:40:21 PM PST 23
Peak memory 554692 kb
Host smart-af14dcb3-d3fa-4a4c-bc7c-fdc5aa4212b7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72675698626430219911210575827779907845157033090979613030423019354159872485982 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.72675698626430219911210575827779907845157033090979613030423019354159872485982
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.91468821700181777695157313230946833818932629822545809004569697583102364525125
Short name T753
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.13 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:08:00 PM PST 23
Peak memory 553484 kb
Host smart-c474b0e4-d69f-42e9-bed4-e15b266a16c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91468821700181777695157313230946833818932629822545809004569697583102364525125 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.91468821700181777695157313230946833818932629822545809004569697583102364525125
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_random.31551316240216625512624541935216156937112672277096077476097545878790620740896
Short name T951
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.09 seconds
Started Nov 22 03:07:10 PM PST 23
Finished Nov 22 03:08:23 PM PST 23
Peak memory 553516 kb
Host smart-83733716-ad37-4dca-9cb8-0aab28d6e03b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31551316240216625512624541935216156937112672277096077476097545878790620740896 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 41.xbar_error_random.31551316240216625512624541935216156937112672277096077476097545878790620740896
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random.105262675829908375416026391996760979804167080660245341429804299416080519816080
Short name T1405
Test name
Test status
Simulation time 2231375727 ps
CPU time 81 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:08:21 PM PST 23
Peak memory 553664 kb
Host smart-74c5c356-4dcb-4438-9f8a-3b18a035682b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105262675829908375416026391996760979804167080660245341429804299416080519816080 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 41.xbar_random.105262675829908375416026391996760979804167080660245341429804299416080519816080
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.57034103674639622915667100218655924565252544410762145042121158601114235361872
Short name T369
Test name
Test status
Simulation time 97702135727 ps
CPU time 1148.19 seconds
Started Nov 22 03:06:57 PM PST 23
Finished Nov 22 03:26:06 PM PST 23
Peak memory 553632 kb
Host smart-399a9a1e-1f5f-4314-9315-39efac7532bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57034103674639622915667100218655924565252544410762145042121158601114235361872 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.57034103674639622915667100218655924565252544410762145042121158601114235361872
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.67101365037919644912044748939419217652155153224498129834363459009432012388544
Short name T199
Test name
Test status
Simulation time 60576345727 ps
CPU time 1083.77 seconds
Started Nov 22 03:07:04 PM PST 23
Finished Nov 22 03:25:08 PM PST 23
Peak memory 553700 kb
Host smart-7dd4de65-2459-4194-bd89-24f35e536bc6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67101365037919644912044748939419217652155153224498129834363459009432012388544 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.67101365037919644912044748939419217652155153224498129834363459009432012388544
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.51758666664545131470613990557266777817339032524881761579412053669033129634982
Short name T331
Test name
Test status
Simulation time 556965727 ps
CPU time 47.12 seconds
Started Nov 22 03:07:04 PM PST 23
Finished Nov 22 03:07:51 PM PST 23
Peak memory 553824 kb
Host smart-f1f346c0-2dc1-4642-87fb-698cca5b1c4a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51758666664545131470613990557266777817339032524881761579412053669033129634982 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.51758666664545131470613990557266777817339032524881761579412053669033129634982
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_same_source.41378197481016734208150749883340782909260145488933068729017758349091482737441
Short name T660
Test name
Test status
Simulation time 2498784073 ps
CPU time 78.59 seconds
Started Nov 22 03:07:19 PM PST 23
Finished Nov 22 03:08:38 PM PST 23
Peak memory 553720 kb
Host smart-642ebe30-fdbe-4131-bb67-bdb23359668f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41378197481016734208150749883340782909260145488933068729017758349091482737441 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.41378197481016734208150749883340782909260145488933068729017758349091482737441
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke.4524499703308358874403321554501577699657323899162771095049383329245675284355
Short name T990
Test name
Test status
Simulation time 196985727 ps
CPU time 9.19 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:07:09 PM PST 23
Peak memory 552464 kb
Host smart-4c0326d5-b695-4d3b-99b1-1a3efe0c7ba0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4524499703308358874403321554501577699657323899162771095049383329245675284355 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 41.xbar_smoke.4524499703308358874403321554501577699657323899162771095049383329245675284355
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.74988668445011352685033964836987174505085555415651221953080629848673154046009
Short name T427
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.34 seconds
Started Nov 22 03:06:59 PM PST 23
Finished Nov 22 03:08:30 PM PST 23
Peak memory 552392 kb
Host smart-c2e29056-1869-46b4-80fe-e6e3c0113049
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74988668445011352685033964836987174505085555415651221953080629848673154046009 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.74988668445011352685033964836987174505085555415651221953080629848673154046009
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.41354066980514026215953026719771876978179066720814150619226641429812984619053
Short name T450
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.32 seconds
Started Nov 22 03:07:01 PM PST 23
Finished Nov 22 03:08:32 PM PST 23
Peak memory 552388 kb
Host smart-0e16410c-f4dc-4c53-ae20-0116e341c574
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41354066980514026215953026719771876978179066720814150619226641429812984619053 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.41354066980514026215953026719771876978179066720814150619226641429812984619053
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.72598666296961904440209695711930321050312707557504006000214009262456766846405
Short name T572
Test name
Test status
Simulation time 45555727 ps
CPU time 5.74 seconds
Started Nov 22 03:06:58 PM PST 23
Finished Nov 22 03:07:05 PM PST 23
Peak memory 552328 kb
Host smart-e11d3aeb-11ba-46a2-a52d-d792d6218496
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72598666296961904440209695711930321050312707557504006000214009262456766846405 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.72598666296961904440209695711930321050312707557504006000214009262456766846405
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all.77501108050309016918036995463173478663613756723796290432903483911004704989210
Short name T303
Test name
Test status
Simulation time 13992004073 ps
CPU time 554.63 seconds
Started Nov 22 03:07:11 PM PST 23
Finished Nov 22 03:16:27 PM PST 23
Peak memory 555724 kb
Host smart-f2a3cd4d-014e-4529-aec6-bf829c565cb5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77501108050309016918036995463173478663613756723796290432903483911004704989210 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.77501108050309016918036995463173478663613756723796290432903483911004704989210
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.27898073336057277825476825660370674486620560428667221242877181896014206840174
Short name T504
Test name
Test status
Simulation time 13999524073 ps
CPU time 470.17 seconds
Started Nov 22 03:07:13 PM PST 23
Finished Nov 22 03:15:04 PM PST 23
Peak memory 555704 kb
Host smart-be340080-a2f3-41ff-a3a5-f2871631b7b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27898073336057277825476825660370674486620560428667221242877181896014206840174 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.27898073336057277825476825660370674486620560428667221242877181896014206840174
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.34586546227890069467919147579671146712703848415377800603604426718365459149290
Short name T21
Test name
Test status
Simulation time 4815189184 ps
CPU time 367.33 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:13:20 PM PST 23
Peak memory 557196 kb
Host smart-ef11a633-c700-458f-b9a0-ee51473243f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586546227890069467919147579671146712703848415377800603604426718365459149290 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.34586546227890069467919147579671146712703848415377800603604426
718365459149290
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.47677969498971249448070196408087762413093295805335702075212413241162304375209
Short name T1304
Test name
Test status
Simulation time 4815189184 ps
CPU time 323.29 seconds
Started Nov 22 03:07:10 PM PST 23
Finished Nov 22 03:12:34 PM PST 23
Peak memory 559696 kb
Host smart-a0c102dd-eb7a-43ba-a655-3814f3097ae3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47677969498971249448070196408087762413093295805335702075212413241162304375209 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.476779694989712494480701964080877624130932958053357020752124
13241162304375209
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.110688720271216209929630761990479306142255922837661491914342059304193798366228
Short name T1590
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.27 seconds
Started Nov 22 03:07:13 PM PST 23
Finished Nov 22 03:08:02 PM PST 23
Peak memory 553656 kb
Host smart-f79395a4-3c10-48c2-a928-c9772b39e389
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110688720271216209929630761990479306142255922837661491914342059304193798366228 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.110688720271216209929630761990479306142255922837661491914342059304193798366228
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device.71785349419312608869772282181151414228632181408997799570886650614620231567793
Short name T1487
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.26 seconds
Started Nov 22 03:07:14 PM PST 23
Finished Nov 22 03:09:02 PM PST 23
Peak memory 554792 kb
Host smart-6797e60a-db28-4e54-b965-fb359489b44d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71785349419312608869772282181151414228632181408997799570886650614620231567793 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.71785349419312608869772282181151414228632181408997799570886650614620231567793
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.102482238460686408532990521592378687627273028863115899657580206009298029176461
Short name T1482
Test name
Test status
Simulation time 115195295727 ps
CPU time 2092.85 seconds
Started Nov 22 03:07:10 PM PST 23
Finished Nov 22 03:42:03 PM PST 23
Peak memory 554748 kb
Host smart-e4c40483-ece9-4fdc-8329-4da146d01cb4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102482238460686408532990521592378687627273028863115899657580206009298029176461 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.102482238460686408532990521592378687627273028863115899657580206009298029176461
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.112108037202955322463091992495182729396334541899473164399668528867624974896102
Short name T165
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.88 seconds
Started Nov 22 03:07:21 PM PST 23
Finished Nov 22 03:08:04 PM PST 23
Peak memory 553468 kb
Host smart-6526b677-d110-44d4-bbdd-97784aa3cb5d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112108037202955322463091992495182729396334541899473164399668528867624974896102 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.112108037202955322463091992495182729396334541899473164399668528867624974896102
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_random.561015692089722726626318827084050309954664154057843667757467298162477983574
Short name T1732
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.76 seconds
Started Nov 22 03:07:13 PM PST 23
Finished Nov 22 03:08:26 PM PST 23
Peak memory 553496 kb
Host smart-2b8df529-287f-4184-85e8-6ad4288a93a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561015692089722726626318827084050309954664154057843667757467298162477983574 -assert nopostproc +UVM_T
ESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 42.xbar_error_random.561015692089722726626318827084050309954664154057843667757467298162477983574
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random.29191091541201142807817873309052466907085416512700805471109271350472323029157
Short name T1171
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.09 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:08:27 PM PST 23
Peak memory 553784 kb
Host smart-bb986690-2469-4b36-90f8-ea6fb71d8c57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29191091541201142807817873309052466907085416512700805471109271350472323029157 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 42.xbar_random.29191091541201142807817873309052466907085416512700805471109271350472323029157
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.981156697015380913681745758697173442377488479095401873906193994426521426549
Short name T286
Test name
Test status
Simulation time 97702135727 ps
CPU time 1150.32 seconds
Started Nov 22 03:07:11 PM PST 23
Finished Nov 22 03:26:22 PM PST 23
Peak memory 553484 kb
Host smart-374a0b8e-8d50-4f58-b178-d140ca68bac5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981156697015380913681745758697173442377488479095401873906193994426521426549 -assert nopostp
roc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.981156697015380913681745758697173442377488479095401873906193994426521426549
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.64657231737218917432977134553394702557485458521457832438927756498516269461655
Short name T356
Test name
Test status
Simulation time 60576345727 ps
CPU time 1113.69 seconds
Started Nov 22 03:07:13 PM PST 23
Finished Nov 22 03:25:48 PM PST 23
Peak memory 553728 kb
Host smart-b75ecdd5-b478-4722-82cb-6ed27763ff15
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64657231737218917432977134553394702557485458521457832438927756498516269461655 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.64657231737218917432977134553394702557485458521457832438927756498516269461655
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.106707302949840973507323739406118963916773803516851377440609573339646802842568
Short name T1813
Test name
Test status
Simulation time 556965727 ps
CPU time 46.63 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:07:59 PM PST 23
Peak memory 553676 kb
Host smart-75667dbb-0079-47fc-a12a-d415b7e45323
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106707302949840973507323739406118963916773803516851377440609573339646802842568 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.106707302949840973507323739406118963916773803516851377440609573339646802842568
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_same_source.85063087978924574659502921044554253386530837799314637500856118339982896358341
Short name T696
Test name
Test status
Simulation time 2498784073 ps
CPU time 79.94 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:08:33 PM PST 23
Peak memory 553832 kb
Host smart-141c9b80-aa6a-40b6-a01c-09f1f0ba8a5d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85063087978924574659502921044554253386530837799314637500856118339982896358341 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.85063087978924574659502921044554253386530837799314637500856118339982896358341
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke.55018516940099208921652095305970762705540024843262195721296385484552404365687
Short name T576
Test name
Test status
Simulation time 196985727 ps
CPU time 8.48 seconds
Started Nov 22 03:07:13 PM PST 23
Finished Nov 22 03:07:22 PM PST 23
Peak memory 552380 kb
Host smart-93623828-e873-4bb5-aff2-db1985546b84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55018516940099208921652095305970762705540024843262195721296385484552404365687 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 42.xbar_smoke.55018516940099208921652095305970762705540024843262195721296385484552404365687
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.107689739383659065990556981790996285663843178277448300229560923952353846339219
Short name T225
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.11 seconds
Started Nov 22 03:07:10 PM PST 23
Finished Nov 22 03:08:42 PM PST 23
Peak memory 552376 kb
Host smart-c0bcd33d-deb8-467a-9922-e737684313b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107689739383659065990556981790996285663843178277448300229560923952353846339219 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.107689739383659065990556981790996285663843178277448300229560923952353846339219
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.78666756538360630867362145071400655478605529922889436317342409982330686087335
Short name T100
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.23 seconds
Started Nov 22 03:07:14 PM PST 23
Finished Nov 22 03:08:42 PM PST 23
Peak memory 552344 kb
Host smart-4bd7710f-876e-4ebc-9f8f-eea0b0ce8dd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78666756538360630867362145071400655478605529922889436317342409982330686087335 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.78666756538360630867362145071400655478605529922889436317342409982330686087335
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.38234763035832688277922150054892813917674344424166194417065453542589141622528
Short name T455
Test name
Test status
Simulation time 45555727 ps
CPU time 6.1 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:07:19 PM PST 23
Peak memory 552288 kb
Host smart-1da95420-fa0b-4928-92f2-1b63db9d3619
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38234763035832688277922150054892813917674344424166194417065453542589141622528 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.38234763035832688277922150054892813917674344424166194417065453542589141622528
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all.35214535361269679789185949724390572139204152324022559784981435368898741041166
Short name T1184
Test name
Test status
Simulation time 13992004073 ps
CPU time 516.14 seconds
Started Nov 22 03:07:16 PM PST 23
Finished Nov 22 03:15:52 PM PST 23
Peak memory 555912 kb
Host smart-c399ed10-9c7a-42a5-b10f-e0f72ff4eb79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35214535361269679789185949724390572139204152324022559784981435368898741041166 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.35214535361269679789185949724390572139204152324022559784981435368898741041166
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.96118496377137591547738553287921568570119841512667178642509918531281029983529
Short name T202
Test name
Test status
Simulation time 13999524073 ps
CPU time 452.29 seconds
Started Nov 22 03:07:20 PM PST 23
Finished Nov 22 03:14:53 PM PST 23
Peak memory 555720 kb
Host smart-4c8b3dc5-5cc3-49f6-b353-09060660b13c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96118496377137591547738553287921568570119841512667178642509918531281029983529 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.96118496377137591547738553287921568570119841512667178642509918531281029983529
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.52411241035377979121659899792908824621428079287519972928425142111586734006528
Short name T487
Test name
Test status
Simulation time 4815189184 ps
CPU time 377.15 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:13:29 PM PST 23
Peak memory 557216 kb
Host smart-91d5ef27-eeac-4c61-a7ee-bd0f70b2038d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52411241035377979121659899792908824621428079287519972928425142111586734006528 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.52411241035377979121659899792908824621428079287519972928425142
111586734006528
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.52107426400479280994643533372336296021884529579220057120208102902008125295327
Short name T1502
Test name
Test status
Simulation time 4815189184 ps
CPU time 312.61 seconds
Started Nov 22 03:07:14 PM PST 23
Finished Nov 22 03:12:28 PM PST 23
Peak memory 559732 kb
Host smart-73ef217b-ae7c-4086-ae73-b6add059b949
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52107426400479280994643533372336296021884529579220057120208102902008125295327 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.521074264004792809946435333723362960218845295792200571202081
02902008125295327
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.51248504508401875490551961542278194551507211775055806799789218833276416102798
Short name T1022
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.65 seconds
Started Nov 22 03:07:11 PM PST 23
Finished Nov 22 03:08:01 PM PST 23
Peak memory 553736 kb
Host smart-df1bc62e-0b68-4864-a018-cb61f93c10ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51248504508401875490551961542278194551507211775055806799789218833276416102798 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.51248504508401875490551961542278194551507211775055806799789218833276416102798
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device.15143564954523975640342396874851586577870448659190381104908918520521221288262
Short name T1684
Test name
Test status
Simulation time 2590995727 ps
CPU time 123.07 seconds
Started Nov 22 03:07:16 PM PST 23
Finished Nov 22 03:09:20 PM PST 23
Peak memory 554800 kb
Host smart-d4a13859-13ab-4320-a128-1bd834fc95fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15143564954523975640342396874851586577870448659190381104908918520521221288262 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.15143564954523975640342396874851586577870448659190381104908918520521221288262
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.97760424551286384011601266447376557447886582644823643531301757228131853578320
Short name T561
Test name
Test status
Simulation time 115195295727 ps
CPU time 2025.12 seconds
Started Nov 22 03:07:25 PM PST 23
Finished Nov 22 03:41:12 PM PST 23
Peak memory 554780 kb
Host smart-1f39a210-83b8-417c-8c83-abd914c6127a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97760424551286384011601266447376557447886582644823643531301757228131853578320 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.97760424551286384011601266447376557447886582644823643531301757228131853578320
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.115072677043837883358180541985327615048974850502183618662919926433615566405342
Short name T1845
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.74 seconds
Started Nov 22 03:07:24 PM PST 23
Finished Nov 22 03:08:13 PM PST 23
Peak memory 553480 kb
Host smart-e2615284-6aee-43e1-81d9-cca4365b044e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115072677043837883358180541985327615048974850502183618662919926433615566405342 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.115072677043837883358180541985327615048974850502183618662919926433615566405342
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_random.115529395207756933767065091281476207267176595175545347023842716376171381203130
Short name T1898
Test name
Test status
Simulation time 2231375727 ps
CPU time 68.4 seconds
Started Nov 22 03:07:22 PM PST 23
Finished Nov 22 03:08:35 PM PST 23
Peak memory 553508 kb
Host smart-c3a25260-ecf7-4097-99ad-00fa2df7e370
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115529395207756933767065091281476207267176595175545347023842716376171381203130 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 43.xbar_error_random.115529395207756933767065091281476207267176595175545347023842716376171381203130
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random.70429467164627539017153547372322689375816608865103819172794152681473446182422
Short name T1361
Test name
Test status
Simulation time 2231375727 ps
CPU time 71 seconds
Started Nov 22 03:07:20 PM PST 23
Finished Nov 22 03:08:32 PM PST 23
Peak memory 553780 kb
Host smart-851fe188-bb8e-432a-b118-e678dcc1db1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70429467164627539017153547372322689375816608865103819172794152681473446182422 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 43.xbar_random.70429467164627539017153547372322689375816608865103819172794152681473446182422
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.11197430775901441472831711991177417611914349502682781282212041129224919985954
Short name T1465
Test name
Test status
Simulation time 97702135727 ps
CPU time 1172.11 seconds
Started Nov 22 03:07:25 PM PST 23
Finished Nov 22 03:26:59 PM PST 23
Peak memory 553664 kb
Host smart-4504d487-44ad-4649-95c5-a5a71bd284de
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197430775901441472831711991177417611914349502682781282212041129224919985954 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.11197430775901441472831711991177417611914349502682781282212041129224919985954
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.76787996299975009806199903188260706596268221743788468534553821049673255823478
Short name T222
Test name
Test status
Simulation time 60576345727 ps
CPU time 1018.88 seconds
Started Nov 22 03:07:20 PM PST 23
Finished Nov 22 03:24:19 PM PST 23
Peak memory 553732 kb
Host smart-95074854-aacf-4d19-bbe2-dce09d900bf7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76787996299975009806199903188260706596268221743788468534553821049673255823478 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.76787996299975009806199903188260706596268221743788468534553821049673255823478
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.61173596180672345789803202385347452648505636561683162429807084034083676343500
Short name T476
Test name
Test status
Simulation time 556965727 ps
CPU time 46.74 seconds
Started Nov 22 03:07:25 PM PST 23
Finished Nov 22 03:08:13 PM PST 23
Peak memory 553708 kb
Host smart-d963fd24-48e0-41aa-830f-747d7d9d880b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61173596180672345789803202385347452648505636561683162429807084034083676343500 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.61173596180672345789803202385347452648505636561683162429807084034083676343500
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_same_source.27681224138825790985746832607618185458895247551610118194924436040308398155587
Short name T687
Test name
Test status
Simulation time 2498784073 ps
CPU time 80.28 seconds
Started Nov 22 03:07:27 PM PST 23
Finished Nov 22 03:08:48 PM PST 23
Peak memory 553788 kb
Host smart-e7357b26-a921-4103-b0d9-06dfaf12eb7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27681224138825790985746832607618185458895247551610118194924436040308398155587 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.27681224138825790985746832607618185458895247551610118194924436040308398155587
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke.92938219712778635897176506007147617698457959548145686919608936389787618880622
Short name T992
Test name
Test status
Simulation time 196985727 ps
CPU time 9.18 seconds
Started Nov 22 03:07:14 PM PST 23
Finished Nov 22 03:07:24 PM PST 23
Peak memory 552368 kb
Host smart-40dcebcf-0c38-4f51-9872-cb92dcb3483f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92938219712778635897176506007147617698457959548145686919608936389787618880622 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 43.xbar_smoke.92938219712778635897176506007147617698457959548145686919608936389787618880622
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.29191450254751049324861610281064429849499470315598916993856248344195219032852
Short name T98
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.64 seconds
Started Nov 22 03:07:21 PM PST 23
Finished Nov 22 03:08:52 PM PST 23
Peak memory 552376 kb
Host smart-dd538fb0-d153-4d37-9344-c5b24509f464
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29191450254751049324861610281064429849499470315598916993856248344195219032852 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.29191450254751049324861610281064429849499470315598916993856248344195219032852
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.49978275060239163759450959525509371555737707516375371922068500736227190539209
Short name T1011
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.91 seconds
Started Nov 22 03:07:14 PM PST 23
Finished Nov 22 03:08:35 PM PST 23
Peak memory 552372 kb
Host smart-733f1a05-bf5d-46c5-86e7-5114ae44d994
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49978275060239163759450959525509371555737707516375371922068500736227190539209 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.49978275060239163759450959525509371555737707516375371922068500736227190539209
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.80940597628316053388756238168808728290095382008241187445802093595001894810615
Short name T1730
Test name
Test status
Simulation time 45555727 ps
CPU time 5.93 seconds
Started Nov 22 03:07:12 PM PST 23
Finished Nov 22 03:07:18 PM PST 23
Peak memory 552296 kb
Host smart-c009378c-788b-4f91-a4c5-c977819936c4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80940597628316053388756238168808728290095382008241187445802093595001894810615 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.80940597628316053388756238168808728290095382008241187445802093595001894810615
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all.38150935174001632839433877104834377823037884864977259378607732872861055631831
Short name T1795
Test name
Test status
Simulation time 13992004073 ps
CPU time 512.52 seconds
Started Nov 22 03:07:25 PM PST 23
Finished Nov 22 03:15:59 PM PST 23
Peak memory 555972 kb
Host smart-dfa1b3b4-a885-412f-b986-f0dead20d43c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38150935174001632839433877104834377823037884864977259378607732872861055631831 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.38150935174001632839433877104834377823037884864977259378607732872861055631831
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.22774306149266198085892537616665886474709412859329923044069469589870743177353
Short name T1924
Test name
Test status
Simulation time 13999524073 ps
CPU time 531.81 seconds
Started Nov 22 03:07:24 PM PST 23
Finished Nov 22 03:16:18 PM PST 23
Peak memory 555820 kb
Host smart-22b87e49-edc9-45e9-90c9-dce127973563
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22774306149266198085892537616665886474709412859329923044069469589870743177353 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.22774306149266198085892537616665886474709412859329923044069469589870743177353
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.43661187328075891622875459328147125839239190940659700884130068830117648112236
Short name T1065
Test name
Test status
Simulation time 4815189184 ps
CPU time 390.73 seconds
Started Nov 22 03:07:25 PM PST 23
Finished Nov 22 03:13:57 PM PST 23
Peak memory 557248 kb
Host smart-8d31c222-b917-45cd-84f3-4b1eec9a7e93
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43661187328075891622875459328147125839239190940659700884130068830117648112236 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.43661187328075891622875459328147125839239190940659700884130068
830117648112236
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.77631574995297722396753150535345252677054158108789832072996171676246893446633
Short name T535
Test name
Test status
Simulation time 4815189184 ps
CPU time 308.01 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:12:53 PM PST 23
Peak memory 559700 kb
Host smart-787a3d84-d333-4a6a-addc-aa8d191d3744
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77631574995297722396753150535345252677054158108789832072996171676246893446633 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.776315749952977223967531505353452526770541581087898320729961
71676246893446633
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.28718187545355007753738146094653674621920600731401890165986025726166609061346
Short name T1697
Test name
Test status
Simulation time 1176995727 ps
CPU time 55.48 seconds
Started Nov 22 03:07:24 PM PST 23
Finished Nov 22 03:08:22 PM PST 23
Peak memory 553680 kb
Host smart-9e871c58-9c70-4d2e-8b7a-c7346e414544
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28718187545355007753738146094653674621920600731401890165986025726166609061346 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.28718187545355007753738146094653674621920600731401890165986025726166609061346
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device.104994326086979242256804238796667370468769911378458273612035893730821897490606
Short name T1820
Test name
Test status
Simulation time 2590995727 ps
CPU time 103.22 seconds
Started Nov 22 03:07:35 PM PST 23
Finished Nov 22 03:09:19 PM PST 23
Peak memory 554812 kb
Host smart-4829846a-a107-4cfb-b383-d71241451653
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104994326086979242256804238796667370468769911378458273612035893730821897490606 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.104994326086979242256804238796667370468769911378458273612035893730821897490606
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.106424164954569099979834402267344103763737406470872302430531125145492204149629
Short name T979
Test name
Test status
Simulation time 115195295727 ps
CPU time 2105.07 seconds
Started Nov 22 03:07:36 PM PST 23
Finished Nov 22 03:42:42 PM PST 23
Peak memory 554764 kb
Host smart-2f185132-3914-44d7-9899-4a84ed4d44f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106424164954569099979834402267344103763737406470872302430531125145492204149629 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.106424164954569099979834402267344103763737406470872302430531125145492204149629
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.48358139025815904152191679064734097231322961110807531980257640702708360273487
Short name T758
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.57 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:08:24 PM PST 23
Peak memory 553508 kb
Host smart-1d6f9333-e5fe-4799-9787-bc8950969f88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48358139025815904152191679064734097231322961110807531980257640702708360273487 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.48358139025815904152191679064734097231322961110807531980257640702708360273487
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_random.16449227235608318344962027903794253281331776556822150704472175851519105640566
Short name T1131
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.89 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:09:00 PM PST 23
Peak memory 553536 kb
Host smart-071c26ce-ebf6-4c1f-9d62-8ead7ba086ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449227235608318344962027903794253281331776556822150704472175851519105640566 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 44.xbar_error_random.16449227235608318344962027903794253281331776556822150704472175851519105640566
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random.100651715949356236407661930490584412065873072996047700418556014928718873083084
Short name T82
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.6 seconds
Started Nov 22 03:07:24 PM PST 23
Finished Nov 22 03:08:49 PM PST 23
Peak memory 553744 kb
Host smart-1364fe7c-53da-427c-9a35-83b93a692850
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100651715949356236407661930490584412065873072996047700418556014928718873083084 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 44.xbar_random.100651715949356236407661930490584412065873072996047700418556014928718873083084
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.104758965225678531854055358797478432319799423599959485245545344117812080251336
Short name T757
Test name
Test status
Simulation time 97702135727 ps
CPU time 1173.53 seconds
Started Nov 22 03:07:38 PM PST 23
Finished Nov 22 03:27:13 PM PST 23
Peak memory 553688 kb
Host smart-9a8e4590-3de7-4b31-b622-d8bd0184ecc2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104758965225678531854055358797478432319799423599959485245545344117812080251336 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.104758965225678531854055358797478432319799423599959485245545344117812080251336
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.108913922744548341931046843387689740908221872611682640707481290182788670028967
Short name T1801
Test name
Test status
Simulation time 60576345727 ps
CPU time 1128.28 seconds
Started Nov 22 03:07:34 PM PST 23
Finished Nov 22 03:26:23 PM PST 23
Peak memory 553708 kb
Host smart-ebf874cb-2c8d-4882-8708-eea81d2696ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108913922744548341931046843387689740908221872611682640707481290182788670028967 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.108913922744548341931046843387689740908221872611682640707481290182788670028967
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.10358556281371135985754122140539993198054123851966302746309661268261376774829
Short name T862
Test name
Test status
Simulation time 556965727 ps
CPU time 48.3 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:08:29 PM PST 23
Peak memory 553708 kb
Host smart-284939c2-6559-41cf-8a0b-71afb369d627
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10358556281371135985754122140539993198054123851966302746309661268261376774829 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.10358556281371135985754122140539993198054123851966302746309661268261376774829
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_same_source.10396947447634207631683703876417768238597737062434964199912246785191450425491
Short name T985
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.24 seconds
Started Nov 22 03:07:39 PM PST 23
Finished Nov 22 03:08:56 PM PST 23
Peak memory 553728 kb
Host smart-601a02a1-2eec-44f2-a52c-1b3d81a20db1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10396947447634207631683703876417768238597737062434964199912246785191450425491 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.10396947447634207631683703876417768238597737062434964199912246785191450425491
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke.75405916333659873240489474655669689063353167212231661550970906006647679630749
Short name T1574
Test name
Test status
Simulation time 196985727 ps
CPU time 9.76 seconds
Started Nov 22 03:07:24 PM PST 23
Finished Nov 22 03:07:36 PM PST 23
Peak memory 552380 kb
Host smart-e623953a-248f-44a7-af91-9ddbe30005de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75405916333659873240489474655669689063353167212231661550970906006647679630749 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 44.xbar_smoke.75405916333659873240489474655669689063353167212231661550970906006647679630749
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.114144435370124673087446167645613480692848084545435216224125203688073125305312
Short name T964
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.19 seconds
Started Nov 22 03:07:29 PM PST 23
Finished Nov 22 03:08:58 PM PST 23
Peak memory 552268 kb
Host smart-76662982-c970-4f7d-87c6-547e478014f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114144435370124673087446167645613480692848084545435216224125203688073125305312 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.114144435370124673087446167645613480692848084545435216224125203688073125305312
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.16355702935346686813673238410604438564483422201162333809514791432093534405622
Short name T106
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.46 seconds
Started Nov 22 03:07:26 PM PST 23
Finished Nov 22 03:08:57 PM PST 23
Peak memory 552420 kb
Host smart-c7df3382-d9b6-48ab-a7f0-6a33e6733ace
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16355702935346686813673238410604438564483422201162333809514791432093534405622 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.16355702935346686813673238410604438564483422201162333809514791432093534405622
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.54936138874585791378501502965509428887517074151522830973026634262155006562706
Short name T340
Test name
Test status
Simulation time 45555727 ps
CPU time 5.93 seconds
Started Nov 22 03:07:31 PM PST 23
Finished Nov 22 03:07:38 PM PST 23
Peak memory 552360 kb
Host smart-cbaaa042-76d2-40dc-a3ae-0626f494351d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54936138874585791378501502965509428887517074151522830973026634262155006562706 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.54936138874585791378501502965509428887517074151522830973026634262155006562706
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all.100907744755275176529551228862140710785035712019663818153531686540102203841672
Short name T1424
Test name
Test status
Simulation time 13992004073 ps
CPU time 499.14 seconds
Started Nov 22 03:07:39 PM PST 23
Finished Nov 22 03:16:00 PM PST 23
Peak memory 555896 kb
Host smart-84b9afe7-1419-47ec-81c1-fc4f443a1623
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100907744755275176529551228862140710785035712019663818153531686540102203841672 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.100907744755275176529551228862140710785035712019663818153531686540102203841672
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.92353193369265352431467473072871119318156655058673443615035927468117826302952
Short name T240
Test name
Test status
Simulation time 13999524073 ps
CPU time 481.53 seconds
Started Nov 22 03:07:32 PM PST 23
Finished Nov 22 03:15:34 PM PST 23
Peak memory 555732 kb
Host smart-4f09d689-3e2e-45f3-82bb-e6290f8a8be5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92353193369265352431467473072871119318156655058673443615035927468117826302952 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.92353193369265352431467473072871119318156655058673443615035927468117826302952
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.85993930460852430551337366283457322175317042977722399778837791372562412401194
Short name T484
Test name
Test status
Simulation time 4815189184 ps
CPU time 385.08 seconds
Started Nov 22 03:07:36 PM PST 23
Finished Nov 22 03:14:02 PM PST 23
Peak memory 557268 kb
Host smart-ec203be4-c6de-40ac-943c-e1fda9f5b288
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85993930460852430551337366283457322175317042977722399778837791372562412401194 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.85993930460852430551337366283457322175317042977722399778837791
372562412401194
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.8395263362184872225848651883854088782822856166387832743108399037243901429625
Short name T584
Test name
Test status
Simulation time 4815189184 ps
CPU time 320.41 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:13:06 PM PST 23
Peak memory 559672 kb
Host smart-8cb5c4ac-13c0-4eca-9098-aa355e1a0a81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8395263362184872225848651883854088782822856166387832743108399037243901429625 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.8395263362184872225848651883854088782822856166387832743108399
037243901429625
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.106554423669625607397567435257723734999040411035840372375885835492792550462237
Short name T1053
Test name
Test status
Simulation time 1176995727 ps
CPU time 51.92 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:08:36 PM PST 23
Peak memory 553628 kb
Host smart-9e6db896-b123-4d82-84c6-8080dde23de2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106554423669625607397567435257723734999040411035840372375885835492792550462237 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.106554423669625607397567435257723734999040411035840372375885835492792550462237
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device.87548909051180642553228470156452890997340065945282799770098297867374365203639
Short name T1485
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.21 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:09:26 PM PST 23
Peak memory 554704 kb
Host smart-7330a980-d801-4166-b0ab-6f00eee78fea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87548909051180642553228470156452890997340065945282799770098297867374365203639 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.87548909051180642553228470156452890997340065945282799770098297867374365203639
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.79472568053577229353304888509220982212537512069718201158246535552032014300252
Short name T1328
Test name
Test status
Simulation time 115195295727 ps
CPU time 1861.16 seconds
Started Nov 22 03:07:38 PM PST 23
Finished Nov 22 03:38:41 PM PST 23
Peak memory 554760 kb
Host smart-e83a7c0d-dc09-414b-8e49-4550d7cf28f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79472568053577229353304888509220982212537512069718201158246535552032014300252 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.79472568053577229353304888509220982212537512069718201158246535552032014300252
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.82940849903392676043281767355446532722921935907600827110288995565856431082659
Short name T760
Test name
Test status
Simulation time 1171215727 ps
CPU time 48.98 seconds
Started Nov 22 03:07:38 PM PST 23
Finished Nov 22 03:08:28 PM PST 23
Peak memory 553484 kb
Host smart-553043b6-c69e-431e-adeb-c9d9b7c67f2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82940849903392676043281767355446532722921935907600827110288995565856431082659 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.82940849903392676043281767355446532722921935907600827110288995565856431082659
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_random.52598510711461398239632214498123856238656932216635888356108410453777636926304
Short name T1489
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.58 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:09:02 PM PST 23
Peak memory 553644 kb
Host smart-881cc9e3-4ccb-4ffa-8d83-d627f9c1fb06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52598510711461398239632214498123856238656932216635888356108410453777636926304 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 45.xbar_error_random.52598510711461398239632214498123856238656932216635888356108410453777636926304
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random.70724600077108838275397187261415997746349104968260092073319665065875985557377
Short name T1442
Test name
Test status
Simulation time 2231375727 ps
CPU time 83.94 seconds
Started Nov 22 03:07:35 PM PST 23
Finished Nov 22 03:09:00 PM PST 23
Peak memory 553756 kb
Host smart-64c8d9b0-fa8a-4f45-b280-ed0c5f9a35e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70724600077108838275397187261415997746349104968260092073319665065875985557377 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 45.xbar_random.70724600077108838275397187261415997746349104968260092073319665065875985557377
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.23322599670008255767986110977033055342462762291639693521462963755343400207393
Short name T1208
Test name
Test status
Simulation time 97702135727 ps
CPU time 1178.44 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:27:24 PM PST 23
Peak memory 553608 kb
Host smart-b5eac5b8-56d8-4b74-8724-03c1e2ffd922
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23322599670008255767986110977033055342462762291639693521462963755343400207393 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.23322599670008255767986110977033055342462762291639693521462963755343400207393
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.89803339893804877316031125270062784004420593160995217875973665963539871607382
Short name T1819
Test name
Test status
Simulation time 60576345727 ps
CPU time 1136.86 seconds
Started Nov 22 03:07:36 PM PST 23
Finished Nov 22 03:26:34 PM PST 23
Peak memory 553668 kb
Host smart-e21d92d4-1e9c-448a-bb2b-b5397fd54049
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89803339893804877316031125270062784004420593160995217875973665963539871607382 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.89803339893804877316031125270062784004420593160995217875973665963539871607382
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.106037384725786740413109340775547910043796401720711232077194543362540968476880
Short name T1838
Test name
Test status
Simulation time 556965727 ps
CPU time 52.65 seconds
Started Nov 22 03:07:42 PM PST 23
Finished Nov 22 03:08:40 PM PST 23
Peak memory 553760 kb
Host smart-e28e9707-84c2-4819-ba20-2f7372c76e33
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106037384725786740413109340775547910043796401720711232077194543362540968476880 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.106037384725786740413109340775547910043796401720711232077194543362540968476880
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_same_source.105593557911025317942809856799127098675609743042791721696678591925723402511684
Short name T312
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.44 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:08:51 PM PST 23
Peak memory 553672 kb
Host smart-eabe9c64-bf26-4697-a051-f4de9536a1ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105593557911025317942809856799127098675609743042791721696678591925723402511684 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.105593557911025317942809856799127098675609743042791721696678591925723402511684
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke.24828396623127480301730019658784121827740742469290051094419204806783332320927
Short name T710
Test name
Test status
Simulation time 196985727 ps
CPU time 8.72 seconds
Started Nov 22 03:07:38 PM PST 23
Finished Nov 22 03:07:48 PM PST 23
Peak memory 552372 kb
Host smart-e8793be2-09d3-4fb5-9bf2-b932ac0be7a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828396623127480301730019658784121827740742469290051094419204806783332320927 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 45.xbar_smoke.24828396623127480301730019658784121827740742469290051094419204806783332320927
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.112638642592560961648849790048133837276841656431553471044245117941453121675203
Short name T1007
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.36 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:09:10 PM PST 23
Peak memory 552476 kb
Host smart-d60b63a7-1e89-4dcb-abe1-34345c6e24ca
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112638642592560961648849790048133837276841656431553471044245117941453121675203 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.112638642592560961648849790048133837276841656431553471044245117941453121675203
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.62990260592255628619020019163196851997525409399201220382993957255573702681517
Short name T451
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.78 seconds
Started Nov 22 03:07:38 PM PST 23
Finished Nov 22 03:09:08 PM PST 23
Peak memory 552400 kb
Host smart-a8487a9d-dab8-4451-ab25-51b749299821
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62990260592255628619020019163196851997525409399201220382993957255573702681517 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.62990260592255628619020019163196851997525409399201220382993957255573702681517
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.42620441003713189995984356445568205267488329115539673064634206395645368290093
Short name T1698
Test name
Test status
Simulation time 45555727 ps
CPU time 6.23 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:07:44 PM PST 23
Peak memory 552340 kb
Host smart-f83205f2-d952-47a7-9bab-153bf9105d0e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42620441003713189995984356445568205267488329115539673064634206395645368290093 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.42620441003713189995984356445568205267488329115539673064634206395645368290093
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all.5136092914517415056894396824605141832145274588506160275833022589777458044194
Short name T348
Test name
Test status
Simulation time 13992004073 ps
CPU time 532.13 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:16:39 PM PST 23
Peak memory 555848 kb
Host smart-04ff7336-252d-4b0b-91f4-b04d0715884e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5136092914517415056894396824605141832145274588506160275833022589777458044194 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.5136092914517415056894396824605141832145274588506160275833022589777458044194
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.43418440867069179932216148725030443415259452578130365570375630316324898881494
Short name T1762
Test name
Test status
Simulation time 13999524073 ps
CPU time 506.61 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:16:11 PM PST 23
Peak memory 555724 kb
Host smart-cb8dceb1-b300-4d05-9865-3998e031e20a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43418440867069179932216148725030443415259452578130365570375630316324898881494 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.43418440867069179932216148725030443415259452578130365570375630316324898881494
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.18341086625722144944723634493101980112701402222882326223049157812700784108677
Short name T1166
Test name
Test status
Simulation time 4815189184 ps
CPU time 371.54 seconds
Started Nov 22 03:07:35 PM PST 23
Finished Nov 22 03:13:47 PM PST 23
Peak memory 557272 kb
Host smart-cd675477-27b4-4ea8-a68f-f18cd4184055
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18341086625722144944723634493101980112701402222882326223049157812700784108677 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.18341086625722144944723634493101980112701402222882326223049157
812700784108677
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.102429543000336219827507738274525591897169452973788787865353388634880727249714
Short name T528
Test name
Test status
Simulation time 4815189184 ps
CPU time 321.66 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:13:07 PM PST 23
Peak memory 559724 kb
Host smart-57739508-abcb-4178-9216-14a851928187
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102429543000336219827507738274525591897169452973788787865353388634880727249714 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.10242954300033621982750773827452559189716945297378878786535
3388634880727249714
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.56676171588476556943920578656879031356887227658318198666685847466911361352086
Short name T1855
Test name
Test status
Simulation time 1176995727 ps
CPU time 51.32 seconds
Started Nov 22 03:07:35 PM PST 23
Finished Nov 22 03:08:27 PM PST 23
Peak memory 553648 kb
Host smart-908793b9-f472-4ae8-80e1-2fa7c4180f44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56676171588476556943920578656879031356887227658318198666685847466911361352086 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.56676171588476556943920578656879031356887227658318198666685847466911361352086
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device.61914338512630167984532531927874032040018970023429351361072083085700479406872
Short name T353
Test name
Test status
Simulation time 2590995727 ps
CPU time 113.13 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:09:31 PM PST 23
Peak memory 554792 kb
Host smart-3d617b3d-9f20-41f1-a6f9-38d415b70413
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61914338512630167984532531927874032040018970023429351361072083085700479406872 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.61914338512630167984532531927874032040018970023429351361072083085700479406872
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.113402963582175010570063967184556496735740677213661572872984291546446972164404
Short name T276
Test name
Test status
Simulation time 115195295727 ps
CPU time 1887.52 seconds
Started Nov 22 03:07:46 PM PST 23
Finished Nov 22 03:39:16 PM PST 23
Peak memory 554804 kb
Host smart-7f122d99-eb39-4d59-9d07-4fd975ceaed0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113402963582175010570063967184556496735740677213661572872984291546446972164404 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.113402963582175010570063967184556496735740677213661572872984291546446972164404
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.45031450042315181259193697257731647424146353850529549051955654137253901891344
Short name T814
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.7 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:08:32 PM PST 23
Peak memory 553432 kb
Host smart-2aa87b56-a31f-4b85-933d-88c03abfb7cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45031450042315181259193697257731647424146353850529549051955654137253901891344 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.45031450042315181259193697257731647424146353850529549051955654137253901891344
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_random.67661479863180481140967713093418910798476928189769880626398616426030271916143
Short name T1769
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.74 seconds
Started Nov 22 03:07:39 PM PST 23
Finished Nov 22 03:08:56 PM PST 23
Peak memory 553536 kb
Host smart-5a3579ca-2961-4926-82f1-551cb075cc50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67661479863180481140967713093418910798476928189769880626398616426030271916143 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 46.xbar_error_random.67661479863180481140967713093418910798476928189769880626398616426030271916143
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random.28796696325360453895713793465534855130161828737053141559348414777761306707870
Short name T1157
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.17 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:09:07 PM PST 23
Peak memory 553704 kb
Host smart-cacdca56-c53f-4910-838b-b7214a2d81e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796696325360453895713793465534855130161828737053141559348414777761306707870 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 46.xbar_random.28796696325360453895713793465534855130161828737053141559348414777761306707870
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.61400666882021536762843477448244858759490736172146796218700232099094188585198
Short name T132
Test name
Test status
Simulation time 97702135727 ps
CPU time 1151.86 seconds
Started Nov 22 03:07:40 PM PST 23
Finished Nov 22 03:26:56 PM PST 23
Peak memory 553640 kb
Host smart-59e341cf-00b2-4b03-ae58-2250d0462100
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61400666882021536762843477448244858759490736172146796218700232099094188585198 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.61400666882021536762843477448244858759490736172146796218700232099094188585198
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.76253686440192202225414071721332669012848905561502423189919796333793418165289
Short name T1054
Test name
Test status
Simulation time 60576345727 ps
CPU time 1105.25 seconds
Started Nov 22 03:07:38 PM PST 23
Finished Nov 22 03:26:05 PM PST 23
Peak memory 553716 kb
Host smart-b529f27f-db74-4867-a5a3-248d8b152bd2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76253686440192202225414071721332669012848905561502423189919796333793418165289 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.76253686440192202225414071721332669012848905561502423189919796333793418165289
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.95078920533558770159165293724536304095805034373304499589643164671883247440608
Short name T695
Test name
Test status
Simulation time 556965727 ps
CPU time 43.34 seconds
Started Nov 22 03:07:36 PM PST 23
Finished Nov 22 03:08:20 PM PST 23
Peak memory 553708 kb
Host smart-b10c190f-ed0f-484c-9648-d6bff7fdf198
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95078920533558770159165293724536304095805034373304499589643164671883247440608 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.95078920533558770159165293724536304095805034373304499589643164671883247440608
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_same_source.70589464764100424082193511608492038512304800362995828057023538182541453059201
Short name T1113
Test name
Test status
Simulation time 2498784073 ps
CPU time 70.55 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:08:58 PM PST 23
Peak memory 553848 kb
Host smart-629f13fc-1fa4-47fc-a48d-b68fbad2bae3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70589464764100424082193511608492038512304800362995828057023538182541453059201 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.70589464764100424082193511608492038512304800362995828057023538182541453059201
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke.57423984650860605949172208808487028323155366988031666244497898382542337930574
Short name T1004
Test name
Test status
Simulation time 196985727 ps
CPU time 8.68 seconds
Started Nov 22 03:07:35 PM PST 23
Finished Nov 22 03:07:45 PM PST 23
Peak memory 552276 kb
Host smart-21a376c5-4ee9-4778-ac5b-089d8c3e8ad7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57423984650860605949172208808487028323155366988031666244497898382542337930574 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 46.xbar_smoke.57423984650860605949172208808487028323155366988031666244497898382542337930574
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.89028888140293505950595937025495738925612178151298898348917191779520307489538
Short name T1530
Test name
Test status
Simulation time 7758585727 ps
CPU time 83.4 seconds
Started Nov 22 03:07:39 PM PST 23
Finished Nov 22 03:09:04 PM PST 23
Peak memory 552364 kb
Host smart-3357ac45-c20a-417b-ad92-69f02daadc85
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89028888140293505950595937025495738925612178151298898348917191779520307489538 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.89028888140293505950595937025495738925612178151298898348917191779520307489538
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.35479909488754517328911512906398260931049657891213160259662837486423897823850
Short name T1137
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.18 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:09:04 PM PST 23
Peak memory 552416 kb
Host smart-02397ed8-3b6e-48ca-93a2-1b5d8269df8b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35479909488754517328911512906398260931049657891213160259662837486423897823850 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.35479909488754517328911512906398260931049657891213160259662837486423897823850
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.61912618374052515906938889655023308921137099286562947512349883899930630359042
Short name T105
Test name
Test status
Simulation time 45555727 ps
CPU time 6.32 seconds
Started Nov 22 03:07:38 PM PST 23
Finished Nov 22 03:07:45 PM PST 23
Peak memory 552328 kb
Host smart-4bd9d326-8a0b-4347-81c6-b88d86faedd5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61912618374052515906938889655023308921137099286562947512349883899930630359042 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.61912618374052515906938889655023308921137099286562947512349883899930630359042
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all.5279362390386510523568844451446502581317618890558473461328170456983594702567
Short name T195
Test name
Test status
Simulation time 13992004073 ps
CPU time 543.1 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:16:49 PM PST 23
Peak memory 555816 kb
Host smart-d2d8315e-7608-45b7-82ef-3f75e9841be1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5279362390386510523568844451446502581317618890558473461328170456983594702567 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.5279362390386510523568844451446502581317618890558473461328170456983594702567
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.105583396478520015176800032044193624692381018709664588578642706830812377606894
Short name T1606
Test name
Test status
Simulation time 13999524073 ps
CPU time 477.76 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:15:44 PM PST 23
Peak memory 555660 kb
Host smart-e717990d-8097-40df-9a6f-dfae77cdcc2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105583396478520015176800032044193624692381018709664588578642706830812377606894 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.105583396478520015176800032044193624692381018709664588578642706830812377606894
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.60929389818581607657033252358699073400227838855045340515158568172007934152652
Short name T1585
Test name
Test status
Simulation time 4815189184 ps
CPU time 394.74 seconds
Started Nov 22 03:07:39 PM PST 23
Finished Nov 22 03:14:15 PM PST 23
Peak memory 557220 kb
Host smart-cc2f347b-f781-42ba-be68-e430d86b651d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60929389818581607657033252358699073400227838855045340515158568172007934152652 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.60929389818581607657033252358699073400227838855045340515158568
172007934152652
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.9375055887115805796566965935224515854045311777521043278126080034315983188654
Short name T244
Test name
Test status
Simulation time 4815189184 ps
CPU time 306.75 seconds
Started Nov 22 03:07:42 PM PST 23
Finished Nov 22 03:12:54 PM PST 23
Peak memory 559660 kb
Host smart-5c5262e2-681b-46a7-9211-52e018bb034e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9375055887115805796566965935224515854045311777521043278126080034315983188654 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.9375055887115805796566965935224515854045311777521043278126080
034315983188654
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.32295513568034803643995115983600657370607212258320244169457409928028782538389
Short name T65
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.99 seconds
Started Nov 22 03:07:34 PM PST 23
Finished Nov 22 03:08:21 PM PST 23
Peak memory 553712 kb
Host smart-da4f5700-e6bf-4b96-9fc7-6c32e3c94af7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295513568034803643995115983600657370607212258320244169457409928028782538389 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.32295513568034803643995115983600657370607212258320244169457409928028782538389
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device.84653551567727358946323871734597837084943988568228775675348677484971080370486
Short name T412
Test name
Test status
Simulation time 2590995727 ps
CPU time 122.28 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:09:54 PM PST 23
Peak memory 554776 kb
Host smart-275da187-e1cb-4457-b769-6671216dc4c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84653551567727358946323871734597837084943988568228775675348677484971080370486 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.84653551567727358946323871734597837084943988568228775675348677484971080370486
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.50219334484638336869929563663715087649910039763895397230323975303971675698051
Short name T1794
Test name
Test status
Simulation time 115195295727 ps
CPU time 2013.97 seconds
Started Nov 22 03:07:50 PM PST 23
Finished Nov 22 03:41:26 PM PST 23
Peak memory 554796 kb
Host smart-9df4f889-f09d-4e43-8102-ec75fd25d139
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50219334484638336869929563663715087649910039763895397230323975303971675698051 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.50219334484638336869929563663715087649910039763895397230323975303971675698051
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.18894351325812669061530440050565369325337706672178079266642245552095061686236
Short name T1350
Test name
Test status
Simulation time 1171215727 ps
CPU time 48.21 seconds
Started Nov 22 03:07:51 PM PST 23
Finished Nov 22 03:08:40 PM PST 23
Peak memory 553576 kb
Host smart-26014537-9dc9-4700-beff-fdd862f4d0fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18894351325812669061530440050565369325337706672178079266642245552095061686236 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.18894351325812669061530440050565369325337706672178079266642245552095061686236
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_random.79478813161516126647413783695834605172358317020812789836070669514739936293921
Short name T870
Test name
Test status
Simulation time 2231375727 ps
CPU time 83.45 seconds
Started Nov 22 03:07:48 PM PST 23
Finished Nov 22 03:09:15 PM PST 23
Peak memory 553556 kb
Host smart-cd5f8681-46b3-4496-bd9e-848c7ec77163
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79478813161516126647413783695834605172358317020812789836070669514739936293921 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 47.xbar_error_random.79478813161516126647413783695834605172358317020812789836070669514739936293921
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random.60419680506740664535716266575022165011684876004427707239408170495458663625862
Short name T1609
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.99 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:09:04 PM PST 23
Peak memory 553644 kb
Host smart-8c972c19-fb12-45a3-afee-a88a6e83732c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60419680506740664535716266575022165011684876004427707239408170495458663625862 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 47.xbar_random.60419680506740664535716266575022165011684876004427707239408170495458663625862
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.67403322349664315145485792668792797081662231929853570734592097612775525971165
Short name T1791
Test name
Test status
Simulation time 97702135727 ps
CPU time 1096.5 seconds
Started Nov 22 03:07:45 PM PST 23
Finished Nov 22 03:26:04 PM PST 23
Peak memory 553700 kb
Host smart-7c617c0e-f23b-4988-ae13-027ad9f54007
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67403322349664315145485792668792797081662231929853570734592097612775525971165 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.67403322349664315145485792668792797081662231929853570734592097612775525971165
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.11507183399968583502364661265997859992687140473322468563885704081372314330633
Short name T1733
Test name
Test status
Simulation time 60576345727 ps
CPU time 1086.23 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:25:53 PM PST 23
Peak memory 553684 kb
Host smart-48faf215-0e95-4672-9b5f-6ba42c5d4c35
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11507183399968583502364661265997859992687140473322468563885704081372314330633 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.11507183399968583502364661265997859992687140473322468563885704081372314330633
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.56951806571416685525781385091396924273797063742849013233445414843333754279302
Short name T454
Test name
Test status
Simulation time 556965727 ps
CPU time 48.1 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:08:34 PM PST 23
Peak memory 553736 kb
Host smart-66cea492-18ff-44c6-a98d-7519910caeb0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56951806571416685525781385091396924273797063742849013233445414843333754279302 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.56951806571416685525781385091396924273797063742849013233445414843333754279302
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_same_source.53449607365703775757205914729470802160481694722643489831847321954606297814583
Short name T1229
Test name
Test status
Simulation time 2498784073 ps
CPU time 84.58 seconds
Started Nov 22 03:07:39 PM PST 23
Finished Nov 22 03:09:05 PM PST 23
Peak memory 553820 kb
Host smart-b2f7c8f2-6fec-43e3-a3d2-1c83fb701260
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53449607365703775757205914729470802160481694722643489831847321954606297814583 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.53449607365703775757205914729470802160481694722643489831847321954606297814583
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke.63721895410576739273467603963607534631064587651573495741820064300296408051404
Short name T1192
Test name
Test status
Simulation time 196985727 ps
CPU time 8.4 seconds
Started Nov 22 03:07:37 PM PST 23
Finished Nov 22 03:07:47 PM PST 23
Peak memory 552368 kb
Host smart-8ccfcbfa-4574-45a2-932e-f06779e0934a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63721895410576739273467603963607534631064587651573495741820064300296408051404 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 47.xbar_smoke.63721895410576739273467603963607534631064587651573495741820064300296408051404
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2334657765927620752416707565314165268174049637733227298342052355015756264722
Short name T730
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.75 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:09:18 PM PST 23
Peak memory 552276 kb
Host smart-cbe7af20-53fd-4b19-ab92-f3c95e37172e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334657765927620752416707565314165268174049637733227298342052355015756264722 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2334657765927620752416707565314165268174049637733227298342052355015756264722
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.42938395162547004647823084241688498526603293059855426508496376009549426448418
Short name T212
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.43 seconds
Started Nov 22 03:07:51 PM PST 23
Finished Nov 22 03:09:20 PM PST 23
Peak memory 552484 kb
Host smart-f3d041d0-dbb4-4d75-8c6f-93304cbfa8b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938395162547004647823084241688498526603293059855426508496376009549426448418 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.42938395162547004647823084241688498526603293059855426508496376009549426448418
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.113541369007428750597329881306003295585315626194773727581265824512907591828885
Short name T160
Test name
Test status
Simulation time 45555727 ps
CPU time 5.98 seconds
Started Nov 22 03:07:45 PM PST 23
Finished Nov 22 03:07:54 PM PST 23
Peak memory 552372 kb
Host smart-728fd758-c624-4447-9347-4779a943704f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113541369007428750597329881306003295585315626194773727581265824512907591828885 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.113541369007428750597329881306003295585315626194773727581265824512907591828885
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all.41783203481558273094947220537940200099022658250621447380090781496063121361508
Short name T1679
Test name
Test status
Simulation time 13992004073 ps
CPU time 514.37 seconds
Started Nov 22 03:07:39 PM PST 23
Finished Nov 22 03:16:15 PM PST 23
Peak memory 555920 kb
Host smart-7618154d-aafa-4f13-99fd-4e3920de1225
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41783203481558273094947220537940200099022658250621447380090781496063121361508 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.41783203481558273094947220537940200099022658250621447380090781496063121361508
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.24504776670211320646426575192588759071663654219807674087264367722076883009735
Short name T403
Test name
Test status
Simulation time 13999524073 ps
CPU time 523.04 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:16:35 PM PST 23
Peak memory 555708 kb
Host smart-5e709b46-ee0b-4521-a777-f28e80cf47b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24504776670211320646426575192588759071663654219807674087264367722076883009735 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.24504776670211320646426575192588759071663654219807674087264367722076883009735
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.43713935943119148632845657641353495331642006714064546424286521257656604266982
Short name T869
Test name
Test status
Simulation time 4815189184 ps
CPU time 406.75 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:14:38 PM PST 23
Peak memory 557252 kb
Host smart-83aab23a-1e6b-472b-b038-485317f4939b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43713935943119148632845657641353495331642006714064546424286521257656604266982 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.43713935943119148632845657641353495331642006714064546424286521
257656604266982
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.74955080950101023552933190506692306147493959184593353616881890874956025392936
Short name T1073
Test name
Test status
Simulation time 4815189184 ps
CPU time 307.34 seconds
Started Nov 22 03:07:47 PM PST 23
Finished Nov 22 03:12:58 PM PST 23
Peak memory 559648 kb
Host smart-04d0dd84-5a8c-4315-a87e-f4033acfc7b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74955080950101023552933190506692306147493959184593353616881890874956025392936 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.749550809501010235529331905066923061474939591845933536168818
90874956025392936
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.75370261104900767332979286508844729055491477534769966209047411028264270023771
Short name T1010
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.55 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:08:40 PM PST 23
Peak memory 553728 kb
Host smart-3ecd4b79-1c9e-4b8d-b357-45e0f879d861
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75370261104900767332979286508844729055491477534769966209047411028264270023771 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.75370261104900767332979286508844729055491477534769966209047411028264270023771
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device.108555550016064785573181391376728561184811863604649866971145422153847106381723
Short name T897
Test name
Test status
Simulation time 2590995727 ps
CPU time 104.24 seconds
Started Nov 22 03:07:51 PM PST 23
Finished Nov 22 03:09:36 PM PST 23
Peak memory 554888 kb
Host smart-f5b23344-32eb-44c6-8349-f35f0a2f2f6e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108555550016064785573181391376728561184811863604649866971145422153847106381723 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.108555550016064785573181391376728561184811863604649866971145422153847106381723
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.85735121340174332216123268498350034947371228693463137612409480714612145114859
Short name T691
Test name
Test status
Simulation time 115195295727 ps
CPU time 2036.15 seconds
Started Nov 22 03:07:51 PM PST 23
Finished Nov 22 03:41:48 PM PST 23
Peak memory 554864 kb
Host smart-a4aafdfb-3867-48d6-b810-72154b9a954b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85735121340174332216123268498350034947371228693463137612409480714612145114859 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.85735121340174332216123268498350034947371228693463137612409480714612145114859
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.114157536580587504064549386047384679797317622140374619994217367156875051622001
Short name T170
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.83 seconds
Started Nov 22 03:07:46 PM PST 23
Finished Nov 22 03:08:36 PM PST 23
Peak memory 553392 kb
Host smart-3e64cdb5-6773-4e9f-9f44-ec00eb6071e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114157536580587504064549386047384679797317622140374619994217367156875051622001 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.114157536580587504064549386047384679797317622140374619994217367156875051622001
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_random.31014174007595962455246022368278239282691797456736524822192171035669275607275
Short name T1082
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.56 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:09:09 PM PST 23
Peak memory 553532 kb
Host smart-41442235-7d18-4c08-9687-515799e1c690
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31014174007595962455246022368278239282691797456736524822192171035669275607275 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 48.xbar_error_random.31014174007595962455246022368278239282691797456736524822192171035669275607275
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random.88486208064445714580779361491883617061735357167933738245619324453062141732751
Short name T1319
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.6 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:09:05 PM PST 23
Peak memory 553636 kb
Host smart-c8bac73a-fe40-40d4-9835-d7edaf738f10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88486208064445714580779361491883617061735357167933738245619324453062141732751 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 48.xbar_random.88486208064445714580779361491883617061735357167933738245619324453062141732751
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.51808883350795135639833100605223780912236745727611838790840874555793940210423
Short name T1086
Test name
Test status
Simulation time 97702135727 ps
CPU time 1158.61 seconds
Started Nov 22 03:07:47 PM PST 23
Finished Nov 22 03:27:09 PM PST 23
Peak memory 553588 kb
Host smart-0df32e86-37e4-4320-a849-fa951eb247be
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51808883350795135639833100605223780912236745727611838790840874555793940210423 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.51808883350795135639833100605223780912236745727611838790840874555793940210423
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.100836535947804725799514399873640911180766690988469325785202458472416924827131
Short name T749
Test name
Test status
Simulation time 60576345727 ps
CPU time 1088.45 seconds
Started Nov 22 03:07:50 PM PST 23
Finished Nov 22 03:26:00 PM PST 23
Peak memory 553728 kb
Host smart-f62a4382-072e-41b2-b415-083d2e487094
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100836535947804725799514399873640911180766690988469325785202458472416924827131 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.100836535947804725799514399873640911180766690988469325785202458472416924827131
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.11461813730615938463958639347508272522285139766130542243811601788160524740549
Short name T667
Test name
Test status
Simulation time 556965727 ps
CPU time 48.71 seconds
Started Nov 22 03:07:46 PM PST 23
Finished Nov 22 03:08:39 PM PST 23
Peak memory 553632 kb
Host smart-e6bf22b0-b7d9-4637-bb33-57dee9ddfec9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11461813730615938463958639347508272522285139766130542243811601788160524740549 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.11461813730615938463958639347508272522285139766130542243811601788160524740549
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_same_source.53357649654395097307266298847028532846830115197996299439376997948679579513499
Short name T1327
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.78 seconds
Started Nov 22 03:07:45 PM PST 23
Finished Nov 22 03:09:04 PM PST 23
Peak memory 553704 kb
Host smart-af85e62b-2939-4270-bb45-f980d58825e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53357649654395097307266298847028532846830115197996299439376997948679579513499 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.53357649654395097307266298847028532846830115197996299439376997948679579513499
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke.47144468448187956336730818072775529583673851922077354184042182230226370831779
Short name T773
Test name
Test status
Simulation time 196985727 ps
CPU time 8.83 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:08:01 PM PST 23
Peak memory 552376 kb
Host smart-2f449b01-3e87-4c32-b657-21dc1cbfa98b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47144468448187956336730818072775529583673851922077354184042182230226370831779 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 48.xbar_smoke.47144468448187956336730818072775529583673851922077354184042182230226370831779
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.105729442021316822946800532876632895995722012480158123281629539037610421068435
Short name T189
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.52 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:09:20 PM PST 23
Peak memory 552348 kb
Host smart-41c26ee2-a99c-4cbd-9a68-8f29e9fdefc5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105729442021316822946800532876632895995722012480158123281629539037610421068435 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.105729442021316822946800532876632895995722012480158123281629539037610421068435
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.85802464004805457807234244205721664113998652098206135218484485541515232231966
Short name T296
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.86 seconds
Started Nov 22 03:07:41 PM PST 23
Finished Nov 22 03:09:14 PM PST 23
Peak memory 552280 kb
Host smart-9539c8f7-c5b9-49e8-ab58-da5b670dbf87
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85802464004805457807234244205721664113998652098206135218484485541515232231966 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.85802464004805457807234244205721664113998652098206135218484485541515232231966
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.31578975131616179607930093500005299293395138484378358728180129194330002397365
Short name T701
Test name
Test status
Simulation time 45555727 ps
CPU time 5.85 seconds
Started Nov 22 03:07:48 PM PST 23
Finished Nov 22 03:07:57 PM PST 23
Peak memory 552288 kb
Host smart-7b442df9-405c-48ef-bede-9ebba4cc9164
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31578975131616179607930093500005299293395138484378358728180129194330002397365 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.31578975131616179607930093500005299293395138484378358728180129194330002397365
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all.30230533910118156206874114939229020877155515249720700645754903973228550358787
Short name T1763
Test name
Test status
Simulation time 13992004073 ps
CPU time 542.38 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:16:50 PM PST 23
Peak memory 555920 kb
Host smart-a9b8fbf3-b52b-44be-9118-5b8594c26f42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230533910118156206874114939229020877155515249720700645754903973228550358787 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.30230533910118156206874114939229020877155515249720700645754903973228550358787
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.94442920448269789088620633583033006120004462500871563968617621323775832106461
Short name T1691
Test name
Test status
Simulation time 13999524073 ps
CPU time 565.58 seconds
Started Nov 22 03:07:47 PM PST 23
Finished Nov 22 03:17:17 PM PST 23
Peak memory 555784 kb
Host smart-27da6b98-885f-43ae-a21e-891d980839de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94442920448269789088620633583033006120004462500871563968617621323775832106461 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.94442920448269789088620633583033006120004462500871563968617621323775832106461
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.22174792944856586488240248425942224728400849582454222400944791616510767635186
Short name T1856
Test name
Test status
Simulation time 4815189184 ps
CPU time 361.92 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:13:49 PM PST 23
Peak memory 557232 kb
Host smart-e069f2c2-304d-4317-b0a0-4677d5e38605
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22174792944856586488240248425942224728400849582454222400944791616510767635186 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.22174792944856586488240248425942224728400849582454222400944791
616510767635186
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.31809079590754186675089692331666877896314997977502302855106421702342759715930
Short name T668
Test name
Test status
Simulation time 4815189184 ps
CPU time 327.12 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:13:15 PM PST 23
Peak memory 559720 kb
Host smart-1dd62b3f-bc90-46b5-bb28-6c12d94f88b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31809079590754186675089692331666877896314997977502302855106421702342759715930 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.318090795907541866750896923316668778963149979775023028551064
21702342759715930
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.101188685483207890634196725313920832602866893840687440198976901926602186464084
Short name T1420
Test name
Test status
Simulation time 1176995727 ps
CPU time 43.3 seconds
Started Nov 22 03:07:46 PM PST 23
Finished Nov 22 03:08:32 PM PST 23
Peak memory 553744 kb
Host smart-03546258-f1e2-4fde-b1a9-c78fd5a2c72a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101188685483207890634196725313920832602866893840687440198976901926602186464084 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.101188685483207890634196725313920832602866893840687440198976901926602186464084
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device.39268745890173570962483191327970333551427588251828133479166901706088879062177
Short name T1685
Test name
Test status
Simulation time 2590995727 ps
CPU time 104.75 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:09:32 PM PST 23
Peak memory 554792 kb
Host smart-f125cf62-a312-4208-81fb-ea353b44662b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39268745890173570962483191327970333551427588251828133479166901706088879062177 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.39268745890173570962483191327970333551427588251828133479166901706088879062177
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.41385653194262801600832207550424400937649185806532181058611063463922582588784
Short name T1404
Test name
Test status
Simulation time 115195295727 ps
CPU time 1971.74 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:40:44 PM PST 23
Peak memory 554760 kb
Host smart-ef495781-7991-4672-b149-f895e854358c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41385653194262801600832207550424400937649185806532181058611063463922582588784 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.41385653194262801600832207550424400937649185806532181058611063463922582588784
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.52448254269394873681305261933992773929637372617218100790161393095918323451588
Short name T724
Test name
Test status
Simulation time 1171215727 ps
CPU time 41.24 seconds
Started Nov 22 03:08:09 PM PST 23
Finished Nov 22 03:08:51 PM PST 23
Peak memory 553452 kb
Host smart-87b8d09b-33e1-4676-93e7-7235a07a26e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52448254269394873681305261933992773929637372617218100790161393095918323451588 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.52448254269394873681305261933992773929637372617218100790161393095918323451588
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_random.38616516004257184314391574185581548207753050682661418456701862546240851247387
Short name T573
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.34 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:09:02 PM PST 23
Peak memory 553552 kb
Host smart-4a49afda-b6e2-4844-ba6b-1ea1aa35f5f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38616516004257184314391574185581548207753050682661418456701862546240851247387 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 49.xbar_error_random.38616516004257184314391574185581548207753050682661418456701862546240851247387
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random.39583494425678915578404497101363874996861731443174436895228664759965250796936
Short name T327
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.85 seconds
Started Nov 22 03:07:50 PM PST 23
Finished Nov 22 03:09:15 PM PST 23
Peak memory 553756 kb
Host smart-389ab72f-919f-4c86-bec6-0ab92322187b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39583494425678915578404497101363874996861731443174436895228664759965250796936 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 49.xbar_random.39583494425678915578404497101363874996861731443174436895228664759965250796936
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.78773364434943078656639949733080079506132979017167506785663378513799932351652
Short name T1707
Test name
Test status
Simulation time 97702135727 ps
CPU time 1177.89 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:27:25 PM PST 23
Peak memory 553632 kb
Host smart-51de2a14-0eb2-4242-b36d-ec76627ee766
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78773364434943078656639949733080079506132979017167506785663378513799932351652 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.78773364434943078656639949733080079506132979017167506785663378513799932351652
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.93744777492816016520558733276843821195118592222637825222835963664064026998342
Short name T993
Test name
Test status
Simulation time 60576345727 ps
CPU time 1137.38 seconds
Started Nov 22 03:07:47 PM PST 23
Finished Nov 22 03:26:48 PM PST 23
Peak memory 553724 kb
Host smart-456b5b3f-1dbb-4be2-960e-c6628b3750d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93744777492816016520558733276843821195118592222637825222835963664064026998342 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.93744777492816016520558733276843821195118592222637825222835963664064026998342
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.66442691403619973334762663630960801687232756002326397712316301318947495823710
Short name T1749
Test name
Test status
Simulation time 556965727 ps
CPU time 46.65 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:08:34 PM PST 23
Peak memory 553728 kb
Host smart-152ae9eb-c9b8-42ef-9eb5-b17d8a1b7c49
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66442691403619973334762663630960801687232756002326397712316301318947495823710 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.66442691403619973334762663630960801687232756002326397712316301318947495823710
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_same_source.50105104849732752620098875764585306842809896267468148714615105552898347869688
Short name T1210
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.94 seconds
Started Nov 22 03:07:45 PM PST 23
Finished Nov 22 03:09:03 PM PST 23
Peak memory 553780 kb
Host smart-56aa1794-1934-4918-b5e6-eff2c3911148
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50105104849732752620098875764585306842809896267468148714615105552898347869688 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.50105104849732752620098875764585306842809896267468148714615105552898347869688
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke.10097838787467804039328872267524792915879579315593928051143386139140140503798
Short name T164
Test name
Test status
Simulation time 196985727 ps
CPU time 9.07 seconds
Started Nov 22 03:07:47 PM PST 23
Finished Nov 22 03:08:00 PM PST 23
Peak memory 552424 kb
Host smart-09cc7bd1-bb56-46f3-a98c-42d76d3accde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10097838787467804039328872267524792915879579315593928051143386139140140503798 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 49.xbar_smoke.10097838787467804039328872267524792915879579315593928051143386139140140503798
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.72002123509587035610525860446983510463071738727055334856242499955462276886345
Short name T562
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.74 seconds
Started Nov 22 03:07:47 PM PST 23
Finished Nov 22 03:09:22 PM PST 23
Peak memory 552492 kb
Host smart-dee1336e-3c73-43b8-a1df-d9cdd67ec81f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72002123509587035610525860446983510463071738727055334856242499955462276886345 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.72002123509587035610525860446983510463071738727055334856242499955462276886345
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.105588567328337899263500078671232884806725000800174479458988731159363550429475
Short name T221
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.9 seconds
Started Nov 22 03:07:52 PM PST 23
Finished Nov 22 03:09:24 PM PST 23
Peak memory 552404 kb
Host smart-390fab44-5e5b-4692-8b81-10d5ba81a705
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105588567328337899263500078671232884806725000800174479458988731159363550429475 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.105588567328337899263500078671232884806725000800174479458988731159363550429475
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.83532463156025777169583911552215547394703490523128203625588859046890070912847
Short name T1919
Test name
Test status
Simulation time 45555727 ps
CPU time 6.25 seconds
Started Nov 22 03:07:44 PM PST 23
Finished Nov 22 03:07:54 PM PST 23
Peak memory 552348 kb
Host smart-afd9bd0a-40e7-452e-807d-0602c7319fb5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83532463156025777169583911552215547394703490523128203625588859046890070912847 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.83532463156025777169583911552215547394703490523128203625588859046890070912847
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all.80926347167879505360189875961977209757751631129953410576936114900126596638286
Short name T136
Test name
Test status
Simulation time 13992004073 ps
CPU time 535.62 seconds
Started Nov 22 03:07:55 PM PST 23
Finished Nov 22 03:16:51 PM PST 23
Peak memory 555884 kb
Host smart-a5151db6-8dd7-45e3-b949-c748759a230b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80926347167879505360189875961977209757751631129953410576936114900126596638286 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.80926347167879505360189875961977209757751631129953410576936114900126596638286
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.87838669298472665733602623754599954055306874906984991451777257571726744203733
Short name T1108
Test name
Test status
Simulation time 13999524073 ps
CPU time 513.22 seconds
Started Nov 22 03:07:51 PM PST 23
Finished Nov 22 03:16:26 PM PST 23
Peak memory 555708 kb
Host smart-1752c030-d25b-45bf-b808-f77ba56b981c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87838669298472665733602623754599954055306874906984991451777257571726744203733 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.87838669298472665733602623754599954055306874906984991451777257571726744203733
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.6253131943985817022090471642279208964658259784625013989965058807353782964866
Short name T1031
Test name
Test status
Simulation time 4815189184 ps
CPU time 372.11 seconds
Started Nov 22 03:08:09 PM PST 23
Finished Nov 22 03:14:22 PM PST 23
Peak memory 557204 kb
Host smart-5b93df2f-5f1a-4321-9510-13067360055b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6253131943985817022090471642279208964658259784625013989965058807353782964866 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.625313194398581702209047164227920896465825978462501398996505880
7353782964866
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.100745535001963514560425163281664813495552986335951172107644743861861313135885
Short name T1162
Test name
Test status
Simulation time 4815189184 ps
CPU time 334.98 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:13:27 PM PST 23
Peak memory 559672 kb
Host smart-89fefdaa-0c5c-48b6-a237-17d9207b4a99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100745535001963514560425163281664813495552986335951172107644743861861313135885 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.10074553500196351456042516328166481349555298633595117210764
4743861861313135885
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.82297548569918233992960098044517521027645234069323730717583280601353509127462
Short name T1683
Test name
Test status
Simulation time 1176995727 ps
CPU time 54.33 seconds
Started Nov 22 03:07:53 PM PST 23
Finished Nov 22 03:08:48 PM PST 23
Peak memory 553720 kb
Host smart-76983a58-98ab-4e51-bf3f-d86494d56ba3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82297548569918233992960098044517521027645234069323730717583280601353509127462 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.82297548569918233992960098044517521027645234069323730717583280601353509127462
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.89391720818051335631729134526079172347340760075552102864466002874019858600197
Short name T662
Test name
Test status
Simulation time 7234930891 ps
CPU time 302.12 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:08:43 PM PST 23
Peak memory 622520 kb
Host smart-ba9b14ce-0c8b-4579-950b-d37f7c4b4e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8939172081805133563172913452607
9172347340760075552102864466002874019858600197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.8939172081805
1335631729134526079172347340760075552102864466002874019858600197
Directory /workspace/5.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_rw.104882499271521305689434412901084680653425551791543809304542072742252963743296
Short name T1537
Test name
Test status
Simulation time 5924944675 ps
CPU time 495.44 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:11:57 PM PST 23
Peak memory 580492 kb
Host smart-fc95710b-fc28-4c98-bb96-c1c3fd2cd872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104882499271521305689434412901084680653425551791543809304542072742252963743296 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.104882499271521305689434412901084680653425551791543809304542072742252963743296
Directory /workspace/5.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.36047417079606425645217705313729586510788439114549571224525585445635231550397
Short name T963
Test name
Test status
Simulation time 30604932618 ps
CPU time 3097.58 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:55:10 PM PST 23
Peak memory 580320 kb
Host smart-7c3258ee-f28b-445d-bbe7-f45b717f4443
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604741707960642564521770531372958651
0788439114549571224525585445635231550397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.3604741707960642564521770
5313729586510788439114549571224525585445635231550397
Directory /workspace/5.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.chip_tl_errors.40603943937348658165259212320724149027451776434782890824184815585241029934429
Short name T1239
Test name
Test status
Simulation time 3069924257 ps
CPU time 177.62 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:06:35 PM PST 23
Peak memory 580608 kb
Host smart-a05a9eea-3b21-4c46-a6c1-bfb150b31847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603943937348658165259212320724149027451776434782890824184815585241029934429 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.40603943937348658165259212320724149027451776434782890824184815585241029934429
Directory /workspace/5.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device.13012081810015889014402193473319174607414613059379303605477952552715641126360
Short name T928
Test name
Test status
Simulation time 2590995727 ps
CPU time 96.41 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:05:18 PM PST 23
Peak memory 554820 kb
Host smart-67100496-136e-4971-a18e-db5bd6feccc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13012081810015889014402193473319174607414613059379303605477952552715641126360 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.13012081810015889014402193473319174607414613059379303605477952552715641126360
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.8480599824076444048936185225675075093327004481171819374706588447778786126537
Short name T1709
Test name
Test status
Simulation time 115195295727 ps
CPU time 2024.71 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:37:30 PM PST 23
Peak memory 554656 kb
Host smart-db9dde71-2cf4-49e8-bf0e-99f033f39aca
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8480599824076444048936185225675075093327004481171819374706588447778786126537 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.8480599824076444048936185225675075093327004481171819374706588447778786126537
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.104649652686004171520916751832966760047650094237760583338739844817328791137774
Short name T563
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.12 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:04:18 PM PST 23
Peak memory 553492 kb
Host smart-fcfe7b6e-709b-413c-b9bf-89197eea0e90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104649652686004171520916751832966760047650094237760583338739844817328791137774 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.104649652686004171520916751832966760047650094237760583338739844817328791137774
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_random.113698839240087380043472402396235381062944754519149537422968704301459919401484
Short name T1267
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.83 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:04:57 PM PST 23
Peak memory 553532 kb
Host smart-6f4b39b0-9b46-4192-9a7a-10c08defc060
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113698839240087380043472402396235381062944754519149537422968704301459919401484 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.xbar_error_random.113698839240087380043472402396235381062944754519149537422968704301459919401484
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random.73143597273396091562816485019440542210227330764589041050183109480105667699302
Short name T965
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.88 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:04:56 PM PST 23
Peak memory 553560 kb
Host smart-be972cd0-0b74-4466-a259-2a7a8dddc0fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73143597273396091562816485019440542210227330764589041050183109480105667699302 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.xbar_random.73143597273396091562816485019440542210227330764589041050183109480105667699302
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.24887778107869999501885243511619950559997778609839627696843436769045911733599
Short name T449
Test name
Test status
Simulation time 97702135727 ps
CPU time 1081.53 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:21:36 PM PST 23
Peak memory 553676 kb
Host smart-e3b46965-f85e-4ddb-8d57-9a23cb449d58
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887778107869999501885243511619950559997778609839627696843436769045911733599 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.24887778107869999501885243511619950559997778609839627696843436769045911733599
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.85420716780919009295746070390933314543168780508389643326127434556184306039334
Short name T635
Test name
Test status
Simulation time 60576345727 ps
CPU time 1004.7 seconds
Started Nov 22 03:03:42 PM PST 23
Finished Nov 22 03:20:28 PM PST 23
Peak memory 553672 kb
Host smart-68e1d58a-3b75-4c72-99ea-836702c0bea7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85420716780919009295746070390933314543168780508389643326127434556184306039334 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.85420716780919009295746070390933314543168780508389643326127434556184306039334
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.103263606620464162390740581280263808061792780551005776855239549959008565151351
Short name T1095
Test name
Test status
Simulation time 556965727 ps
CPU time 45.8 seconds
Started Nov 22 03:03:31 PM PST 23
Finished Nov 22 03:04:17 PM PST 23
Peak memory 553500 kb
Host smart-bd7081d3-ebc8-4d17-bcdb-0d92f504f626
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103263606620464162390740581280263808061792780551005776855239549959008565151351 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.103263606620464162390740581280263808061792780551005776855239549959008565151351
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_same_source.46752778322940239854386275452766841793537963192486139484395820993267620943103
Short name T159
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.92 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:04:51 PM PST 23
Peak memory 553724 kb
Host smart-6218d033-5106-411f-a19f-105427a9fa71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46752778322940239854386275452766841793537963192486139484395820993267620943103 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.46752778322940239854386275452766841793537963192486139484395820993267620943103
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke.104699606128401642824226889491015619450144481020699250089559508313586624262078
Short name T739
Test name
Test status
Simulation time 196985727 ps
CPU time 8.29 seconds
Started Nov 22 03:03:36 PM PST 23
Finished Nov 22 03:03:45 PM PST 23
Peak memory 552420 kb
Host smart-6930ff85-9578-466a-b3e0-6660367e6e1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104699606128401642824226889491015619450144481020699250089559508313586624262078 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.xbar_smoke.104699606128401642824226889491015619450144481020699250089559508313586624262078
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.94758757782177209114923019957716673686791310708367835481722448640714807720085
Short name T942
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.15 seconds
Started Nov 22 03:03:53 PM PST 23
Finished Nov 22 03:05:22 PM PST 23
Peak memory 552312 kb
Host smart-49dbac18-5fb2-4483-9c60-c844213aa3ef
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94758757782177209114923019957716673686791310708367835481722448640714807720085 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.94758757782177209114923019957716673686791310708367835481722448640714807720085
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.73251779196778024659829305507437413998816612554750195960739051789149975362485
Short name T908
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.65 seconds
Started Nov 22 03:03:35 PM PST 23
Finished Nov 22 03:04:56 PM PST 23
Peak memory 552324 kb
Host smart-cd35d1a8-2608-4e6a-ae0e-0a868cbe0eeb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73251779196778024659829305507437413998816612554750195960739051789149975362485 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.73251779196778024659829305507437413998816612554750195960739051789149975362485
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.51546943710531551794564410449955661184098849956486302425105366530513457982128
Short name T833
Test name
Test status
Simulation time 45555727 ps
CPU time 5.85 seconds
Started Nov 22 03:03:35 PM PST 23
Finished Nov 22 03:03:42 PM PST 23
Peak memory 552384 kb
Host smart-1f1071fb-1d4c-4e0e-a4fc-aebbf92f9485
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51546943710531551794564410449955661184098849956486302425105366530513457982128 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.51546943710531551794564410449955661184098849956486302425105366530513457982128
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all.64821584592160807640224610884358463004739878010015657981042393474760932506984
Short name T988
Test name
Test status
Simulation time 13992004073 ps
CPU time 545.22 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:12:46 PM PST 23
Peak memory 555900 kb
Host smart-224a5caf-0a25-4f0e-a944-18152190c993
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64821584592160807640224610884358463004739878010015657981042393474760932506984 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.64821584592160807640224610884358463004739878010015657981042393474760932506984
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.48974937951633023781827871228262749606397681429837897590941592517135565739978
Short name T1014
Test name
Test status
Simulation time 13999524073 ps
CPU time 518.72 seconds
Started Nov 22 03:03:52 PM PST 23
Finished Nov 22 03:12:31 PM PST 23
Peak memory 555720 kb
Host smart-ef03171e-4628-44c6-9642-317c276dd2f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48974937951633023781827871228262749606397681429837897590941592517135565739978 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.48974937951633023781827871228262749606397681429837897590941592517135565739978
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.102514838296989113822867497144952065104498713215212248319785465127217388286299
Short name T434
Test name
Test status
Simulation time 4815189184 ps
CPU time 360.34 seconds
Started Nov 22 03:03:53 PM PST 23
Finished Nov 22 03:09:54 PM PST 23
Peak memory 557180 kb
Host smart-92d66cb8-f78d-4574-96d8-86d597348bd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102514838296989113822867497144952065104498713215212248319785465127217388286299 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.10251483829698911382286749714495206510449871321521224831978546
5127217388286299
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.51581783785830231183894052206493719296645115638826157905032897607389365244563
Short name T46
Test name
Test status
Simulation time 4815189184 ps
CPU time 309 seconds
Started Nov 22 03:03:52 PM PST 23
Finished Nov 22 03:09:01 PM PST 23
Peak memory 559708 kb
Host smart-105d488f-1ad0-4708-8ba3-fc5fb5e2098d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51581783785830231183894052206493719296645115638826157905032897607389365244563 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.5158178378583023118389405220649371929664511563882615790503289
7607389365244563
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.24414078954959487192917600018831767455188036000103049461496646323180766155324
Short name T1776
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.74 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:04:34 PM PST 23
Peak memory 553600 kb
Host smart-6152c0ce-5a44-4d26-b2e0-459898245cd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24414078954959487192917600018831767455188036000103049461496646323180766155324 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.24414078954959487192917600018831767455188036000103049461496646323180766155324
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device.25732641527667112889081102679425940844693824893786129160167565142186928855625
Short name T150
Test name
Test status
Simulation time 2590995727 ps
CPU time 113.44 seconds
Started Nov 22 03:07:58 PM PST 23
Finished Nov 22 03:09:52 PM PST 23
Peak memory 554772 kb
Host smart-6656d820-49cd-4245-ac47-48207d8aa721
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25732641527667112889081102679425940844693824893786129160167565142186928855625 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device.25732641527667112889081102679425940844693824893786129160167565142186928855625
Directory /workspace/50.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2789954382428079371012495037797354674917010874189229078328441869980148742814
Short name T280
Test name
Test status
Simulation time 115195295727 ps
CPU time 2045.41 seconds
Started Nov 22 03:08:01 PM PST 23
Finished Nov 22 03:42:07 PM PST 23
Peak memory 554784 kb
Host smart-454ad997-2035-406a-9681-c9d20d724dfd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789954382428079371012495037797354674917010874189229078328441869980148742814 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device_slow_rsp.2789954382428079371012495037797354674917010874189229078328441869980148742814
Directory /workspace/50.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.43177605192802920503890291078705062861454554163174939925373168773954343712576
Short name T1298
Test name
Test status
Simulation time 1171215727 ps
CPU time 48.4 seconds
Started Nov 22 03:08:03 PM PST 23
Finished Nov 22 03:08:53 PM PST 23
Peak memory 553412 kb
Host smart-e6e717e4-ff28-49a1-9255-6a6beff70859
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43177605192802920503890291078705062861454554163174939925373168773954343712576 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr.43177605192802920503890291078705062861454554163174939925373168773954343712576
Directory /workspace/50.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_random.107780814331527341529126932536657601994152422438924500823418519643492163459713
Short name T1028
Test name
Test status
Simulation time 2231375727 ps
CPU time 66.44 seconds
Started Nov 22 03:08:10 PM PST 23
Finished Nov 22 03:09:17 PM PST 23
Peak memory 553512 kb
Host smart-a7fd3310-490f-4086-892e-0651f74fc9b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107780814331527341529126932536657601994152422438924500823418519643492163459713 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 50.xbar_error_random.107780814331527341529126932536657601994152422438924500823418519643492163459713
Directory /workspace/50.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random.69720011442352366958915502015041868262128001521037024534771163438610836547906
Short name T103
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.22 seconds
Started Nov 22 03:07:50 PM PST 23
Finished Nov 22 03:09:13 PM PST 23
Peak memory 553692 kb
Host smart-06242f7b-2e48-4dce-866e-3a294339c80d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69720011442352366958915502015041868262128001521037024534771163438610836547906 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 50.xbar_random.69720011442352366958915502015041868262128001521037024534771163438610836547906
Directory /workspace/50.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.92078289079683924545379483117373349074093872508048250153101013531759028038365
Short name T1051
Test name
Test status
Simulation time 97702135727 ps
CPU time 1087.44 seconds
Started Nov 22 03:08:09 PM PST 23
Finished Nov 22 03:26:17 PM PST 23
Peak memory 553636 kb
Host smart-a1bd4b21-718b-4e3b-9a91-dd1e5705f2ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92078289079683924545379483117373349074093872508048250153101013531759028038365 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.92078289079683924545379483117373349074093872508048250153101013531759028038365
Directory /workspace/50.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.51868797118552818882146407236160817619437211992994282027712687048806025096627
Short name T980
Test name
Test status
Simulation time 60576345727 ps
CPU time 1118.16 seconds
Started Nov 22 03:08:01 PM PST 23
Finished Nov 22 03:26:40 PM PST 23
Peak memory 553652 kb
Host smart-bd7b8dc9-554f-49ef-922d-660955e1d0b5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51868797118552818882146407236160817619437211992994282027712687048806025096627 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.51868797118552818882146407236160817619437211992994282027712687048806025096627
Directory /workspace/50.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.22741698647769326723793445869677341093250180592639542841497065426627726308464
Short name T414
Test name
Test status
Simulation time 556965727 ps
CPU time 44.39 seconds
Started Nov 22 03:07:49 PM PST 23
Finished Nov 22 03:08:36 PM PST 23
Peak memory 553616 kb
Host smart-f016b292-92eb-4a0f-b915-ba0b28fdded7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22741698647769326723793445869677341093250180592639542841497065426627726308464 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_delays.22741698647769326723793445869677341093250180592639542841497065426627726308464
Directory /workspace/50.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_same_source.677627066191381511101660856410991506425909474056558194072020630975819495903
Short name T69
Test name
Test status
Simulation time 2498784073 ps
CPU time 74.73 seconds
Started Nov 22 03:07:59 PM PST 23
Finished Nov 22 03:09:14 PM PST 23
Peak memory 553708 kb
Host smart-6909a998-f0ce-4c28-8cce-14e1cb141b88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677627066191381511101660856410991506425909474056558194072020630975819495903 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.677627066191381511101660856410991506425909474056558194072020630975819495903
Directory /workspace/50.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke.97651944789323308106730308816628322627703794568868585913716138174981470720225
Short name T569
Test name
Test status
Simulation time 196985727 ps
CPU time 8.13 seconds
Started Nov 22 03:08:09 PM PST 23
Finished Nov 22 03:08:18 PM PST 23
Peak memory 552336 kb
Host smart-8f063e71-3a2b-4555-a671-8b9b9e58c24d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97651944789323308106730308816628322627703794568868585913716138174981470720225 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 50.xbar_smoke.97651944789323308106730308816628322627703794568868585913716138174981470720225
Directory /workspace/50.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.7640037914544889320605968673988071189160811900961482177120740492628965354351
Short name T95
Test name
Test status
Simulation time 7758585727 ps
CPU time 87.24 seconds
Started Nov 22 03:07:56 PM PST 23
Finished Nov 22 03:09:23 PM PST 23
Peak memory 552360 kb
Host smart-c660153c-21a7-4970-9a7a-d660bedb64c4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7640037914544889320605968673988071189160811900961482177120740492628965354351 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.7640037914544889320605968673988071189160811900961482177120740492628965354351
Directory /workspace/50.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.58565286201634101042107357023204320539501962577532045209261651541733698857575
Short name T1148
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.54 seconds
Started Nov 22 03:07:51 PM PST 23
Finished Nov 22 03:09:21 PM PST 23
Peak memory 552392 kb
Host smart-05bd6e31-ba95-4e87-b0d7-b6d8c73d3f7e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58565286201634101042107357023204320539501962577532045209261651541733698857575 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.58565286201634101042107357023204320539501962577532045209261651541733698857575
Directory /workspace/50.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.8542138290358045650021164834629481674490979284172664912843642285610296948594
Short name T93
Test name
Test status
Simulation time 45555727 ps
CPU time 5.79 seconds
Started Nov 22 03:07:55 PM PST 23
Finished Nov 22 03:08:02 PM PST 23
Peak memory 552336 kb
Host smart-e78bdb06-af0c-4cab-a189-da12bb7f2450
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8542138290358045650021164834629481674490979284172664912843642285610296948594 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.8542138290358045650021164834629481674490979284172664912843642285610296948594
Directory /workspace/50.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all.53747572716790545598972446800408701194778691752755768244786139700108448794301
Short name T1461
Test name
Test status
Simulation time 13992004073 ps
CPU time 556.78 seconds
Started Nov 22 03:07:57 PM PST 23
Finished Nov 22 03:17:15 PM PST 23
Peak memory 555916 kb
Host smart-83001643-1428-4f5a-8417-c012b0bbada6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53747572716790545598972446800408701194778691752755768244786139700108448794301 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.53747572716790545598972446800408701194778691752755768244786139700108448794301
Directory /workspace/50.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.114544521274452246051675615364981403803327847266570871067818801352765345147764
Short name T281
Test name
Test status
Simulation time 13999524073 ps
CPU time 488.22 seconds
Started Nov 22 03:08:03 PM PST 23
Finished Nov 22 03:16:11 PM PST 23
Peak memory 555724 kb
Host smart-56b89468-a0ee-4ef9-ac22-7908672c6fe8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114544521274452246051675615364981403803327847266570871067818801352765345147764 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.114544521274452246051675615364981403803327847266570871067818801352765345147764
Directory /workspace/50.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.48914426058557401416685716413718158452284033909412130707568529346866891877193
Short name T1597
Test name
Test status
Simulation time 4815189184 ps
CPU time 390.25 seconds
Started Nov 22 03:08:02 PM PST 23
Finished Nov 22 03:14:33 PM PST 23
Peak memory 557204 kb
Host smart-ac270392-00f2-46d6-922a-1ec9c70877bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48914426058557401416685716413718158452284033909412130707568529346866891877193 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_rand_reset.48914426058557401416685716413718158452284033909412130707568529
346866891877193
Directory /workspace/50.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.73689887141507213523733322656401816738516123185458294700833151003108139777646
Short name T123
Test name
Test status
Simulation time 4815189184 ps
CPU time 307.53 seconds
Started Nov 22 03:08:01 PM PST 23
Finished Nov 22 03:13:09 PM PST 23
Peak memory 559708 kb
Host smart-ca70e422-0495-4076-b844-ee1c57870406
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73689887141507213523733322656401816738516123185458294700833151003108139777646 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_reset_error.736898871415072135237333226564018167385161231854582947008331
51003108139777646
Directory /workspace/50.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.31615693625217065961243403506892887088763332847843383289178163278173409456789
Short name T1926
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.38 seconds
Started Nov 22 03:07:58 PM PST 23
Finished Nov 22 03:08:49 PM PST 23
Peak memory 553816 kb
Host smart-3ad3ce94-3ea3-4306-b32e-eaa857346c3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615693625217065961243403506892887088763332847843383289178163278173409456789 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.31615693625217065961243403506892887088763332847843383289178163278173409456789
Directory /workspace/50.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device.69488750728662572935862590458691821336755752509148904459202105135317837894469
Short name T1220
Test name
Test status
Simulation time 2590995727 ps
CPU time 113.12 seconds
Started Nov 22 03:07:58 PM PST 23
Finished Nov 22 03:09:51 PM PST 23
Peak memory 554800 kb
Host smart-23e9d665-360f-4c23-95ac-119adee11eb1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69488750728662572935862590458691821336755752509148904459202105135317837894469 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device.69488750728662572935862590458691821336755752509148904459202105135317837894469
Directory /workspace/51.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.78751578153062590459089642989987030079054930135825478384734577850331821879932
Short name T1633
Test name
Test status
Simulation time 115195295727 ps
CPU time 1963.68 seconds
Started Nov 22 03:07:57 PM PST 23
Finished Nov 22 03:40:41 PM PST 23
Peak memory 554764 kb
Host smart-23de416c-07c6-43c1-a648-f1e6315e838b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78751578153062590459089642989987030079054930135825478384734577850331821879932 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device_slow_rsp.78751578153062590459089642989987030079054930135825478384734577850331821879932
Directory /workspace/51.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.102831914378155575375184284476978832337962526266335657763439033235574040956978
Short name T431
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.47 seconds
Started Nov 22 03:08:14 PM PST 23
Finished Nov 22 03:09:00 PM PST 23
Peak memory 553484 kb
Host smart-0e5dbbe8-4d5d-4e10-951b-471ae2cfa8f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102831914378155575375184284476978832337962526266335657763439033235574040956978 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr.102831914378155575375184284476978832337962526266335657763439033235574040956978
Directory /workspace/51.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_random.72930498278163499569657227260840744845432472089766477573879130646281221392846
Short name T1067
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.86 seconds
Started Nov 22 03:08:22 PM PST 23
Finished Nov 22 03:09:38 PM PST 23
Peak memory 553564 kb
Host smart-755e65c5-9911-46fb-9bd6-ccde62faedac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72930498278163499569657227260840744845432472089766477573879130646281221392846 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 51.xbar_error_random.72930498278163499569657227260840744845432472089766477573879130646281221392846
Directory /workspace/51.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random.89180275785234860902001251532160736830937830809827699071276312009163836517669
Short name T316
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.21 seconds
Started Nov 22 03:08:00 PM PST 23
Finished Nov 22 03:09:22 PM PST 23
Peak memory 553672 kb
Host smart-6595e5c1-d1de-416d-af13-375534836868
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89180275785234860902001251532160736830937830809827699071276312009163836517669 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 51.xbar_random.89180275785234860902001251532160736830937830809827699071276312009163836517669
Directory /workspace/51.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.895394853263242224901821009894557754777940315758764950811968518729042565731
Short name T706
Test name
Test status
Simulation time 97702135727 ps
CPU time 1165.61 seconds
Started Nov 22 03:07:59 PM PST 23
Finished Nov 22 03:27:26 PM PST 23
Peak memory 553664 kb
Host smart-f3809556-227f-4e7e-84dd-a3bd140b1654
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895394853263242224901821009894557754777940315758764950811968518729042565731 -assert nopostp
roc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.895394853263242224901821009894557754777940315758764950811968518729042565731
Directory /workspace/51.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.98561303618633535797311120846713010423639801189193106851945649218301897246465
Short name T1570
Test name
Test status
Simulation time 60576345727 ps
CPU time 1133.58 seconds
Started Nov 22 03:08:00 PM PST 23
Finished Nov 22 03:26:55 PM PST 23
Peak memory 553640 kb
Host smart-be2a00a1-4ad2-4f27-9e79-3e4e8d7529f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98561303618633535797311120846713010423639801189193106851945649218301897246465 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.98561303618633535797311120846713010423639801189193106851945649218301897246465
Directory /workspace/51.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.107738727515237850511627389013163388696236206874473666827437711748158777684246
Short name T80
Test name
Test status
Simulation time 556965727 ps
CPU time 42.98 seconds
Started Nov 22 03:08:09 PM PST 23
Finished Nov 22 03:08:53 PM PST 23
Peak memory 553676 kb
Host smart-008f0c32-bf8d-479d-8129-334eae3d66f3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107738727515237850511627389013163388696236206874473666827437711748158777684246 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_delays.107738727515237850511627389013163388696236206874473666827437711748158777684246
Directory /workspace/51.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_same_source.78629847332512573586226409044451702997749070377224980441053008460538700354546
Short name T1083
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.23 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:09:46 PM PST 23
Peak memory 553760 kb
Host smart-b83c8f07-5c26-4af0-ba39-f6ed30c69da8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78629847332512573586226409044451702997749070377224980441053008460538700354546 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.78629847332512573586226409044451702997749070377224980441053008460538700354546
Directory /workspace/51.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke.100339140850008443633214366765652461063156163694511785884744155707976630042724
Short name T1875
Test name
Test status
Simulation time 196985727 ps
CPU time 8.07 seconds
Started Nov 22 03:07:57 PM PST 23
Finished Nov 22 03:08:06 PM PST 23
Peak memory 552324 kb
Host smart-df307880-9ee8-4df8-a6a6-b92ab628cabc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100339140850008443633214366765652461063156163694511785884744155707976630042724 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 51.xbar_smoke.100339140850008443633214366765652461063156163694511785884744155707976630042724
Directory /workspace/51.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.24735348623638730666431052670347337113838177500979539686484095157410238287870
Short name T317
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.87 seconds
Started Nov 22 03:07:58 PM PST 23
Finished Nov 22 03:09:27 PM PST 23
Peak memory 552384 kb
Host smart-f073bdb2-8e3d-409a-ae58-ac37e59608ce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24735348623638730666431052670347337113838177500979539686484095157410238287870 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.24735348623638730666431052670347337113838177500979539686484095157410238287870
Directory /workspace/51.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.72912645333413981782802024261075441069753686977653187422099073174412777527100
Short name T613
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.99 seconds
Started Nov 22 03:08:00 PM PST 23
Finished Nov 22 03:09:25 PM PST 23
Peak memory 552280 kb
Host smart-53a0cd41-1c83-439b-86bc-8b562314eaa3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72912645333413981782802024261075441069753686977653187422099073174412777527100 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.72912645333413981782802024261075441069753686977653187422099073174412777527100
Directory /workspace/51.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.79723870779118130402208260506543456505194659236057431880528459944551486393865
Short name T1058
Test name
Test status
Simulation time 45555727 ps
CPU time 6.29 seconds
Started Nov 22 03:07:59 PM PST 23
Finished Nov 22 03:08:06 PM PST 23
Peak memory 552360 kb
Host smart-7479e483-43f6-4906-a7a5-edbd63a3e2c0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79723870779118130402208260506543456505194659236057431880528459944551486393865 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays.79723870779118130402208260506543456505194659236057431880528459944551486393865
Directory /workspace/51.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all.39340026143889630525920590006603895274282939959350205095164899588969161162100
Short name T1339
Test name
Test status
Simulation time 13992004073 ps
CPU time 567.49 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:17:58 PM PST 23
Peak memory 555840 kb
Host smart-4c1edb5a-0eea-48e4-8c77-c60aec92203b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39340026143889630525920590006603895274282939959350205095164899588969161162100 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.39340026143889630525920590006603895274282939959350205095164899588969161162100
Directory /workspace/51.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.6485334051470267268575687662169968561600066851667579671655028622632511745815
Short name T618
Test name
Test status
Simulation time 13999524073 ps
CPU time 488.52 seconds
Started Nov 22 03:08:23 PM PST 23
Finished Nov 22 03:16:32 PM PST 23
Peak memory 555724 kb
Host smart-5dd6a35f-70ba-4841-bdf6-f4bae7afd232
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6485334051470267268575687662169968561600066851667579671655028622632511745815 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.6485334051470267268575687662169968561600066851667579671655028622632511745815
Directory /workspace/51.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.15497401013798477468366282333392729011247008093107729013513052902009498491220
Short name T685
Test name
Test status
Simulation time 4815189184 ps
CPU time 396.72 seconds
Started Nov 22 03:08:21 PM PST 23
Finished Nov 22 03:14:59 PM PST 23
Peak memory 557236 kb
Host smart-176a810c-077c-44f4-9838-016e49aeabb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15497401013798477468366282333392729011247008093107729013513052902009498491220 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_rand_reset.15497401013798477468366282333392729011247008093107729013513052
902009498491220
Directory /workspace/51.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.89197667720632700180221962934101048654677867975903524096366803568447716025955
Short name T752
Test name
Test status
Simulation time 4815189184 ps
CPU time 313.29 seconds
Started Nov 22 03:08:25 PM PST 23
Finished Nov 22 03:13:39 PM PST 23
Peak memory 559708 kb
Host smart-d09bf52d-ed3e-4ab6-a6ee-4acfb51a3147
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89197667720632700180221962934101048654677867975903524096366803568447716025955 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_reset_error.891976677206327001802219629341010486546778679759035240963668
03568447716025955
Directory /workspace/51.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.18823049660958826225837578308326677097158242877627721700384908535630064659197
Short name T1406
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.62 seconds
Started Nov 22 03:08:21 PM PST 23
Finished Nov 22 03:09:09 PM PST 23
Peak memory 553752 kb
Host smart-449de5b9-be74-4ab0-9112-66e37ed7c424
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18823049660958826225837578308326677097158242877627721700384908535630064659197 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.18823049660958826225837578308326677097158242877627721700384908535630064659197
Directory /workspace/51.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device.27630870959840847980376146996159663927967347845111798680001058503155677279302
Short name T972
Test name
Test status
Simulation time 2590995727 ps
CPU time 114.97 seconds
Started Nov 22 03:08:22 PM PST 23
Finished Nov 22 03:10:17 PM PST 23
Peak memory 554788 kb
Host smart-9fac8afb-107b-477f-a915-c7d4833b1913
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27630870959840847980376146996159663927967347845111798680001058503155677279302 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device.27630870959840847980376146996159663927967347845111798680001058503155677279302
Directory /workspace/52.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.54338548121347458213321329272668424257729114792599877455328420373888703915747
Short name T755
Test name
Test status
Simulation time 115195295727 ps
CPU time 2066.7 seconds
Started Nov 22 03:08:31 PM PST 23
Finished Nov 22 03:42:59 PM PST 23
Peak memory 554724 kb
Host smart-9cc68904-b477-46b5-83a4-215305a24131
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54338548121347458213321329272668424257729114792599877455328420373888703915747 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device_slow_rsp.54338548121347458213321329272668424257729114792599877455328420373888703915747
Directory /workspace/52.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.54180655733929697631440377843690595617463209480183196788560756126888048212235
Short name T140
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.03 seconds
Started Nov 22 03:08:33 PM PST 23
Finished Nov 22 03:09:19 PM PST 23
Peak memory 553500 kb
Host smart-e7049a64-a1f5-49bb-9899-d387a4fd0242
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54180655733929697631440377843690595617463209480183196788560756126888048212235 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr.54180655733929697631440377843690595617463209480183196788560756126888048212235
Directory /workspace/52.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_random.37216899056019283748168847304938308915266099034392653084645265297163269229771
Short name T508
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.19 seconds
Started Nov 22 03:08:32 PM PST 23
Finished Nov 22 03:09:44 PM PST 23
Peak memory 553496 kb
Host smart-23003676-dee7-45d7-a7ff-a5366eb91712
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216899056019283748168847304938308915266099034392653084645265297163269229771 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 52.xbar_error_random.37216899056019283748168847304938308915266099034392653084645265297163269229771
Directory /workspace/52.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random.112377542354947155804777870681721311169431538299520932092208045879602662968248
Short name T1168
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.62 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:09:51 PM PST 23
Peak memory 553768 kb
Host smart-adbab58f-1cd7-4768-b410-e7ededf8baaa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112377542354947155804777870681721311169431538299520932092208045879602662968248 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 52.xbar_random.112377542354947155804777870681721311169431538299520932092208045879602662968248
Directory /workspace/52.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.13145067536514935875530717433801628829178623317270648611128232698439281434962
Short name T83
Test name
Test status
Simulation time 97702135727 ps
CPU time 1173.54 seconds
Started Nov 22 03:08:23 PM PST 23
Finished Nov 22 03:27:58 PM PST 23
Peak memory 553684 kb
Host smart-fbbec247-0a2f-4a1d-8605-89dd60834144
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13145067536514935875530717433801628829178623317270648611128232698439281434962 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.13145067536514935875530717433801628829178623317270648611128232698439281434962
Directory /workspace/52.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.20845478005503607158022828051172558927775415529975878454899371338864038488558
Short name T692
Test name
Test status
Simulation time 60576345727 ps
CPU time 1122.02 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:27:09 PM PST 23
Peak memory 553708 kb
Host smart-764e6802-ce16-4c5d-a36d-4d64a47cea1f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20845478005503607158022828051172558927775415529975878454899371338864038488558 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.20845478005503607158022828051172558927775415529975878454899371338864038488558
Directory /workspace/52.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.40762206601094882628001485678704600883993031982556571461482571023130170346564
Short name T457
Test name
Test status
Simulation time 556965727 ps
CPU time 46.64 seconds
Started Nov 22 03:08:13 PM PST 23
Finished Nov 22 03:09:01 PM PST 23
Peak memory 553732 kb
Host smart-eda764a4-c85c-4925-9321-8868daf964da
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40762206601094882628001485678704600883993031982556571461482571023130170346564 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delays.40762206601094882628001485678704600883993031982556571461482571023130170346564
Directory /workspace/52.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_same_source.63112243159791343634202606060726321853953836626828196106919547258991162174243
Short name T1070
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.75 seconds
Started Nov 22 03:08:21 PM PST 23
Finished Nov 22 03:09:38 PM PST 23
Peak memory 553716 kb
Host smart-ff25e267-c1e2-45c7-9b8d-d6f186e9dcdf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63112243159791343634202606060726321853953836626828196106919547258991162174243 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.63112243159791343634202606060726321853953836626828196106919547258991162174243
Directory /workspace/52.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke.78734232407875690335819242388718873338587355676044765151739608622148686481230
Short name T597
Test name
Test status
Simulation time 196985727 ps
CPU time 8.74 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:08:43 PM PST 23
Peak memory 552380 kb
Host smart-c34eb033-67d8-4a29-925f-21cdfdc1accc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78734232407875690335819242388718873338587355676044765151739608622148686481230 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 52.xbar_smoke.78734232407875690335819242388718873338587355676044765151739608622148686481230
Directory /workspace/52.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.37816640559975724288889732508097866042285448875246831490010759584874478046667
Short name T162
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.07 seconds
Started Nov 22 03:08:22 PM PST 23
Finished Nov 22 03:09:55 PM PST 23
Peak memory 552392 kb
Host smart-3065cb56-2c6f-4ab9-a318-05bcf8952817
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37816640559975724288889732508097866042285448875246831490010759584874478046667 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.37816640559975724288889732508097866042285448875246831490010759584874478046667
Directory /workspace/52.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.42020520558219547575271878680066797117331640906753276329043267286027148568113
Short name T1209
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.27 seconds
Started Nov 22 03:08:16 PM PST 23
Finished Nov 22 03:09:45 PM PST 23
Peak memory 552364 kb
Host smart-06beac7a-9ffb-4b0c-889b-994f3ffce9b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020520558219547575271878680066797117331640906753276329043267286027148568113 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.42020520558219547575271878680066797117331640906753276329043267286027148568113
Directory /workspace/52.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.13233833718104843101590655055715142714050006170764732825934176886754674647127
Short name T1367
Test name
Test status
Simulation time 45555727 ps
CPU time 6.25 seconds
Started Nov 22 03:08:21 PM PST 23
Finished Nov 22 03:08:28 PM PST 23
Peak memory 552360 kb
Host smart-cd912745-5257-41ee-bcb8-247fa7cf8de4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233833718104843101590655055715142714050006170764732825934176886754674647127 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.13233833718104843101590655055715142714050006170764732825934176886754674647127
Directory /workspace/52.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all.49083532862902304120317977651864907115417972407747684274060924013790325978389
Short name T1672
Test name
Test status
Simulation time 13992004073 ps
CPU time 545.86 seconds
Started Nov 22 03:08:25 PM PST 23
Finished Nov 22 03:17:32 PM PST 23
Peak memory 555876 kb
Host smart-5f5c7a18-f70b-4197-928a-dddffb3bc27c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49083532862902304120317977651864907115417972407747684274060924013790325978389 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.49083532862902304120317977651864907115417972407747684274060924013790325978389
Directory /workspace/52.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.76842842603903043331585911107146730368041519612340740333662383926947028119230
Short name T1650
Test name
Test status
Simulation time 13999524073 ps
CPU time 507.28 seconds
Started Nov 22 03:08:21 PM PST 23
Finished Nov 22 03:16:49 PM PST 23
Peak memory 555820 kb
Host smart-bf286040-1879-473d-a20d-4732ebc510e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76842842603903043331585911107146730368041519612340740333662383926947028119230 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.76842842603903043331585911107146730368041519612340740333662383926947028119230
Directory /workspace/52.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.7807728264319398547582892369431059518133315223296812447939090164426780483911
Short name T392
Test name
Test status
Simulation time 4815189184 ps
CPU time 358.11 seconds
Started Nov 22 03:08:12 PM PST 23
Finished Nov 22 03:14:11 PM PST 23
Peak memory 557244 kb
Host smart-7ec36e02-c4be-4490-8909-c1a53e66d077
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7807728264319398547582892369431059518133315223296812447939090164426780483911 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_rand_reset.780772826431939854758289236943105951813331522329681244793909016
4426780483911
Directory /workspace/52.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.10673769442105315059385443220606853970338764346258722072268641300980259798608
Short name T1743
Test name
Test status
Simulation time 4815189184 ps
CPU time 324.4 seconds
Started Nov 22 03:08:20 PM PST 23
Finished Nov 22 03:13:45 PM PST 23
Peak memory 559720 kb
Host smart-6acfca75-7743-46e7-95f4-4916cc92ef4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10673769442105315059385443220606853970338764346258722072268641300980259798608 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_reset_error.106737694421053150593854432206068539703387643462587220722686
41300980259798608
Directory /workspace/52.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.65434047270791409361505052417504994383970480517875815192651933923438550640796
Short name T737
Test name
Test status
Simulation time 1176995727 ps
CPU time 52.86 seconds
Started Nov 22 03:08:21 PM PST 23
Finished Nov 22 03:09:14 PM PST 23
Peak memory 553648 kb
Host smart-5c739feb-163d-4649-84f0-b6e01a9b5e49
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65434047270791409361505052417504994383970480517875815192651933923438550640796 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.65434047270791409361505052417504994383970480517875815192651933923438550640796
Directory /workspace/52.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device.111282302135288568270145247758609990006465015500315173417273044126189390054339
Short name T1591
Test name
Test status
Simulation time 2590995727 ps
CPU time 108.99 seconds
Started Nov 22 03:08:22 PM PST 23
Finished Nov 22 03:10:11 PM PST 23
Peak memory 554736 kb
Host smart-82093eb0-56c3-4504-bf35-bbd1a2007113
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111282302135288568270145247758609990006465015500315173417273044126189390054339 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device.111282302135288568270145247758609990006465015500315173417273044126189390054339
Directory /workspace/53.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.25298544633753861176146425520253937951517783834839870680535831044138739862065
Short name T536
Test name
Test status
Simulation time 115195295727 ps
CPU time 2001.28 seconds
Started Nov 22 03:08:14 PM PST 23
Finished Nov 22 03:41:37 PM PST 23
Peak memory 554864 kb
Host smart-4dc07501-ee09-4d2e-96e2-4069a54356f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25298544633753861176146425520253937951517783834839870680535831044138739862065 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device_slow_rsp.25298544633753861176146425520253937951517783834839870680535831044138739862065
Directory /workspace/53.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.96580674770409235075350286885323509176905438398732308215467390266547361635393
Short name T507
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.55 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:09:18 PM PST 23
Peak memory 553396 kb
Host smart-2162c064-2643-46cd-919e-cd4932ca655d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96580674770409235075350286885323509176905438398732308215467390266547361635393 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr.96580674770409235075350286885323509176905438398732308215467390266547361635393
Directory /workspace/53.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_random.33168937839568656594845165426343899680847191510470883515309065021018510665246
Short name T238
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.13 seconds
Started Nov 22 03:08:14 PM PST 23
Finished Nov 22 03:09:32 PM PST 23
Peak memory 553544 kb
Host smart-2016b54d-b59d-412f-8828-2967dbe3f348
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33168937839568656594845165426343899680847191510470883515309065021018510665246 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 53.xbar_error_random.33168937839568656594845165426343899680847191510470883515309065021018510665246
Directory /workspace/53.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random.67480649171325498199419694404599944218682188266474477091197726790057640198251
Short name T1463
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.42 seconds
Started Nov 22 03:08:27 PM PST 23
Finished Nov 22 03:09:45 PM PST 23
Peak memory 553844 kb
Host smart-2ed97df4-0b3f-4fc0-a897-0d782599eabb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67480649171325498199419694404599944218682188266474477091197726790057640198251 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 53.xbar_random.67480649171325498199419694404599944218682188266474477091197726790057640198251
Directory /workspace/53.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.40277484627605503364909307608186260168042091861806465420147017211397769905229
Short name T1457
Test name
Test status
Simulation time 97702135727 ps
CPU time 1141.64 seconds
Started Nov 22 03:08:20 PM PST 23
Finished Nov 22 03:27:22 PM PST 23
Peak memory 553660 kb
Host smart-facbadd1-729d-4f46-81ca-4e1e4ee00198
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40277484627605503364909307608186260168042091861806465420147017211397769905229 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.40277484627605503364909307608186260168042091861806465420147017211397769905229
Directory /workspace/53.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.67467984349866589531680086065334386260336935924727463602784331927868904841096
Short name T58
Test name
Test status
Simulation time 60576345727 ps
CPU time 1141.25 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:27:32 PM PST 23
Peak memory 553720 kb
Host smart-b446c1cc-60d5-4274-b054-549ca3d38547
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67467984349866589531680086065334386260336935924727463602784331927868904841096 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.67467984349866589531680086065334386260336935924727463602784331927868904841096
Directory /workspace/53.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.65014611629539533137300321066759147019334303712497369543781132375393402000469
Short name T445
Test name
Test status
Simulation time 556965727 ps
CPU time 48.14 seconds
Started Nov 22 03:08:14 PM PST 23
Finished Nov 22 03:09:03 PM PST 23
Peak memory 553688 kb
Host smart-bde41433-d90d-48f5-ac75-0b8c665e484e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65014611629539533137300321066759147019334303712497369543781132375393402000469 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_delays.65014611629539533137300321066759147019334303712497369543781132375393402000469
Directory /workspace/53.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_same_source.101980302028148885710166662908712870553393516202058673176837389154657907494330
Short name T1180
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.07 seconds
Started Nov 22 03:08:21 PM PST 23
Finished Nov 22 03:09:34 PM PST 23
Peak memory 553708 kb
Host smart-840a7907-878b-43a1-965b-83bf736a5f3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101980302028148885710166662908712870553393516202058673176837389154657907494330 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.101980302028148885710166662908712870553393516202058673176837389154657907494330
Directory /workspace/53.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke.114330444400377216071397739654134190900187884090891943777713947716727383707562
Short name T610
Test name
Test status
Simulation time 196985727 ps
CPU time 9.02 seconds
Started Nov 22 03:08:14 PM PST 23
Finished Nov 22 03:08:24 PM PST 23
Peak memory 552384 kb
Host smart-335f36aa-b611-43ba-93aa-4dfb038c3d24
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114330444400377216071397739654134190900187884090891943777713947716727383707562 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 53.xbar_smoke.114330444400377216071397739654134190900187884090891943777713947716727383707562
Directory /workspace/53.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.11628062251059514682154602988641239989643139699198940183106204111164667725831
Short name T1259
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.42 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:09:55 PM PST 23
Peak memory 552476 kb
Host smart-ea642d6c-ca68-4c6f-8273-c80a127bf3cb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11628062251059514682154602988641239989643139699198940183106204111164667725831 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.11628062251059514682154602988641239989643139699198940183106204111164667725831
Directory /workspace/53.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.79332197030217538905699677670323171585026770018783465449694314831839209279916
Short name T1786
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.26 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:09:53 PM PST 23
Peak memory 552408 kb
Host smart-63d608a7-e9d2-4735-a818-879faf0ff5d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79332197030217538905699677670323171585026770018783465449694314831839209279916 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.79332197030217538905699677670323171585026770018783465449694314831839209279916
Directory /workspace/53.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.52259438624858591878790105784354431912141268290170835086536550279015069367152
Short name T289
Test name
Test status
Simulation time 45555727 ps
CPU time 6.63 seconds
Started Nov 22 03:08:38 PM PST 23
Finished Nov 22 03:08:45 PM PST 23
Peak memory 552220 kb
Host smart-7fc9c455-5956-48b6-a8d1-7d1f8523e65c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52259438624858591878790105784354431912141268290170835086536550279015069367152 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays.52259438624858591878790105784354431912141268290170835086536550279015069367152
Directory /workspace/53.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all.40028762596126129476361271806011828636658927244702605519725711454209597281180
Short name T1888
Test name
Test status
Simulation time 13992004073 ps
CPU time 562.66 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:17:50 PM PST 23
Peak memory 555896 kb
Host smart-f5deedba-4ab0-4b12-9441-3404cc907793
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40028762596126129476361271806011828636658927244702605519725711454209597281180 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.40028762596126129476361271806011828636658927244702605519725711454209597281180
Directory /workspace/53.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.48859821407714578582067175811849556908767447091603489254072342145996339546170
Short name T1076
Test name
Test status
Simulation time 13999524073 ps
CPU time 511.26 seconds
Started Nov 22 03:08:20 PM PST 23
Finished Nov 22 03:16:52 PM PST 23
Peak memory 555680 kb
Host smart-9658b6f3-a1ab-4c31-ba1b-60e470b52306
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48859821407714578582067175811849556908767447091603489254072342145996339546170 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.48859821407714578582067175811849556908767447091603489254072342145996339546170
Directory /workspace/53.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.66267982830013355255265084696149327887305819039322655484325812102709877536976
Short name T1495
Test name
Test status
Simulation time 4815189184 ps
CPU time 388.96 seconds
Started Nov 22 03:08:15 PM PST 23
Finished Nov 22 03:14:44 PM PST 23
Peak memory 557188 kb
Host smart-e380ffd4-2b4b-4a6f-9159-ee7576f7cabe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66267982830013355255265084696149327887305819039322655484325812102709877536976 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_rand_reset.66267982830013355255265084696149327887305819039322655484325812
102709877536976
Directory /workspace/53.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.61822713423983369695783419168267967118959710068050726167163394300696766491305
Short name T1467
Test name
Test status
Simulation time 4815189184 ps
CPU time 298.24 seconds
Started Nov 22 03:08:25 PM PST 23
Finished Nov 22 03:13:24 PM PST 23
Peak memory 559736 kb
Host smart-f3fbba9e-faa6-4354-a456-1f572fbb3a3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61822713423983369695783419168267967118959710068050726167163394300696766491305 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_reset_error.618227134239833696957834191682679671189597100680507261671633
94300696766491305
Directory /workspace/53.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.28301811615621387553122962376375441970786383851463996285635866936877710369876
Short name T1620
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.26 seconds
Started Nov 22 03:08:24 PM PST 23
Finished Nov 22 03:09:15 PM PST 23
Peak memory 553712 kb
Host smart-3246670a-887d-4009-94a1-85de6c176f0e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28301811615621387553122962376375441970786383851463996285635866936877710369876 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.28301811615621387553122962376375441970786383851463996285635866936877710369876
Directory /workspace/53.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device.87886289654791344797946171883496475432329777997165751820384998245790934158282
Short name T684
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.32 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:10:13 PM PST 23
Peak memory 554716 kb
Host smart-fef4e404-4278-41a0-b3b1-b9fe3da70f0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87886289654791344797946171883496475432329777997165751820384998245790934158282 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.87886289654791344797946171883496475432329777997165751820384998245790934158282
Directory /workspace/54.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.39866654255937698705992270345430182869569082201235031376697080823299663979894
Short name T642
Test name
Test status
Simulation time 115195295727 ps
CPU time 1997.28 seconds
Started Nov 22 03:08:35 PM PST 23
Finished Nov 22 03:41:53 PM PST 23
Peak memory 554752 kb
Host smart-2eb8b7a9-c553-4211-b66b-3a7df3b9810c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39866654255937698705992270345430182869569082201235031376697080823299663979894 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device_slow_rsp.39866654255937698705992270345430182869569082201235031376697080823299663979894
Directory /workspace/54.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.13776088358424342580473583230609696235228099997553773500647887754107464026495
Short name T228
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.61 seconds
Started Nov 22 03:08:28 PM PST 23
Finished Nov 22 03:09:12 PM PST 23
Peak memory 553444 kb
Host smart-2cdf1b36-e91c-494a-903d-531fc1be4900
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13776088358424342580473583230609696235228099997553773500647887754107464026495 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.13776088358424342580473583230609696235228099997553773500647887754107464026495
Directory /workspace/54.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_random.74259839763065746874055596906580958603250320432439787375836050714740349356388
Short name T423
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.38 seconds
Started Nov 22 03:08:24 PM PST 23
Finished Nov 22 03:09:37 PM PST 23
Peak memory 553560 kb
Host smart-1b15b92c-6bc3-4662-9e9c-47ef32fc57d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74259839763065746874055596906580958603250320432439787375836050714740349356388 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 54.xbar_error_random.74259839763065746874055596906580958603250320432439787375836050714740349356388
Directory /workspace/54.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random.22750915180319389370908289948226652336668633166629521913513875416937917443832
Short name T1553
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.34 seconds
Started Nov 22 03:08:32 PM PST 23
Finished Nov 22 03:09:51 PM PST 23
Peak memory 553724 kb
Host smart-12a3d253-29b1-4bca-bb6b-df946a4bfd5a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22750915180319389370908289948226652336668633166629521913513875416937917443832 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 54.xbar_random.22750915180319389370908289948226652336668633166629521913513875416937917443832
Directory /workspace/54.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.99706944695689467245020855252047328895621891230278432287120766147052941396229
Short name T958
Test name
Test status
Simulation time 97702135727 ps
CPU time 1118.82 seconds
Started Nov 22 03:08:24 PM PST 23
Finished Nov 22 03:27:04 PM PST 23
Peak memory 553664 kb
Host smart-d753439b-aa8f-49f0-9de7-be89440e56b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99706944695689467245020855252047328895621891230278432287120766147052941396229 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.99706944695689467245020855252047328895621891230278432287120766147052941396229
Directory /workspace/54.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.25354256246303575138901985612817256846221334528908171884516145140169299775080
Short name T1243
Test name
Test status
Simulation time 60576345727 ps
CPU time 1098.35 seconds
Started Nov 22 03:08:24 PM PST 23
Finished Nov 22 03:26:43 PM PST 23
Peak memory 553724 kb
Host smart-d39b3c71-c288-441f-8fd5-c44d31b3c0a7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25354256246303575138901985612817256846221334528908171884516145140169299775080 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.25354256246303575138901985612817256846221334528908171884516145140169299775080
Directory /workspace/54.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.67042758215998308981884545603530038091878851244706605457676667793967191650819
Short name T1688
Test name
Test status
Simulation time 556965727 ps
CPU time 47.17 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:09:22 PM PST 23
Peak memory 553640 kb
Host smart-eb090c74-c0f8-490a-bba3-ac8885b4345d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67042758215998308981884545603530038091878851244706605457676667793967191650819 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_delays.67042758215998308981884545603530038091878851244706605457676667793967191650819
Directory /workspace/54.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_same_source.80770055187626244906151068027095136303058818808398031207499585736246796608981
Short name T1871
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.85 seconds
Started Nov 22 03:08:42 PM PST 23
Finished Nov 22 03:09:58 PM PST 23
Peak memory 553556 kb
Host smart-58170420-9f77-4768-ab67-6885cbce084a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80770055187626244906151068027095136303058818808398031207499585736246796608981 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.80770055187626244906151068027095136303058818808398031207499585736246796608981
Directory /workspace/54.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke.102986679656338635724550022380982295833694389087538955304398297856027297089052
Short name T892
Test name
Test status
Simulation time 196985727 ps
CPU time 8.75 seconds
Started Nov 22 03:08:25 PM PST 23
Finished Nov 22 03:08:35 PM PST 23
Peak memory 552368 kb
Host smart-e0af60ae-9497-40e4-a161-f3a0071745e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102986679656338635724550022380982295833694389087538955304398297856027297089052 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 54.xbar_smoke.102986679656338635724550022380982295833694389087538955304398297856027297089052
Directory /workspace/54.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.103696606488567487280929682727272223245123546391346899213098455351400292299207
Short name T1634
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.78 seconds
Started Nov 22 03:08:40 PM PST 23
Finished Nov 22 03:10:10 PM PST 23
Peak memory 552212 kb
Host smart-93f3da67-e676-4167-8500-7dcf7e84f747
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103696606488567487280929682727272223245123546391346899213098455351400292299207 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.103696606488567487280929682727272223245123546391346899213098455351400292299207
Directory /workspace/54.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.59834279130335783319406159618099765347149756291933733650932237436898093692083
Short name T1854
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.66 seconds
Started Nov 22 03:08:35 PM PST 23
Finished Nov 22 03:10:05 PM PST 23
Peak memory 552360 kb
Host smart-f5e5f182-32b8-45c3-a49d-f421f8890af0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59834279130335783319406159618099765347149756291933733650932237436898093692083 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.59834279130335783319406159618099765347149756291933733650932237436898093692083
Directory /workspace/54.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.66161435357290416462593211398536528955648321331069219541455650926966135508622
Short name T1341
Test name
Test status
Simulation time 45555727 ps
CPU time 6.42 seconds
Started Nov 22 03:08:25 PM PST 23
Finished Nov 22 03:08:32 PM PST 23
Peak memory 552280 kb
Host smart-4a35009c-bf47-4cb5-812a-5b1705f4a4f5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66161435357290416462593211398536528955648321331069219541455650926966135508622 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays.66161435357290416462593211398536528955648321331069219541455650926966135508622
Directory /workspace/54.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all.8391018878524555087601489896696815620047052108512329498253316228479059995918
Short name T663
Test name
Test status
Simulation time 13992004073 ps
CPU time 531.3 seconds
Started Nov 22 03:08:47 PM PST 23
Finished Nov 22 03:17:39 PM PST 23
Peak memory 555892 kb
Host smart-2d1d9776-8672-4724-9dbf-7b306763fa65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8391018878524555087601489896696815620047052108512329498253316228479059995918 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.8391018878524555087601489896696815620047052108512329498253316228479059995918
Directory /workspace/54.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.106146883077482187975562635341936139501257211013331599309485438331683938130083
Short name T272
Test name
Test status
Simulation time 13999524073 ps
CPU time 459.87 seconds
Started Nov 22 03:08:46 PM PST 23
Finished Nov 22 03:16:27 PM PST 23
Peak memory 555720 kb
Host smart-5ea18096-aafd-4aff-bf41-d216326f8dfc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106146883077482187975562635341936139501257211013331599309485438331683938130083 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.106146883077482187975562635341936139501257211013331599309485438331683938130083
Directory /workspace/54.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.9893540522784572950413443646748032163658611313863599655743010354956017836699
Short name T1735
Test name
Test status
Simulation time 4815189184 ps
CPU time 371.65 seconds
Started Nov 22 03:08:27 PM PST 23
Finished Nov 22 03:14:39 PM PST 23
Peak memory 557236 kb
Host smart-2badc671-3192-4840-b19a-c54d2b84e752
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9893540522784572950413443646748032163658611313863599655743010354956017836699 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_rand_reset.989354052278457295041344364674803216365861131386359965574301035
4956017836699
Directory /workspace/54.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.54080940756218630773854715868387410605274661541415963485368363929756928938434
Short name T1792
Test name
Test status
Simulation time 4815189184 ps
CPU time 310.41 seconds
Started Nov 22 03:08:47 PM PST 23
Finished Nov 22 03:13:58 PM PST 23
Peak memory 559704 kb
Host smart-e93ea4c1-1b73-4510-8573-7ce88470a242
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54080940756218630773854715868387410605274661541415963485368363929756928938434 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_reset_error.540809407562186307738547158683874106052746615414159634853683
63929756928938434
Directory /workspace/54.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.108971054806359461516476213739139963604017266049344823437385629210356870369394
Short name T67
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.61 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:09:16 PM PST 23
Peak memory 553712 kb
Host smart-cf3c6e49-1c90-49d8-882f-df33b19dfa47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108971054806359461516476213739139963604017266049344823437385629210356870369394 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.108971054806359461516476213739139963604017266049344823437385629210356870369394
Directory /workspace/54.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device.76466923696378990237979233573541992329163043794181928087523840141838436796535
Short name T1035
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.2 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:10:21 PM PST 23
Peak memory 554732 kb
Host smart-eccae745-c0fe-4ab8-a800-48975690c136
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76466923696378990237979233573541992329163043794181928087523840141838436796535 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device.76466923696378990237979233573541992329163043794181928087523840141838436796535
Directory /workspace/55.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.90208201537236726142218884309782436033229990032815388612556116336842219814257
Short name T443
Test name
Test status
Simulation time 115195295727 ps
CPU time 1837.18 seconds
Started Nov 22 03:08:47 PM PST 23
Finished Nov 22 03:39:26 PM PST 23
Peak memory 554776 kb
Host smart-34ec39cd-356f-45c3-939e-1a5c07c3206f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90208201537236726142218884309782436033229990032815388612556116336842219814257 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device_slow_rsp.90208201537236726142218884309782436033229990032815388612556116336842219814257
Directory /workspace/55.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.104017663076305431127587010274295817721746047700729040969656352799676352567162
Short name T1101
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.61 seconds
Started Nov 22 03:08:38 PM PST 23
Finished Nov 22 03:09:24 PM PST 23
Peak memory 553336 kb
Host smart-ef8dadc9-d035-4912-a862-07ec0fa07e18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104017663076305431127587010274295817721746047700729040969656352799676352567162 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.104017663076305431127587010274295817721746047700729040969656352799676352567162
Directory /workspace/55.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_random.102874498898861285823920910893568959600027346682916199408440604910173606442623
Short name T155
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.89 seconds
Started Nov 22 03:08:27 PM PST 23
Finished Nov 22 03:09:41 PM PST 23
Peak memory 553512 kb
Host smart-ed5219ae-7981-4c98-9dbb-51d1a8706711
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102874498898861285823920910893568959600027346682916199408440604910173606442623 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 55.xbar_error_random.102874498898861285823920910893568959600027346682916199408440604910173606442623
Directory /workspace/55.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random.83681018540799244944697619334076281849954178331304607886911225241023840293416
Short name T1446
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.93 seconds
Started Nov 22 03:08:32 PM PST 23
Finished Nov 22 03:09:46 PM PST 23
Peak memory 553720 kb
Host smart-2d49bce2-d406-4564-afe0-887bf0e7d888
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83681018540799244944697619334076281849954178331304607886911225241023840293416 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 55.xbar_random.83681018540799244944697619334076281849954178331304607886911225241023840293416
Directory /workspace/55.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.22929282066726449243208982846090712456619457327230834263406818148218907730568
Short name T1125
Test name
Test status
Simulation time 97702135727 ps
CPU time 1096.88 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:27:07 PM PST 23
Peak memory 553656 kb
Host smart-d4e931ea-9b6b-4bcf-ac09-e3d7968fd38d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929282066726449243208982846090712456619457327230834263406818148218907730568 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.22929282066726449243208982846090712456619457327230834263406818148218907730568
Directory /workspace/55.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.80935582839507228006731938920772267134465248997284699078142706134267676442852
Short name T1414
Test name
Test status
Simulation time 60576345727 ps
CPU time 1100.2 seconds
Started Nov 22 03:08:39 PM PST 23
Finished Nov 22 03:27:00 PM PST 23
Peak memory 553716 kb
Host smart-8af5401a-9298-4383-8fe6-23568eb420ef
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80935582839507228006731938920772267134465248997284699078142706134267676442852 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.80935582839507228006731938920772267134465248997284699078142706134267676442852
Directory /workspace/55.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.42837681905194416616184955883348540530179899757375863993338041920203839486753
Short name T1887
Test name
Test status
Simulation time 556965727 ps
CPU time 47.64 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:09:37 PM PST 23
Peak memory 553700 kb
Host smart-fe916a86-c0d6-4dd7-8515-a6e0043d31ef
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42837681905194416616184955883348540530179899757375863993338041920203839486753 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delays.42837681905194416616184955883348540530179899757375863993338041920203839486753
Directory /workspace/55.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_same_source.53556311783537940530001370462206767834333025004145053322831664980935501683667
Short name T596
Test name
Test status
Simulation time 2498784073 ps
CPU time 84.38 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:09:56 PM PST 23
Peak memory 553756 kb
Host smart-4149701e-3b32-496e-9391-e5aeef9325e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53556311783537940530001370462206767834333025004145053322831664980935501683667 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.53556311783537940530001370462206767834333025004145053322831664980935501683667
Directory /workspace/55.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke.77544192713311650653316970220072159224668260776282409469605862580217658226031
Short name T1545
Test name
Test status
Simulation time 196985727 ps
CPU time 8.23 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:08:58 PM PST 23
Peak memory 552356 kb
Host smart-68381154-0601-460c-b93d-538d8712b85f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77544192713311650653316970220072159224668260776282409469605862580217658226031 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 55.xbar_smoke.77544192713311650653316970220072159224668260776282409469605862580217658226031
Directory /workspace/55.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.79638739510205880518549633919829820724298190795165091798159835346278923933313
Short name T533
Test name
Test status
Simulation time 7758585727 ps
CPU time 86.44 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:10:16 PM PST 23
Peak memory 552380 kb
Host smart-6e1f57dc-c9b5-48cf-9d9f-65bde19a7e1a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79638739510205880518549633919829820724298190795165091798159835346278923933313 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.79638739510205880518549633919829820724298190795165091798159835346278923933313
Directory /workspace/55.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.71192558228038806806353909033222206819688972806899605605220186279233792417793
Short name T1480
Test name
Test status
Simulation time 4856075727 ps
CPU time 81.91 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:10:11 PM PST 23
Peak memory 552380 kb
Host smart-8b9e1a54-904d-426a-9762-397d81c395df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71192558228038806806353909033222206819688972806899605605220186279233792417793 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.71192558228038806806353909033222206819688972806899605605220186279233792417793
Directory /workspace/55.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.80365210979092856877910052570931002229628528861140091747770438688972430890764
Short name T624
Test name
Test status
Simulation time 45555727 ps
CPU time 5.93 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:08:55 PM PST 23
Peak memory 552356 kb
Host smart-3f803d35-c15f-4fc1-a2e6-b2f762bd3882
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80365210979092856877910052570931002229628528861140091747770438688972430890764 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.80365210979092856877910052570931002229628528861140091747770438688972430890764
Directory /workspace/55.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all.28857286461192843036595329247185216068296938365845388280584994929341259521150
Short name T1258
Test name
Test status
Simulation time 13992004073 ps
CPU time 535.09 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:17:30 PM PST 23
Peak memory 555924 kb
Host smart-7dec3e5c-a3da-4a35-9daf-92d9821fdb7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28857286461192843036595329247185216068296938365845388280584994929341259521150 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.28857286461192843036595329247185216068296938365845388280584994929341259521150
Directory /workspace/55.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.64795327747110054116505793806053389179693119295968713756828087848275671610341
Short name T175
Test name
Test status
Simulation time 13999524073 ps
CPU time 512.06 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:17:03 PM PST 23
Peak memory 555724 kb
Host smart-19646a06-34b8-47a4-a8c1-c8584363eac4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64795327747110054116505793806053389179693119295968713756828087848275671610341 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.64795327747110054116505793806053389179693119295968713756828087848275671610341
Directory /workspace/55.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4196715542412528526694992934820774266522659561559936697770592288774603134445
Short name T1724
Test name
Test status
Simulation time 4815189184 ps
CPU time 359.44 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:14:35 PM PST 23
Peak memory 557168 kb
Host smart-4ef9e084-21d2-4266-ac41-eb542d4e79bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196715542412528526694992934820774266522659561559936697770592288774603134445 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_rand_reset.419671554241252852669499293482077426652265956155993669777059228
8774603134445
Directory /workspace/55.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.13318994388236541116554035506115931829059340518099121095708540113388591869392
Short name T650
Test name
Test status
Simulation time 4815189184 ps
CPU time 312.03 seconds
Started Nov 22 03:08:32 PM PST 23
Finished Nov 22 03:13:45 PM PST 23
Peak memory 559688 kb
Host smart-1a681b17-477b-4927-8c6b-6b842f4f3715
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13318994388236541116554035506115931829059340518099121095708540113388591869392 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_reset_error.133189943882365411165540355061159318290593405180991210957085
40113388591869392
Directory /workspace/55.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.74611592400865934523200023587395813907465420185348268933151074659669753531272
Short name T401
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.49 seconds
Started Nov 22 03:08:27 PM PST 23
Finished Nov 22 03:09:16 PM PST 23
Peak memory 553700 kb
Host smart-052499c9-a014-496c-8284-09e375411a9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74611592400865934523200023587395813907465420185348268933151074659669753531272 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.74611592400865934523200023587395813907465420185348268933151074659669753531272
Directory /workspace/55.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device.58122600072321158251911978499389941341654021050499796917479844084710737880084
Short name T627
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.38 seconds
Started Nov 22 03:08:27 PM PST 23
Finished Nov 22 03:10:14 PM PST 23
Peak memory 554808 kb
Host smart-2eef2641-13fe-4b8e-bf39-fcd3aa38f803
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58122600072321158251911978499389941341654021050499796917479844084710737880084 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device.58122600072321158251911978499389941341654021050499796917479844084710737880084
Directory /workspace/56.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.72037916561910136333817156461919845035287284493889692473591888437536352933565
Short name T1849
Test name
Test status
Simulation time 115195295727 ps
CPU time 1998.47 seconds
Started Nov 22 03:08:27 PM PST 23
Finished Nov 22 03:41:46 PM PST 23
Peak memory 554760 kb
Host smart-6c120892-d000-44f1-b5ec-799adbedd0a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72037916561910136333817156461919845035287284493889692473591888437536352933565 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device_slow_rsp.72037916561910136333817156461919845035287284493889692473591888437536352933565
Directory /workspace/56.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.51042376298676477691750695556327765452841521600384607490536202359388364856686
Short name T727
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.04 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:09:15 PM PST 23
Peak memory 553464 kb
Host smart-e90559f5-04b9-4864-a19d-c0258e58915c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51042376298676477691750695556327765452841521600384607490536202359388364856686 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr.51042376298676477691750695556327765452841521600384607490536202359388364856686
Directory /workspace/56.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_random.34329548407643123208235969211553599236977964342075371958012739743779705211844
Short name T342
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.09 seconds
Started Nov 22 03:08:35 PM PST 23
Finished Nov 22 03:09:47 PM PST 23
Peak memory 553508 kb
Host smart-5e7a0b4b-4bef-44f8-9893-7435061577d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34329548407643123208235969211553599236977964342075371958012739743779705211844 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 56.xbar_error_random.34329548407643123208235969211553599236977964342075371958012739743779705211844
Directory /workspace/56.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random.28408149967428175776248732232288641922682837446914995013938038673041563321968
Short name T1912
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.79 seconds
Started Nov 22 03:08:28 PM PST 23
Finished Nov 22 03:09:46 PM PST 23
Peak memory 553760 kb
Host smart-a6b7dee4-2526-4b6b-ae88-0795d05aba54
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28408149967428175776248732232288641922682837446914995013938038673041563321968 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 56.xbar_random.28408149967428175776248732232288641922682837446914995013938038673041563321968
Directory /workspace/56.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.53331227761302932640516494223156620983156595310018595814030700628825268288474
Short name T187
Test name
Test status
Simulation time 97702135727 ps
CPU time 1112.49 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:27:03 PM PST 23
Peak memory 553648 kb
Host smart-e8dec85a-0f96-4cd1-9597-c983d5271d79
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53331227761302932640516494223156620983156595310018595814030700628825268288474 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.53331227761302932640516494223156620983156595310018595814030700628825268288474
Directory /workspace/56.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.80709177407077092007233006753204695520131856934250858979345980297514508053105
Short name T1731
Test name
Test status
Simulation time 60576345727 ps
CPU time 1101.53 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:26:48 PM PST 23
Peak memory 553796 kb
Host smart-ac768b78-96f3-4105-83be-fc06e4c8774a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80709177407077092007233006753204695520131856934250858979345980297514508053105 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.80709177407077092007233006753204695520131856934250858979345980297514508053105
Directory /workspace/56.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.12366269426655953596074108269444224313180987968110556594227418744625390590062
Short name T688
Test name
Test status
Simulation time 556965727 ps
CPU time 44.63 seconds
Started Nov 22 03:08:47 PM PST 23
Finished Nov 22 03:09:32 PM PST 23
Peak memory 553700 kb
Host smart-660eb617-9f23-4014-925f-235d1331f1a6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12366269426655953596074108269444224313180987968110556594227418744625390590062 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_delays.12366269426655953596074108269444224313180987968110556594227418744625390590062
Directory /workspace/56.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_same_source.32618882445451184062320019047459299839893354706523769536319861751725813934937
Short name T931
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.45 seconds
Started Nov 22 03:08:28 PM PST 23
Finished Nov 22 03:09:42 PM PST 23
Peak memory 553692 kb
Host smart-e9c9834d-59cc-456b-9e06-1a121bdec784
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32618882445451184062320019047459299839893354706523769536319861751725813934937 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.32618882445451184062320019047459299839893354706523769536319861751725813934937
Directory /workspace/56.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke.98327167415869617902705259845524994645619343883544901985869491396282340608819
Short name T1613
Test name
Test status
Simulation time 196985727 ps
CPU time 8.65 seconds
Started Nov 22 03:08:27 PM PST 23
Finished Nov 22 03:08:37 PM PST 23
Peak memory 552328 kb
Host smart-fe4fbf40-2455-45a9-abad-e07dcbc78baf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98327167415869617902705259845524994645619343883544901985869491396282340608819 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 56.xbar_smoke.98327167415869617902705259845524994645619343883544901985869491396282340608819
Directory /workspace/56.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.81452902628482375249970556171930644074135402700244722840579759841627540227910
Short name T904
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.61 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:09:58 PM PST 23
Peak memory 552372 kb
Host smart-dcfb890b-cef4-4e6b-9d0b-7095dff1cff1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81452902628482375249970556171930644074135402700244722840579759841627540227910 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.81452902628482375249970556171930644074135402700244722840579759841627540227910
Directory /workspace/56.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.59964788021416847340068110562936570662907775869767773843226168843213942005602
Short name T734
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.8 seconds
Started Nov 22 03:08:25 PM PST 23
Finished Nov 22 03:09:54 PM PST 23
Peak memory 552344 kb
Host smart-35778a2a-3037-4be2-bcc9-5e2f0c11ee93
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59964788021416847340068110562936570662907775869767773843226168843213942005602 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.59964788021416847340068110562936570662907775869767773843226168843213942005602
Directory /workspace/56.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.38480407521374730485594116672970207517061462285203246864159137117572741657409
Short name T121
Test name
Test status
Simulation time 45555727 ps
CPU time 5.94 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:08:55 PM PST 23
Peak memory 552320 kb
Host smart-ce07420b-2815-4440-b80f-9d9d37455a67
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38480407521374730485594116672970207517061462285203246864159137117572741657409 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays.38480407521374730485594116672970207517061462285203246864159137117572741657409
Directory /workspace/56.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all.94043970459092377920498099743428955513154662525973323028405581922268735944271
Short name T1772
Test name
Test status
Simulation time 13992004073 ps
CPU time 520.27 seconds
Started Nov 22 03:08:33 PM PST 23
Finished Nov 22 03:17:14 PM PST 23
Peak memory 555956 kb
Host smart-74143d98-02cb-44ed-9559-24407786dd72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94043970459092377920498099743428955513154662525973323028405581922268735944271 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.94043970459092377920498099743428955513154662525973323028405581922268735944271
Directory /workspace/56.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.30143471497974125021362588864913656176597614813953837050351756293916504193435
Short name T578
Test name
Test status
Simulation time 13999524073 ps
CPU time 490.96 seconds
Started Nov 22 03:08:28 PM PST 23
Finished Nov 22 03:16:40 PM PST 23
Peak memory 555744 kb
Host smart-f44ec3e2-1425-4102-84fb-10838400c851
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30143471497974125021362588864913656176597614813953837050351756293916504193435 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.30143471497974125021362588864913656176597614813953837050351756293916504193435
Directory /workspace/56.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.10603536211944112831198048191124752099367269827599009652661347954252463228536
Short name T810
Test name
Test status
Simulation time 4815189184 ps
CPU time 383.85 seconds
Started Nov 22 03:08:32 PM PST 23
Finished Nov 22 03:14:57 PM PST 23
Peak memory 557244 kb
Host smart-4ae4831b-23ef-49d2-b380-035781e22f78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10603536211944112831198048191124752099367269827599009652661347954252463228536 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_rand_reset.10603536211944112831198048191124752099367269827599009652661347
954252463228536
Directory /workspace/56.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.7701089802027569099686497296777177208861047849954722038824899865690823123008
Short name T564
Test name
Test status
Simulation time 4815189184 ps
CPU time 321.19 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:13:51 PM PST 23
Peak memory 559724 kb
Host smart-64296c13-6ca0-40e3-b1ee-11c99557d7ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7701089802027569099686497296777177208861047849954722038824899865690823123008 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_reset_error.7701089802027569099686497296777177208861047849954722038824899
865690823123008
Directory /workspace/56.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.31007514587698591030147071501230175695165535965602384764562551362270516641697
Short name T358
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.91 seconds
Started Nov 22 03:08:33 PM PST 23
Finished Nov 22 03:09:25 PM PST 23
Peak memory 553764 kb
Host smart-de16a04c-d8cc-4b21-9868-8573793f8a25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31007514587698591030147071501230175695165535965602384764562551362270516641697 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.31007514587698591030147071501230175695165535965602384764562551362270516641697
Directory /workspace/56.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device.83819392118538495286878861819392266998160049090519680972681708476164907154939
Short name T829
Test name
Test status
Simulation time 2590995727 ps
CPU time 110.48 seconds
Started Nov 22 03:08:32 PM PST 23
Finished Nov 22 03:10:23 PM PST 23
Peak memory 554740 kb
Host smart-09917a41-c790-4c48-a151-e0d70d1af438
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83819392118538495286878861819392266998160049090519680972681708476164907154939 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.83819392118538495286878861819392266998160049090519680972681708476164907154939
Directory /workspace/57.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.15776157638245386129207475587998259715604125005200116033249377590526980442032
Short name T1750
Test name
Test status
Simulation time 115195295727 ps
CPU time 1829.26 seconds
Started Nov 22 03:08:47 PM PST 23
Finished Nov 22 03:39:18 PM PST 23
Peak memory 554776 kb
Host smart-05694be2-13d3-418f-a31b-47c49f631c24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15776157638245386129207475587998259715604125005200116033249377590526980442032 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device_slow_rsp.15776157638245386129207475587998259715604125005200116033249377590526980442032
Directory /workspace/57.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.102278565974787104748666545449904265050701720904161896074101537834571769042470
Short name T1879
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.73 seconds
Started Nov 22 03:08:32 PM PST 23
Finished Nov 22 03:09:15 PM PST 23
Peak memory 553444 kb
Host smart-36cd7ab6-7b9f-4df1-82a7-d443d4fd2ce7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102278565974787104748666545449904265050701720904161896074101537834571769042470 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.102278565974787104748666545449904265050701720904161896074101537834571769042470
Directory /workspace/57.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_random.84813648696190916235753638526569147933413499003452745594699583226718451412615
Short name T1503
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.93 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:09:52 PM PST 23
Peak memory 553452 kb
Host smart-9ec4d827-5cf8-4414-b978-afe1036b4b11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84813648696190916235753638526569147933413499003452745594699583226718451412615 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 57.xbar_error_random.84813648696190916235753638526569147933413499003452745594699583226718451412615
Directory /workspace/57.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random.102448407418422944507552707870507778384326077956553500211891433203823002959255
Short name T1080
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.33 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:09:48 PM PST 23
Peak memory 553676 kb
Host smart-c3ce567e-8861-40c4-a8f8-84799505d654
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102448407418422944507552707870507778384326077956553500211891433203823002959255 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 57.xbar_random.102448407418422944507552707870507778384326077956553500211891433203823002959255
Directory /workspace/57.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.35361627590884968213904624565097507393218738046472247130010793953735278934012
Short name T807
Test name
Test status
Simulation time 97702135727 ps
CPU time 1153.22 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:27:44 PM PST 23
Peak memory 553660 kb
Host smart-b7034d0b-53da-4f47-925c-ed99ea65b526
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35361627590884968213904624565097507393218738046472247130010793953735278934012 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.35361627590884968213904624565097507393218738046472247130010793953735278934012
Directory /workspace/57.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1974242409721824492738152257453879042260092349256141833559502296830639189060
Short name T346
Test name
Test status
Simulation time 60576345727 ps
CPU time 1085.9 seconds
Started Nov 22 03:08:41 PM PST 23
Finished Nov 22 03:26:47 PM PST 23
Peak memory 553532 kb
Host smart-f3c8a2be-ff6a-44fc-ac85-5de3cf3ae295
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974242409721824492738152257453879042260092349256141833559502296830639189060 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.1974242409721824492738152257453879042260092349256141833559502296830639189060
Directory /workspace/57.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.115622765283353213060779227760169542272245137109954437061789587414976743882455
Short name T1087
Test name
Test status
Simulation time 556965727 ps
CPU time 48.65 seconds
Started Nov 22 03:08:38 PM PST 23
Finished Nov 22 03:09:28 PM PST 23
Peak memory 553716 kb
Host smart-e4765bf9-1428-4a7a-a995-c5b69b18a5ca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115622765283353213060779227760169542272245137109954437061789587414976743882455 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_delays.115622765283353213060779227760169542272245137109954437061789587414976743882455
Directory /workspace/57.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_same_source.78161854853990508144923680725323418882094332403895611120290334056434361623652
Short name T863
Test name
Test status
Simulation time 2498784073 ps
CPU time 67.67 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:09:43 PM PST 23
Peak memory 553644 kb
Host smart-a8635866-f948-4bf5-8b1c-0f68faee853f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78161854853990508144923680725323418882094332403895611120290334056434361623652 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.78161854853990508144923680725323418882094332403895611120290334056434361623652
Directory /workspace/57.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke.8051891007523844603249810707790476304254946928615555797710313384639095839067
Short name T1694
Test name
Test status
Simulation time 196985727 ps
CPU time 8.07 seconds
Started Nov 22 03:08:33 PM PST 23
Finished Nov 22 03:08:42 PM PST 23
Peak memory 552412 kb
Host smart-5224a4a3-4ef7-41ff-b146-d9c6122aeee7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8051891007523844603249810707790476304254946928615555797710313384639095839067 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 57.xbar_smoke.8051891007523844603249810707790476304254946928615555797710313384639095839067
Directory /workspace/57.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.98851322416424199746613045818269923845317679992062051004750216313654572787835
Short name T1314
Test name
Test status
Simulation time 7758585727 ps
CPU time 85.56 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:10:14 PM PST 23
Peak memory 552356 kb
Host smart-1b234e4c-fc93-49b5-9c59-e6b0772e90b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98851322416424199746613045818269923845317679992062051004750216313654572787835 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.98851322416424199746613045818269923845317679992062051004750216313654572787835
Directory /workspace/57.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.30208304910076609871276957762908701232047715384310833203749902666899166038152
Short name T478
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.04 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:09:50 PM PST 23
Peak memory 552372 kb
Host smart-51ea28b9-fc97-49c1-8f0d-dc76f51034e0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30208304910076609871276957762908701232047715384310833203749902666899166038152 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.30208304910076609871276957762908701232047715384310833203749902666899166038152
Directory /workspace/57.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3543427056489233506929005874195713572461189563594400393815270533661301906836
Short name T808
Test name
Test status
Simulation time 45555727 ps
CPU time 6.05 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:08:41 PM PST 23
Peak memory 552276 kb
Host smart-68d9cd39-1b5f-41e1-b98c-0078b29dc9f3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543427056489233506929005874195713572461189563594400393815270533661301906836 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays.3543427056489233506929005874195713572461189563594400393815270533661301906836
Directory /workspace/57.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all.66732382581177588383842706077909048153635806575398591248688169629326043096179
Short name T186
Test name
Test status
Simulation time 13992004073 ps
CPU time 554.44 seconds
Started Nov 22 03:08:26 PM PST 23
Finished Nov 22 03:17:42 PM PST 23
Peak memory 555824 kb
Host smart-8652696d-e9f7-4341-8201-72828ee965a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66732382581177588383842706077909048153635806575398591248688169629326043096179 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.66732382581177588383842706077909048153635806575398591248688169629326043096179
Directory /workspace/57.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.1137438247207400821830848863339219408200809332182456522756375210984132990182
Short name T1134
Test name
Test status
Simulation time 13999524073 ps
CPU time 505.36 seconds
Started Nov 22 03:08:34 PM PST 23
Finished Nov 22 03:17:01 PM PST 23
Peak memory 555644 kb
Host smart-92587424-ad3a-4db4-bee0-9319e5d14a60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137438247207400821830848863339219408200809332182456522756375210984132990182 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.1137438247207400821830848863339219408200809332182456522756375210984132990182
Directory /workspace/57.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.67734116954478931750292644999758966157700389227885690333404037292055607751437
Short name T518
Test name
Test status
Simulation time 4815189184 ps
CPU time 379.11 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:14:49 PM PST 23
Peak memory 557252 kb
Host smart-001345af-fa1d-42bc-a43f-5a7a3ef1f9ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67734116954478931750292644999758966157700389227885690333404037292055607751437 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_rand_reset.67734116954478931750292644999758966157700389227885690333404037
292055607751437
Directory /workspace/57.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.86114174626261760965646970153437514461064250691072988079757747728242664048798
Short name T1598
Test name
Test status
Simulation time 4815189184 ps
CPU time 304.7 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:13:35 PM PST 23
Peak memory 559740 kb
Host smart-fb0b062d-8340-452c-9a4b-da27121e4380
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86114174626261760965646970153437514461064250691072988079757747728242664048798 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_reset_error.861141746262617609656469701534375144610642506910729880797577
47728242664048798
Directory /workspace/57.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.93106269770748849747922319694484725513368644706490796034364603850592482109422
Short name T298
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.21 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:09:35 PM PST 23
Peak memory 553708 kb
Host smart-2268be16-28ee-4746-8367-57fc0dd644af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93106269770748849747922319694484725513368644706490796034364603850592482109422 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.93106269770748849747922319694484725513368644706490796034364603850592482109422
Directory /workspace/57.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device.60633669636499325655500218424507129458430065217071109748925352804174288960782
Short name T135
Test name
Test status
Simulation time 2590995727 ps
CPU time 108.48 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:10:20 PM PST 23
Peak memory 554776 kb
Host smart-a77bdf29-7ab8-4a8b-b0bc-60e8e92acc39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60633669636499325655500218424507129458430065217071109748925352804174288960782 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.60633669636499325655500218424507129458430065217071109748925352804174288960782
Directory /workspace/58.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.111463476728612878116695584790970506499614246124107317743351692120268967927761
Short name T1806
Test name
Test status
Simulation time 115195295727 ps
CPU time 2019.51 seconds
Started Nov 22 03:08:40 PM PST 23
Finished Nov 22 03:42:21 PM PST 23
Peak memory 554604 kb
Host smart-52131fa5-3628-4067-b377-1273f7718a0a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111463476728612878116695584790970506499614246124107317743351692120268967927761 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device_slow_rsp.111463476728612878116695584790970506499614246124107317743351692120268967927761
Directory /workspace/58.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.61021380322810007919853126962877076344826146649541021788519309273010571220633
Short name T1787
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.13 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:09:15 PM PST 23
Peak memory 553484 kb
Host smart-4f9e8e0c-9d11-407d-950b-cd3dc06a6556
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61021380322810007919853126962877076344826146649541021788519309273010571220633 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr.61021380322810007919853126962877076344826146649541021788519309273010571220633
Directory /workspace/58.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_random.18117647328848772778483653050595121141722970170741500084068950321722272999494
Short name T1200
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.82 seconds
Started Nov 22 03:08:31 PM PST 23
Finished Nov 22 03:09:46 PM PST 23
Peak memory 553488 kb
Host smart-2a483943-a588-48bf-bdc9-92f8c310b4bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18117647328848772778483653050595121141722970170741500084068950321722272999494 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 58.xbar_error_random.18117647328848772778483653050595121141722970170741500084068950321722272999494
Directory /workspace/58.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random.100160383171979575560555741224102750556381758788876406380874759949053918539627
Short name T57
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.87 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:03 PM PST 23
Peak memory 553748 kb
Host smart-e5a2060b-2233-4300-ba46-90900a717b7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100160383171979575560555741224102750556381758788876406380874759949053918539627 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 58.xbar_random.100160383171979575560555741224102750556381758788876406380874759949053918539627
Directory /workspace/58.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.11186675542728964786257613657832483219731309673922456917187880642320091582336
Short name T1347
Test name
Test status
Simulation time 97702135727 ps
CPU time 1170.51 seconds
Started Nov 22 03:08:33 PM PST 23
Finished Nov 22 03:28:05 PM PST 23
Peak memory 553664 kb
Host smart-86169945-60aa-4fcc-b687-291c7843de62
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11186675542728964786257613657832483219731309673922456917187880642320091582336 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.11186675542728964786257613657832483219731309673922456917187880642320091582336
Directory /workspace/58.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.91076631332450326832773431175488908607645923845762666984725668915537944630874
Short name T1649
Test name
Test status
Simulation time 60576345727 ps
CPU time 1069.39 seconds
Started Nov 22 03:08:40 PM PST 23
Finished Nov 22 03:26:30 PM PST 23
Peak memory 553672 kb
Host smart-f7f81f9c-4f74-4dd5-9342-2fcc4dcd0b4b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91076631332450326832773431175488908607645923845762666984725668915537944630874 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.91076631332450326832773431175488908607645923845762666984725668915537944630874
Directory /workspace/58.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.112989505313916236478964878783152410184616052826408726983843814213261579591193
Short name T1472
Test name
Test status
Simulation time 556965727 ps
CPU time 47.21 seconds
Started Nov 22 03:08:33 PM PST 23
Finished Nov 22 03:09:21 PM PST 23
Peak memory 553736 kb
Host smart-7ccfc932-cb40-4c6f-9903-bbaa9f39215d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112989505313916236478964878783152410184616052826408726983843814213261579591193 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_delays.112989505313916236478964878783152410184616052826408726983843814213261579591193
Directory /workspace/58.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_same_source.57450907401828049047065372937357391058554828924321407164633444203011344467558
Short name T1682
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.04 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:05 PM PST 23
Peak memory 553720 kb
Host smart-91f5a754-8a34-4050-9868-650a018739d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57450907401828049047065372937357391058554828924321407164633444203011344467558 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.57450907401828049047065372937357391058554828924321407164633444203011344467558
Directory /workspace/58.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke.8845927958732557578302854693854013156763947272617785014333534434114617736534
Short name T1362
Test name
Test status
Simulation time 196985727 ps
CPU time 8.62 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:08:40 PM PST 23
Peak memory 552344 kb
Host smart-3e652eb7-1cf2-4108-84b1-04ad5b5ec6b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8845927958732557578302854693854013156763947272617785014333534434114617736534 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 58.xbar_smoke.8845927958732557578302854693854013156763947272617785014333534434114617736534
Directory /workspace/58.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.34509815893536156601567038308900113504502940398325149928472675329228366680005
Short name T936
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.3 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:10:02 PM PST 23
Peak memory 552352 kb
Host smart-94b9f0b1-f3ff-491f-9534-b689abe3a68e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34509815893536156601567038308900113504502940398325149928472675329228366680005 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.34509815893536156601567038308900113504502940398325149928472675329228366680005
Directory /workspace/58.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.40664566574375980624370090968267882850499080621291821915540509876273018138406
Short name T794
Test name
Test status
Simulation time 4856075727 ps
CPU time 85.14 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:09:56 PM PST 23
Peak memory 552384 kb
Host smart-e54c8025-2871-4363-9ac9-deb8236bfd0f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664566574375980624370090968267882850499080621291821915540509876273018138406 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.40664566574375980624370090968267882850499080621291821915540509876273018138406
Directory /workspace/58.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.95969798859692170173465061218704774916430113723839839558448769006592217579148
Short name T252
Test name
Test status
Simulation time 45555727 ps
CPU time 5.71 seconds
Started Nov 22 03:08:33 PM PST 23
Finished Nov 22 03:08:39 PM PST 23
Peak memory 552360 kb
Host smart-8283ab33-4876-477d-a499-4b67d7f8df77
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95969798859692170173465061218704774916430113723839839558448769006592217579148 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays.95969798859692170173465061218704774916430113723839839558448769006592217579148
Directory /workspace/58.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all.23385384720253511900500971008661769542561321889635375027804156705072133558492
Short name T1141
Test name
Test status
Simulation time 13992004073 ps
CPU time 499.47 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:17:10 PM PST 23
Peak memory 555900 kb
Host smart-b7ca4c0a-e49b-46be-bf52-ceb56a311347
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385384720253511900500971008661769542561321889635375027804156705072133558492 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.23385384720253511900500971008661769542561321889635375027804156705072133558492
Directory /workspace/58.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.10651345660077310132699439721239463218299324848295259690438979163222383443114
Short name T1527
Test name
Test status
Simulation time 13999524073 ps
CPU time 538.32 seconds
Started Nov 22 03:08:31 PM PST 23
Finished Nov 22 03:17:30 PM PST 23
Peak memory 555820 kb
Host smart-305b9d15-897c-4f32-a502-a4785f090b7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10651345660077310132699439721239463218299324848295259690438979163222383443114 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.10651345660077310132699439721239463218299324848295259690438979163222383443114
Directory /workspace/58.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.56820471381618837834443386752359344955734896094533836964636081292388282866023
Short name T329
Test name
Test status
Simulation time 4815189184 ps
CPU time 382.74 seconds
Started Nov 22 03:08:30 PM PST 23
Finished Nov 22 03:14:54 PM PST 23
Peak memory 557308 kb
Host smart-eea9b392-a16d-4ddf-b341-1b3b4aa464f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56820471381618837834443386752359344955734896094533836964636081292388282866023 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_rand_reset.56820471381618837834443386752359344955734896094533836964636081
292388282866023
Directory /workspace/58.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.30122054719682555196493310152004272178237812736409291758183203378113843967323
Short name T1558
Test name
Test status
Simulation time 4815189184 ps
CPU time 310.89 seconds
Started Nov 22 03:08:29 PM PST 23
Finished Nov 22 03:13:40 PM PST 23
Peak memory 559744 kb
Host smart-3962f885-e316-4689-ba3d-32e7edea3bc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30122054719682555196493310152004272178237812736409291758183203378113843967323 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_reset_error.301220547196825551964933101520042721782378127364092917581832
03378113843967323
Directory /workspace/58.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.24975250987634167782750881971609945983646160829578928006074971730134196959063
Short name T917
Test name
Test status
Simulation time 1176995727 ps
CPU time 52.45 seconds
Started Nov 22 03:08:31 PM PST 23
Finished Nov 22 03:09:25 PM PST 23
Peak memory 553740 kb
Host smart-30ef27f0-6af4-4b9f-8ad7-7d28daa39ea7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24975250987634167782750881971609945983646160829578928006074971730134196959063 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.24975250987634167782750881971609945983646160829578928006074971730134196959063
Directory /workspace/58.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device.75040726401766623039000315442585919065136064447599610867693968629738410356600
Short name T246
Test name
Test status
Simulation time 2590995727 ps
CPU time 111.75 seconds
Started Nov 22 03:08:38 PM PST 23
Finished Nov 22 03:10:30 PM PST 23
Peak memory 554836 kb
Host smart-f1ecf8e3-e5a1-4954-8f48-16d109fbe671
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75040726401766623039000315442585919065136064447599610867693968629738410356600 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device.75040726401766623039000315442585919065136064447599610867693968629738410356600
Directory /workspace/59.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.80223376119478437056946174255348905445404702846066702772376542589044626403640
Short name T1680
Test name
Test status
Simulation time 115195295727 ps
CPU time 1854.18 seconds
Started Nov 22 03:08:42 PM PST 23
Finished Nov 22 03:39:37 PM PST 23
Peak memory 554744 kb
Host smart-84941535-18d3-48b2-b14a-75eb3a78e76f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80223376119478437056946174255348905445404702846066702772376542589044626403640 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device_slow_rsp.80223376119478437056946174255348905445404702846066702772376542589044626403640
Directory /workspace/59.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.55075720164266824241492632788299622655036467184507606771737562465615063114882
Short name T237
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.87 seconds
Started Nov 22 03:08:37 PM PST 23
Finished Nov 22 03:09:25 PM PST 23
Peak memory 553416 kb
Host smart-810aca28-5d72-4487-9ebd-f0d3363da4f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55075720164266824241492632788299622655036467184507606771737562465615063114882 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr.55075720164266824241492632788299622655036467184507606771737562465615063114882
Directory /workspace/59.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_random.58059733254538872930930791165701709563379556009625146780421864547725943036836
Short name T1403
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.58 seconds
Started Nov 22 03:08:36 PM PST 23
Finished Nov 22 03:09:53 PM PST 23
Peak memory 553544 kb
Host smart-605a24b7-a14e-43b1-a128-67add892a00b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58059733254538872930930791165701709563379556009625146780421864547725943036836 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 59.xbar_error_random.58059733254538872930930791165701709563379556009625146780421864547725943036836
Directory /workspace/59.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random.28199254212832049322315638502019634728651916975983531595465714401446240705869
Short name T1456
Test name
Test status
Simulation time 2231375727 ps
CPU time 77 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:08 PM PST 23
Peak memory 553744 kb
Host smart-f8d0ddcf-bd13-4c31-a286-a932380eb93d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28199254212832049322315638502019634728651916975983531595465714401446240705869 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 59.xbar_random.28199254212832049322315638502019634728651916975983531595465714401446240705869
Directory /workspace/59.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1712547315681494677558966199979450424296681103798097865117380502964237401128
Short name T1821
Test name
Test status
Simulation time 97702135727 ps
CPU time 1089.96 seconds
Started Nov 22 03:08:42 PM PST 23
Finished Nov 22 03:26:53 PM PST 23
Peak memory 553636 kb
Host smart-e57d8241-d998-4504-a5bb-4e80da426f72
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712547315681494677558966199979450424296681103798097865117380502964237401128 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1712547315681494677558966199979450424296681103798097865117380502964237401128
Directory /workspace/59.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.64970316132992344323439141266531544126304034692716222314484908581731695907943
Short name T1809
Test name
Test status
Simulation time 60576345727 ps
CPU time 1038.84 seconds
Started Nov 22 03:08:52 PM PST 23
Finished Nov 22 03:26:12 PM PST 23
Peak memory 553812 kb
Host smart-fd39ecdc-7e8c-42d9-a15e-db7d8fa65aa8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64970316132992344323439141266531544126304034692716222314484908581731695907943 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.64970316132992344323439141266531544126304034692716222314484908581731695907943
Directory /workspace/59.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.105828725497520638520123753512338203192685865654403383045717344130913700444836
Short name T1450
Test name
Test status
Simulation time 556965727 ps
CPU time 46.36 seconds
Started Nov 22 03:08:51 PM PST 23
Finished Nov 22 03:09:38 PM PST 23
Peak memory 553824 kb
Host smart-95c8d18b-4f0d-40af-8aec-8de116551a03
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105828725497520638520123753512338203192685865654403383045717344130913700444836 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_delays.105828725497520638520123753512338203192685865654403383045717344130913700444836
Directory /workspace/59.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_same_source.14577887622596081285546209355646427941641486197834595654478035101351714387446
Short name T1486
Test name
Test status
Simulation time 2498784073 ps
CPU time 85.54 seconds
Started Nov 22 03:08:39 PM PST 23
Finished Nov 22 03:10:05 PM PST 23
Peak memory 553724 kb
Host smart-beff3852-fa4b-4f1e-9a2c-c3dd43b62a17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14577887622596081285546209355646427941641486197834595654478035101351714387446 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.14577887622596081285546209355646427941641486197834595654478035101351714387446
Directory /workspace/59.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke.47739525403508193250715827152844349106243811977019127461448716425932089878281
Short name T1046
Test name
Test status
Simulation time 196985727 ps
CPU time 8.53 seconds
Started Nov 22 03:08:41 PM PST 23
Finished Nov 22 03:08:50 PM PST 23
Peak memory 552196 kb
Host smart-15fdbc55-9783-4b48-b76b-0fee9061f91e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47739525403508193250715827152844349106243811977019127461448716425932089878281 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 59.xbar_smoke.47739525403508193250715827152844349106243811977019127461448716425932089878281
Directory /workspace/59.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.97497910771834558981301296194185828360079966827968207701774745268210965662225
Short name T1493
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.5 seconds
Started Nov 22 03:08:40 PM PST 23
Finished Nov 22 03:10:12 PM PST 23
Peak memory 552204 kb
Host smart-f05cd37d-cad8-42aa-a978-e1e0ad1d7194
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97497910771834558981301296194185828360079966827968207701774745268210965662225 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.97497910771834558981301296194185828360079966827968207701774745268210965662225
Directory /workspace/59.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.103853486099969463996026187802133326810316493731901859669051172943372803699164
Short name T987
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.7 seconds
Started Nov 22 03:08:39 PM PST 23
Finished Nov 22 03:10:08 PM PST 23
Peak memory 552400 kb
Host smart-bcd49fc8-fb4c-4db9-bcb4-237e3a06ee00
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103853486099969463996026187802133326810316493731901859669051172943372803699164 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.103853486099969463996026187802133326810316493731901859669051172943372803699164
Directory /workspace/59.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.99252590997898764403756199514317597414673169584672701452367492646202363591023
Short name T620
Test name
Test status
Simulation time 45555727 ps
CPU time 6.62 seconds
Started Nov 22 03:08:31 PM PST 23
Finished Nov 22 03:08:38 PM PST 23
Peak memory 552364 kb
Host smart-223261b0-994a-403a-ba0d-04d020d9ea43
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99252590997898764403756199514317597414673169584672701452367492646202363591023 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays.99252590997898764403756199514317597414673169584672701452367492646202363591023
Directory /workspace/59.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all.47288225728430828705440110607027899676643749516998251198038145388762836169692
Short name T1643
Test name
Test status
Simulation time 13992004073 ps
CPU time 521.08 seconds
Started Nov 22 03:08:52 PM PST 23
Finished Nov 22 03:17:33 PM PST 23
Peak memory 556024 kb
Host smart-988cb385-06e5-440a-99d6-8c7ee5c95de9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47288225728430828705440110607027899676643749516998251198038145388762836169692 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.47288225728430828705440110607027899676643749516998251198038145388762836169692
Directory /workspace/59.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2292665120541313391875004761885500326949343809900800777242814661382833046281
Short name T1635
Test name
Test status
Simulation time 13999524073 ps
CPU time 507.22 seconds
Started Nov 22 03:08:37 PM PST 23
Finished Nov 22 03:17:04 PM PST 23
Peak memory 555668 kb
Host smart-70c8334d-c3c9-42a1-aede-b188d8ba6544
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292665120541313391875004761885500326949343809900800777242814661382833046281 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.2292665120541313391875004761885500326949343809900800777242814661382833046281
Directory /workspace/59.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.7477666870087358637507949907054303339215354166530598590014794354031980256662
Short name T1512
Test name
Test status
Simulation time 4815189184 ps
CPU time 373.99 seconds
Started Nov 22 03:08:38 PM PST 23
Finished Nov 22 03:14:52 PM PST 23
Peak memory 557176 kb
Host smart-9978cfb7-a1f5-4448-830c-d685bf971455
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7477666870087358637507949907054303339215354166530598590014794354031980256662 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_rand_reset.747766687008735863750794990705430333921535416653059859001479435
4031980256662
Directory /workspace/59.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.55205680672994730530688129830923560272070495216240430704538754435032212418305
Short name T1754
Test name
Test status
Simulation time 4815189184 ps
CPU time 302.55 seconds
Started Nov 22 03:08:51 PM PST 23
Finished Nov 22 03:13:54 PM PST 23
Peak memory 559828 kb
Host smart-813062b5-9db4-416b-9d7a-54858ed45237
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55205680672994730530688129830923560272070495216240430704538754435032212418305 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_reset_error.552056806729947305306881298309235602720704952162404307045387
54435032212418305
Directory /workspace/59.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.41715693917661311165423675142968854646897084937605424605722244916932457142890
Short name T1802
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.8 seconds
Started Nov 22 03:08:37 PM PST 23
Finished Nov 22 03:09:25 PM PST 23
Peak memory 553684 kb
Host smart-42f5a327-ca73-4cb7-939a-a38cc96c5f66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715693917661311165423675142968854646897084937605424605722244916932457142890 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.41715693917661311165423675142968854646897084937605424605722244916932457142890
Directory /workspace/59.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.54100193737479776770749540782238238751446493399127355713357105590867024983758
Short name T1673
Test name
Test status
Simulation time 7234930891 ps
CPU time 320.58 seconds
Started Nov 22 03:03:36 PM PST 23
Finished Nov 22 03:08:58 PM PST 23
Peak memory 622524 kb
Host smart-85744738-22e8-463b-bff1-8598a75a6035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5410019373747977677074954078223
8238751446493399127355713357105590867024983758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.5410019373747
9776770749540782238238751446493399127355713357105590867024983758
Directory /workspace/6.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_rw.18989590581593288935451241761360675236598299181319247628944710221229471523696
Short name T52
Test name
Test status
Simulation time 5924944675 ps
CPU time 573.11 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:13:15 PM PST 23
Peak memory 580640 kb
Host smart-999d3618-5f93-445d-8421-3cdcf4965448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18989590581593288935451241761360675236598299181319247628944710221229471523696 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.18989590581593288935451241761360675236598299181319247628944710221229471523696
Directory /workspace/6.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.67737032858912746216072136892740495986575506708465147992685833170842302106521
Short name T1417
Test name
Test status
Simulation time 30604932618 ps
CPU time 2953.17 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:52:54 PM PST 23
Peak memory 580488 kb
Host smart-7b258a71-6f89-42ed-a4d0-2314657906a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6773703285891274621607213689274049598
6575506708465147992685833170842302106521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.6773703285891274621607213
6892740495986575506708465147992685833170842302106521
Directory /workspace/6.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.chip_tl_errors.54020385883026337450500622614129807570690251587405302177094178126458691464208
Short name T844
Test name
Test status
Simulation time 3069924257 ps
CPU time 173.31 seconds
Started Nov 22 03:03:29 PM PST 23
Finished Nov 22 03:06:23 PM PST 23
Peak memory 580432 kb
Host smart-562b4835-8cce-4d66-9795-03b6decd7224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54020385883026337450500622614129807570690251587405302177094178126458691464208 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.54020385883026337450500622614129807570690251587405302177094178126458691464208
Directory /workspace/6.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device.14387887868980443638059125213589627105203737142720666846050420622375030187358
Short name T394
Test name
Test status
Simulation time 2590995727 ps
CPU time 103.71 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:05:26 PM PST 23
Peak memory 554692 kb
Host smart-1cf7f879-3bb1-4570-bd5d-f5b287b7a1e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387887868980443638059125213589627105203737142720666846050420622375030187358 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.14387887868980443638059125213589627105203737142720666846050420622375030187358
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.114138850759032630544316504332460756301518239919178606915922873627478068407696
Short name T845
Test name
Test status
Simulation time 115195295727 ps
CPU time 2040.45 seconds
Started Nov 22 03:03:31 PM PST 23
Finished Nov 22 03:37:33 PM PST 23
Peak memory 554744 kb
Host smart-8708ebb4-508b-465b-a389-06dec4983131
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114138850759032630544316504332460756301518239919178606915922873627478068407696 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.114138850759032630544316504332460756301518239919178606915922873627478068407696
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.56296270320637361226454252327857040315767640765109175137827574149757990962725
Short name T420
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.3 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:04:28 PM PST 23
Peak memory 553508 kb
Host smart-426985c8-e617-4144-8713-592bae104285
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56296270320637361226454252327857040315767640765109175137827574149757990962725 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.56296270320637361226454252327857040315767640765109175137827574149757990962725
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_random.46314011507574365885078185264076012092513664005285892474809397745289791931712
Short name T1902
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.72 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:04:43 PM PST 23
Peak memory 553524 kb
Host smart-a9774ece-d9c2-42db-93cf-281752a18bdd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46314011507574365885078185264076012092513664005285892474809397745289791931712 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.xbar_error_random.46314011507574365885078185264076012092513664005285892474809397745289791931712
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random.79446690430180380571659649272040009222395798946710759983076733860185647105397
Short name T1110
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.47 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:04:58 PM PST 23
Peak memory 553752 kb
Host smart-396e56e8-5243-4515-8175-0690b63a3402
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79446690430180380571659649272040009222395798946710759983076733860185647105397 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.xbar_random.79446690430180380571659649272040009222395798946710759983076733860185647105397
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.111163754714442240555338271497192292123367617531821490750938549712651240047371
Short name T843
Test name
Test status
Simulation time 97702135727 ps
CPU time 1149.1 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:22:44 PM PST 23
Peak memory 553652 kb
Host smart-de0fc796-2926-482f-b002-7ac20d20db50
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111163754714442240555338271497192292123367617531821490750938549712651240047371 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.111163754714442240555338271497192292123367617531821490750938549712651240047371
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.10707438443673494968729972368962401528028150006152981706437777904511266381684
Short name T842
Test name
Test status
Simulation time 60576345727 ps
CPU time 1078.49 seconds
Started Nov 22 03:03:55 PM PST 23
Finished Nov 22 03:21:54 PM PST 23
Peak memory 553632 kb
Host smart-9ce5e5a1-11de-44d6-89da-649a727ccbce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707438443673494968729972368962401528028150006152981706437777904511266381684 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.10707438443673494968729972368962401528028150006152981706437777904511266381684
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.1132989810764065640230395574006554740796806597232065102547355491256820229257
Short name T362
Test name
Test status
Simulation time 556965727 ps
CPU time 44.37 seconds
Started Nov 22 03:03:35 PM PST 23
Finished Nov 22 03:04:20 PM PST 23
Peak memory 553628 kb
Host smart-77042c42-530b-42d9-9ad8-e9c863e1fd73
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132989810764065640230395574006554740796806597232065102547355491256820229257 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1132989810764065640230395574006554740796806597232065102547355491256820229257
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_same_source.65732350122124174495800625797222420117265120457928457727125639356287725216455
Short name T1044
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.64 seconds
Started Nov 22 03:03:36 PM PST 23
Finished Nov 22 03:04:50 PM PST 23
Peak memory 553820 kb
Host smart-4d91b5fa-cf8c-4d54-abb7-dd315f1ed637
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65732350122124174495800625797222420117265120457928457727125639356287725216455 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.65732350122124174495800625797222420117265120457928457727125639356287725216455
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke.46633722278953188341641565915705056462510736766040513669984449375652261324282
Short name T1775
Test name
Test status
Simulation time 196985727 ps
CPU time 8.23 seconds
Started Nov 22 03:03:32 PM PST 23
Finished Nov 22 03:03:41 PM PST 23
Peak memory 552328 kb
Host smart-a517d6fa-c9bd-4f5a-a79c-25d2bbbbb299
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46633722278953188341641565915705056462510736766040513669984449375652261324282 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.xbar_smoke.46633722278953188341641565915705056462510736766040513669984449375652261324282
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.98598743310709614314289458340153533810385642029096572066711669226189522459001
Short name T255
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.18 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:05:02 PM PST 23
Peak memory 552392 kb
Host smart-5844a9cb-fa2c-4e15-a248-ebecefcbc92d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98598743310709614314289458340153533810385642029096572066711669226189522459001 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.98598743310709614314289458340153533810385642029096572066711669226189522459001
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.107857849061974982074851768448465965716908994023078452447615208271280940687879
Short name T1842
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.22 seconds
Started Nov 22 03:03:34 PM PST 23
Finished Nov 22 03:04:59 PM PST 23
Peak memory 552392 kb
Host smart-a14da068-2194-4bb6-af65-a7083f3d0b41
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107857849061974982074851768448465965716908994023078452447615208271280940687879 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.107857849061974982074851768448465965716908994023078452447615208271280940687879
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.84884953881934749987916873968578956110615475062141220961890865204379569181557
Short name T277
Test name
Test status
Simulation time 45555727 ps
CPU time 5.88 seconds
Started Nov 22 03:03:33 PM PST 23
Finished Nov 22 03:03:40 PM PST 23
Peak memory 552356 kb
Host smart-9c95aa32-4935-4f5d-90fd-f9ef05cbc20d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84884953881934749987916873968578956110615475062141220961890865204379569181557 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.84884953881934749987916873968578956110615475062141220961890865204379569181557
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all.3246633603792369062569233898574677525421266414736654662860509579912049314163
Short name T1745
Test name
Test status
Simulation time 13992004073 ps
CPU time 550.97 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:12:55 PM PST 23
Peak memory 555776 kb
Host smart-cf67626b-412f-48a8-8f95-25d9e0766d3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246633603792369062569233898574677525421266414736654662860509579912049314163 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3246633603792369062569233898574677525421266414736654662860509579912049314163
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.12597736412119377147481586082839413125292065525657032884736478724480900475794
Short name T871
Test name
Test status
Simulation time 13999524073 ps
CPU time 480.98 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:11:40 PM PST 23
Peak memory 555820 kb
Host smart-41583fb2-df2e-4d45-8b68-84d94bd3f9a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12597736412119377147481586082839413125292065525657032884736478724480900475794 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.12597736412119377147481586082839413125292065525657032884736478724480900475794
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.82738294544419895496030404594909723268657103029295531809905326184967249251433
Short name T989
Test name
Test status
Simulation time 4815189184 ps
CPU time 383.86 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:10:20 PM PST 23
Peak memory 557368 kb
Host smart-7eac3fd6-64ae-4212-9bad-9b5fb56e2951
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82738294544419895496030404594909723268657103029295531809905326184967249251433 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.827382945444198954960304045949097232686571030292955318099053261
84967249251433
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.11724080285316364723924943250136003867718629573559636356550439348165212443570
Short name T945
Test name
Test status
Simulation time 4815189184 ps
CPU time 306.4 seconds
Started Nov 22 03:04:00 PM PST 23
Finished Nov 22 03:09:07 PM PST 23
Peak memory 559712 kb
Host smart-5cdd9bef-98a6-498d-8706-a958e4e21fd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11724080285316364723924943250136003867718629573559636356550439348165212443570 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1172408028531636472392494325013600386771862957355963635655043
9348165212443570
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.99999824652346820957807743774516318705555449705927918324082006764523602543332
Short name T1187
Test name
Test status
Simulation time 1176995727 ps
CPU time 43.87 seconds
Started Nov 22 03:03:42 PM PST 23
Finished Nov 22 03:04:27 PM PST 23
Peak memory 553684 kb
Host smart-b34d905e-7f20-4957-828d-0420dd3bc4d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99999824652346820957807743774516318705555449705927918324082006764523602543332 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.99999824652346820957807743774516318705555449705927918324082006764523602543332
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device.26786365337475538678081268975498819900731681095811935560473071532357506018544
Short name T1506
Test name
Test status
Simulation time 2590995727 ps
CPU time 111.57 seconds
Started Nov 22 03:08:45 PM PST 23
Finished Nov 22 03:10:37 PM PST 23
Peak memory 554792 kb
Host smart-a2a60baa-9a61-48df-b392-471a89b02e7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26786365337475538678081268975498819900731681095811935560473071532357506018544 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.26786365337475538678081268975498819900731681095811935560473071532357506018544
Directory /workspace/60.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.91049981141011766965873035449606458808538086044746871453320795368645392922247
Short name T1129
Test name
Test status
Simulation time 115195295727 ps
CPU time 2014.56 seconds
Started Nov 22 03:08:44 PM PST 23
Finished Nov 22 03:42:19 PM PST 23
Peak memory 554816 kb
Host smart-af96873b-1552-4c8c-9dd4-d198833c18b5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91049981141011766965873035449606458808538086044746871453320795368645392922247 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device_slow_rsp.91049981141011766965873035449606458808538086044746871453320795368645392922247
Directory /workspace/60.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.56263195553032873414724027068128899183999928163711678930149701311574199217538
Short name T1811
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.35 seconds
Started Nov 22 03:08:45 PM PST 23
Finished Nov 22 03:09:31 PM PST 23
Peak memory 553480 kb
Host smart-9923f898-c990-4f1b-aa14-89add5a90c4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56263195553032873414724027068128899183999928163711678930149701311574199217538 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr.56263195553032873414724027068128899183999928163711678930149701311574199217538
Directory /workspace/60.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_random.96995966090394673050981511654817540794222160611810351743799284392698674750047
Short name T1853
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.45 seconds
Started Nov 22 03:08:41 PM PST 23
Finished Nov 22 03:09:57 PM PST 23
Peak memory 553496 kb
Host smart-5a683678-d1ba-47ff-b7ae-0bce86ff8502
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96995966090394673050981511654817540794222160611810351743799284392698674750047 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 60.xbar_error_random.96995966090394673050981511654817540794222160611810351743799284392698674750047
Directory /workspace/60.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random.13435101517322531363146591706048245229361057163616399604591572764500989458190
Short name T678
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.52 seconds
Started Nov 22 03:08:45 PM PST 23
Finished Nov 22 03:10:07 PM PST 23
Peak memory 553576 kb
Host smart-f3e20b22-8ffa-4201-977e-e6301a612299
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13435101517322531363146591706048245229361057163616399604591572764500989458190 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 60.xbar_random.13435101517322531363146591706048245229361057163616399604591572764500989458190
Directory /workspace/60.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.102867449606603668720351512727940224982993181471551459155219672587973063146389
Short name T1865
Test name
Test status
Simulation time 97702135727 ps
CPU time 1126 seconds
Started Nov 22 03:08:43 PM PST 23
Finished Nov 22 03:27:30 PM PST 23
Peak memory 553632 kb
Host smart-71414301-5664-4475-a748-91d0121829e9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102867449606603668720351512727940224982993181471551459155219672587973063146389 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.102867449606603668720351512727940224982993181471551459155219672587973063146389
Directory /workspace/60.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.47092079562454166118760344802080290375784408258600574955461556185333065977780
Short name T714
Test name
Test status
Simulation time 60576345727 ps
CPU time 1094.19 seconds
Started Nov 22 03:08:42 PM PST 23
Finished Nov 22 03:26:57 PM PST 23
Peak memory 553700 kb
Host smart-24fc5cc3-3fc1-45bd-9833-be76f563138b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47092079562454166118760344802080290375784408258600574955461556185333065977780 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.47092079562454166118760344802080290375784408258600574955461556185333065977780
Directory /workspace/60.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.59534105619645702032331279763437950642041427933201181176465171506019166248441
Short name T1736
Test name
Test status
Simulation time 556965727 ps
CPU time 55.25 seconds
Started Nov 22 03:08:43 PM PST 23
Finished Nov 22 03:09:39 PM PST 23
Peak memory 553708 kb
Host smart-905e46fe-38fa-4d0e-bb19-5186b74124c2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59534105619645702032331279763437950642041427933201181176465171506019166248441 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_delays.59534105619645702032331279763437950642041427933201181176465171506019166248441
Directory /workspace/60.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_same_source.103177229561404871121595380523612089724496460724619933052186932133055167634080
Short name T1718
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.3 seconds
Started Nov 22 03:08:44 PM PST 23
Finished Nov 22 03:10:01 PM PST 23
Peak memory 553728 kb
Host smart-bd03eddf-a8dc-4d65-b38b-25fb1ef0b9e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103177229561404871121595380523612089724496460724619933052186932133055167634080 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.103177229561404871121595380523612089724496460724619933052186932133055167634080
Directory /workspace/60.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke.88075182672356119248989589213832974030438727286832807768079029171137684955697
Short name T520
Test name
Test status
Simulation time 196985727 ps
CPU time 9 seconds
Started Nov 22 03:08:52 PM PST 23
Finished Nov 22 03:09:01 PM PST 23
Peak memory 552480 kb
Host smart-826354c2-8e01-4ed7-a11f-e71de302988b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88075182672356119248989589213832974030438727286832807768079029171137684955697 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 60.xbar_smoke.88075182672356119248989589213832974030438727286832807768079029171137684955697
Directory /workspace/60.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.13982568840085650028077372855579564248516949114349112214027397978892002193698
Short name T638
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.16 seconds
Started Nov 22 03:08:37 PM PST 23
Finished Nov 22 03:10:10 PM PST 23
Peak memory 552336 kb
Host smart-0d9adfaf-7d51-4ed1-864c-f2ba876bf6ec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13982568840085650028077372855579564248516949114349112214027397978892002193698 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.13982568840085650028077372855579564248516949114349112214027397978892002193698
Directory /workspace/60.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.52826546478019091987844312825231790383184579245462727597205938426925413339773
Short name T1379
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.68 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:15 PM PST 23
Peak memory 552508 kb
Host smart-a90b686e-f371-49b2-b405-7c5c070dc9f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52826546478019091987844312825231790383184579245462727597205938426925413339773 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.52826546478019091987844312825231790383184579245462727597205938426925413339773
Directory /workspace/60.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.60008041264536816675326092269270116606000046135811907568888860194419877749796
Short name T1637
Test name
Test status
Simulation time 45555727 ps
CPU time 6.41 seconds
Started Nov 22 03:08:36 PM PST 23
Finished Nov 22 03:08:43 PM PST 23
Peak memory 552276 kb
Host smart-4c2f5e0c-acbd-4de5-a7c0-62889ca42df0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60008041264536816675326092269270116606000046135811907568888860194419877749796 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.60008041264536816675326092269270116606000046135811907568888860194419877749796
Directory /workspace/60.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all.109005337713532603741870155256857800799682676690045714168040678911579451268727
Short name T968
Test name
Test status
Simulation time 13992004073 ps
CPU time 551.75 seconds
Started Nov 22 03:08:43 PM PST 23
Finished Nov 22 03:17:56 PM PST 23
Peak memory 555908 kb
Host smart-f8ebbced-387b-4f9a-892a-9436d43c45fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109005337713532603741870155256857800799682676690045714168040678911579451268727 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.109005337713532603741870155256857800799682676690045714168040678911579451268727
Directory /workspace/60.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.62105139026124007830597659016013847425836460545616585295330336969437056495204
Short name T1381
Test name
Test status
Simulation time 13999524073 ps
CPU time 511.81 seconds
Started Nov 22 03:08:41 PM PST 23
Finished Nov 22 03:17:14 PM PST 23
Peak memory 555672 kb
Host smart-2b572df1-64a6-4a88-9eca-5487bc83d50b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62105139026124007830597659016013847425836460545616585295330336969437056495204 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.62105139026124007830597659016013847425836460545616585295330336969437056495204
Directory /workspace/60.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.34240797939662950313349032522073005368492216163413712512173686614594204608617
Short name T950
Test name
Test status
Simulation time 4815189184 ps
CPU time 368.55 seconds
Started Nov 22 03:08:45 PM PST 23
Finished Nov 22 03:14:55 PM PST 23
Peak memory 557248 kb
Host smart-b76b93bd-b9fa-4ad7-a0c1-4e1d4d2cfa13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34240797939662950313349032522073005368492216163413712512173686614594204608617 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_rand_reset.34240797939662950313349032522073005368492216163413712512173686
614594204608617
Directory /workspace/60.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.89610094696112788119447598922127518965926621567126648690683539683839079072518
Short name T1291
Test name
Test status
Simulation time 4815189184 ps
CPU time 329.44 seconds
Started Nov 22 03:08:45 PM PST 23
Finished Nov 22 03:14:15 PM PST 23
Peak memory 559820 kb
Host smart-9d1ffaac-3967-4e05-a36a-72cbfb16215e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89610094696112788119447598922127518965926621567126648690683539683839079072518 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_reset_error.896100946961127881194475989221275189659266215671266486906835
39683839079072518
Directory /workspace/60.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.81265926166209870200367011763109716279671552332181212909149940305677625516678
Short name T1758
Test name
Test status
Simulation time 1176995727 ps
CPU time 53.45 seconds
Started Nov 22 03:08:45 PM PST 23
Finished Nov 22 03:09:39 PM PST 23
Peak memory 553728 kb
Host smart-f721585e-a7f0-478f-8b15-bd2c53ac909e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81265926166209870200367011763109716279671552332181212909149940305677625516678 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.81265926166209870200367011763109716279671552332181212909149940305677625516678
Directory /workspace/60.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device.6617605057006374489198064539829689710578942334170947991461297346651720450929
Short name T763
Test name
Test status
Simulation time 2590995727 ps
CPU time 114.73 seconds
Started Nov 22 03:09:03 PM PST 23
Finished Nov 22 03:10:58 PM PST 23
Peak memory 554756 kb
Host smart-e3835c05-f5eb-43e6-beb4-89d3f6f34494
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6617605057006374489198064539829689710578942334170947991461297346651720450929 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.6617605057006374489198064539829689710578942334170947991461297346651720450929
Directory /workspace/61.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.20242263701229209196395409199995990498836127325855348104764169622373888641612
Short name T1427
Test name
Test status
Simulation time 115195295727 ps
CPU time 2029.92 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:42:40 PM PST 23
Peak memory 554760 kb
Host smart-11df3711-7922-49cd-876e-d2b114df205b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20242263701229209196395409199995990498836127325855348104764169622373888641612 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device_slow_rsp.20242263701229209196395409199995990498836127325855348104764169622373888641612
Directory /workspace/61.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.54487738800930535667397867259111978537852245057943127229859192793539655743806
Short name T1293
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.35 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:09:35 PM PST 23
Peak memory 553468 kb
Host smart-c9e3c79e-52c1-45f4-b20c-6b0b3d2951e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54487738800930535667397867259111978537852245057943127229859192793539655743806 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.54487738800930535667397867259111978537852245057943127229859192793539655743806
Directory /workspace/61.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_random.19293833541959686486023930023548992125576978312478936747272344140276770385135
Short name T1647
Test name
Test status
Simulation time 2231375727 ps
CPU time 66.45 seconds
Started Nov 22 03:09:02 PM PST 23
Finished Nov 22 03:10:09 PM PST 23
Peak memory 553500 kb
Host smart-d0ddfac3-e244-4073-9c1e-2fb9ba704d32
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293833541959686486023930023548992125576978312478936747272344140276770385135 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 61.xbar_error_random.19293833541959686486023930023548992125576978312478936747272344140276770385135
Directory /workspace/61.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random.91709014200717137094157406339420775819371232857680389800350617579188475994951
Short name T368
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.71 seconds
Started Nov 22 03:09:02 PM PST 23
Finished Nov 22 03:10:17 PM PST 23
Peak memory 553716 kb
Host smart-3882c050-24c4-4f02-bbb3-ec40f4dd6334
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91709014200717137094157406339420775819371232857680389800350617579188475994951 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 61.xbar_random.91709014200717137094157406339420775819371232857680389800350617579188475994951
Directory /workspace/61.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.87523833696800054727141607307755588604721835564884254519075406240895820735142
Short name T1006
Test name
Test status
Simulation time 97702135727 ps
CPU time 1174.62 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:28:25 PM PST 23
Peak memory 553636 kb
Host smart-17fa80ff-8720-41c1-b7f0-e7715a13ea00
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87523833696800054727141607307755588604721835564884254519075406240895820735142 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.87523833696800054727141607307755588604721835564884254519075406240895820735142
Directory /workspace/61.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.10777012457921295005039196649387249123491980080658570332425114160950766218649
Short name T1069
Test name
Test status
Simulation time 60576345727 ps
CPU time 1135.1 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:27:44 PM PST 23
Peak memory 553724 kb
Host smart-a3f89ffc-c576-443d-a868-35eb537d6b60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10777012457921295005039196649387249123491980080658570332425114160950766218649 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.10777012457921295005039196649387249123491980080658570332425114160950766218649
Directory /workspace/61.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.96750893461414530523426386447372066113535011090160216301309256464934470798949
Short name T1651
Test name
Test status
Simulation time 556965727 ps
CPU time 43.21 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:09:34 PM PST 23
Peak memory 553656 kb
Host smart-c03623dd-75f7-46dd-adce-a6f3c9a4979d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96750893461414530523426386447372066113535011090160216301309256464934470798949 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_delays.96750893461414530523426386447372066113535011090160216301309256464934470798949
Directory /workspace/61.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_same_source.36264364603825619611371171609217302791526099179354772522548727505804416645693
Short name T5
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.67 seconds
Started Nov 22 03:09:02 PM PST 23
Finished Nov 22 03:10:14 PM PST 23
Peak memory 553692 kb
Host smart-06336e34-6eee-4e80-8daa-d6d2bf9bbfef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36264364603825619611371171609217302791526099179354772522548727505804416645693 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.36264364603825619611371171609217302791526099179354772522548727505804416645693
Directory /workspace/61.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke.34025069146318533212674822485518958049581437773271661047020502961564758368516
Short name T923
Test name
Test status
Simulation time 196985727 ps
CPU time 8.56 seconds
Started Nov 22 03:08:42 PM PST 23
Finished Nov 22 03:08:51 PM PST 23
Peak memory 552360 kb
Host smart-f3ab7f33-7943-4982-921b-f558581a8fae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025069146318533212674822485518958049581437773271661047020502961564758368516 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 61.xbar_smoke.34025069146318533212674822485518958049581437773271661047020502961564758368516
Directory /workspace/61.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.90906161384204454487555782226399658657547100958571836007340683499880504908969
Short name T847
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.05 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:21 PM PST 23
Peak memory 552392 kb
Host smart-161d5d5d-6d05-47f1-87ab-d3d451300df3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90906161384204454487555782226399658657547100958571836007340683499880504908969 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.90906161384204454487555782226399658657547100958571836007340683499880504908969
Directory /workspace/61.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3976203047366663453521350083736740395133902437808347659731508844784932661556
Short name T1852
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.21 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:10:19 PM PST 23
Peak memory 552404 kb
Host smart-29920b48-be82-4272-b8ee-fe6a609fc3e6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976203047366663453521350083736740395133902437808347659731508844784932661556 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3976203047366663453521350083736740395133902437808347659731508844784932661556
Directory /workspace/61.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.29465929689299352268791483028598734633360590752227511675846603198249082276645
Short name T1380
Test name
Test status
Simulation time 45555727 ps
CPU time 6.11 seconds
Started Nov 22 03:08:52 PM PST 23
Finished Nov 22 03:08:59 PM PST 23
Peak memory 552472 kb
Host smart-35847a22-f9a6-49c4-96be-f6e1a0faccd0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29465929689299352268791483028598734633360590752227511675846603198249082276645 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays.29465929689299352268791483028598734633360590752227511675846603198249082276645
Directory /workspace/61.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all.73834611939765809235337409949579261852108809918872166438766456031683107595541
Short name T961
Test name
Test status
Simulation time 13992004073 ps
CPU time 539.6 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:17:50 PM PST 23
Peak memory 555908 kb
Host smart-f8e0cf5b-351e-48b5-a3c4-20538bfb133d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73834611939765809235337409949579261852108809918872166438766456031683107595541 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.73834611939765809235337409949579261852108809918872166438766456031683107595541
Directory /workspace/61.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.30024707832202589211693395467304279701233257332068062397878701615519414273798
Short name T1336
Test name
Test status
Simulation time 13999524073 ps
CPU time 500.95 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:17:10 PM PST 23
Peak memory 555616 kb
Host smart-a132f485-abad-400c-9fae-b25cc5690752
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30024707832202589211693395467304279701233257332068062397878701615519414273798 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.30024707832202589211693395467304279701233257332068062397878701615519414273798
Directory /workspace/61.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.48597513185233672092955033288855508468710171283178614973544001640039100814110
Short name T517
Test name
Test status
Simulation time 4815189184 ps
CPU time 355.25 seconds
Started Nov 22 03:09:02 PM PST 23
Finished Nov 22 03:14:58 PM PST 23
Peak memory 557212 kb
Host smart-0fda402d-6c03-4c7a-85ba-b4b182d95702
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48597513185233672092955033288855508468710171283178614973544001640039100814110 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_rand_reset.48597513185233672092955033288855508468710171283178614973544001
640039100814110
Directory /workspace/61.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.8450534403945999875204351991896560537769881318985522734233257795193088674244
Short name T1551
Test name
Test status
Simulation time 4815189184 ps
CPU time 328.07 seconds
Started Nov 22 03:08:51 PM PST 23
Finished Nov 22 03:14:20 PM PST 23
Peak memory 559648 kb
Host smart-45ed1181-b468-4e43-aa2e-da1fb8cd8568
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8450534403945999875204351991896560537769881318985522734233257795193088674244 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_reset_error.8450534403945999875204351991896560537769881318985522734233257
795193088674244
Directory /workspace/61.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.46353032491231123319374436598491443938744448011217668403144540885593498050423
Short name T1494
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.74 seconds
Started Nov 22 03:08:48 PM PST 23
Finished Nov 22 03:09:34 PM PST 23
Peak memory 553688 kb
Host smart-cb9bf2f1-c2b0-4686-9df5-f5cc17a0957e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46353032491231123319374436598491443938744448011217668403144540885593498050423 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.46353032491231123319374436598491443938744448011217668403144540885593498050423
Directory /workspace/61.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device.61244395096459265073757330005237650725275469712477834798220737483317999255819
Short name T586
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.49 seconds
Started Nov 22 03:08:53 PM PST 23
Finished Nov 22 03:10:40 PM PST 23
Peak memory 554376 kb
Host smart-c659eba5-78e3-4353-8b61-2beb5141496a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61244395096459265073757330005237650725275469712477834798220737483317999255819 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.61244395096459265073757330005237650725275469712477834798220737483317999255819
Directory /workspace/62.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.97493181815898273688317461366901323804417233963722476664530785093288861786093
Short name T501
Test name
Test status
Simulation time 115195295727 ps
CPU time 2036.03 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:42:46 PM PST 23
Peak memory 554792 kb
Host smart-8cad4eb4-4b86-47cf-b8e2-5927fbaec034
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97493181815898273688317461366901323804417233963722476664530785093288861786093 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device_slow_rsp.97493181815898273688317461366901323804417233963722476664530785093288861786093
Directory /workspace/62.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.86467613593106538030470712820698512489364707187768779487090656326506832875367
Short name T1002
Test name
Test status
Simulation time 1171215727 ps
CPU time 50.55 seconds
Started Nov 22 03:09:13 PM PST 23
Finished Nov 22 03:10:04 PM PST 23
Peak memory 553468 kb
Host smart-5c6a8669-fc42-4056-b55c-204a30854c90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86467613593106538030470712820698512489364707187768779487090656326506832875367 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr.86467613593106538030470712820698512489364707187768779487090656326506832875367
Directory /workspace/62.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_random.74321360185131987632944162967480758236812052973353981791323549193380272094486
Short name T1020
Test name
Test status
Simulation time 2231375727 ps
CPU time 83.07 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:14 PM PST 23
Peak memory 553524 kb
Host smart-8cbd93c5-6c60-4d55-bbe1-ecf6a81d599b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74321360185131987632944162967480758236812052973353981791323549193380272094486 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 62.xbar_error_random.74321360185131987632944162967480758236812052973353981791323549193380272094486
Directory /workspace/62.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random.106933205363423188499679565892561686389909484364188053939966018321457618705318
Short name T1130
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.62 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:10:02 PM PST 23
Peak memory 553728 kb
Host smart-97fea898-b75d-43f9-9611-c9a7ae4d8761
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106933205363423188499679565892561686389909484364188053939966018321457618705318 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 62.xbar_random.106933205363423188499679565892561686389909484364188053939966018321457618705318
Directory /workspace/62.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.106675057663039730757159549207135210355138922371053703008330559085997979327100
Short name T1273
Test name
Test status
Simulation time 97702135727 ps
CPU time 1186.44 seconds
Started Nov 22 03:08:51 PM PST 23
Finished Nov 22 03:28:38 PM PST 23
Peak memory 553676 kb
Host smart-77c0da26-2297-4a12-b68a-6bc1b3db3f1e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106675057663039730757159549207135210355138922371053703008330559085997979327100 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.106675057663039730757159549207135210355138922371053703008330559085997979327100
Directory /workspace/62.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.11391648615875880214826348941281456601074800643243334839880427355793089253161
Short name T1618
Test name
Test status
Simulation time 60576345727 ps
CPU time 1133.54 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:27:44 PM PST 23
Peak memory 553620 kb
Host smart-71942423-be4e-454e-b1b6-bf5456ae3953
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11391648615875880214826348941281456601074800643243334839880427355793089253161 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.11391648615875880214826348941281456601074800643243334839880427355793089253161
Directory /workspace/62.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.61823877339549169002186095112349382705203031634587467710124088910533845137113
Short name T1307
Test name
Test status
Simulation time 556965727 ps
CPU time 44.49 seconds
Started Nov 22 03:08:53 PM PST 23
Finished Nov 22 03:09:38 PM PST 23
Peak memory 553292 kb
Host smart-bd529bf3-e3f9-4085-9571-cc0bbcb5e9fc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61823877339549169002186095112349382705203031634587467710124088910533845137113 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_delays.61823877339549169002186095112349382705203031634587467710124088910533845137113
Directory /workspace/62.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_same_source.5883407107483274378422323130766053862761304282130340747798489959457032033387
Short name T498
Test name
Test status
Simulation time 2498784073 ps
CPU time 77.96 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:09 PM PST 23
Peak memory 553664 kb
Host smart-fe9102ea-988e-4bb2-876c-52ece8d722e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5883407107483274378422323130766053862761304282130340747798489959457032033387 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.5883407107483274378422323130766053862761304282130340747798489959457032033387
Directory /workspace/62.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke.73788071797285441525273611770799671177088543955268406468729615653943201504904
Short name T956
Test name
Test status
Simulation time 196985727 ps
CPU time 9.02 seconds
Started Nov 22 03:08:51 PM PST 23
Finished Nov 22 03:09:01 PM PST 23
Peak memory 552352 kb
Host smart-24ea27e3-ae43-4a93-ae8d-6a781dfba9f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73788071797285441525273611770799671177088543955268406468729615653943201504904 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 62.xbar_smoke.73788071797285441525273611770799671177088543955268406468729615653943201504904
Directory /workspace/62.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.54972588089320468673027601021862375093530927083472681497203556748564180476622
Short name T611
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.21 seconds
Started Nov 22 03:08:51 PM PST 23
Finished Nov 22 03:10:22 PM PST 23
Peak memory 552392 kb
Host smart-290bd554-4315-4a10-92e8-244af0a2bcb8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54972588089320468673027601021862375093530927083472681497203556748564180476622 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.54972588089320468673027601021862375093530927083472681497203556748564180476622
Directory /workspace/62.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.10022574549386680646392562339519905826430997842010541605546028395575892181651
Short name T1911
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.73 seconds
Started Nov 22 03:08:50 PM PST 23
Finished Nov 22 03:10:21 PM PST 23
Peak memory 552332 kb
Host smart-f56ce039-5f97-4ba8-a744-2f6ddfa97f03
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10022574549386680646392562339519905826430997842010541605546028395575892181651 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.10022574549386680646392562339519905826430997842010541605546028395575892181651
Directory /workspace/62.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.86686709006921211050433570539709229914068357344004550253808082383744966247894
Short name T119
Test name
Test status
Simulation time 45555727 ps
CPU time 6.37 seconds
Started Nov 22 03:08:49 PM PST 23
Finished Nov 22 03:08:56 PM PST 23
Peak memory 552400 kb
Host smart-5a65841b-96b8-4582-97f0-6cba77749132
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86686709006921211050433570539709229914068357344004550253808082383744966247894 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays.86686709006921211050433570539709229914068357344004550253808082383744966247894
Directory /workspace/62.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all.11951337075149785341827770866687274475376531824639670895045656317243549052360
Short name T858
Test name
Test status
Simulation time 13992004073 ps
CPU time 611.22 seconds
Started Nov 22 03:09:13 PM PST 23
Finished Nov 22 03:19:24 PM PST 23
Peak memory 555920 kb
Host smart-1bb66a15-85be-4484-9ca7-568ce7a97ef8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11951337075149785341827770866687274475376531824639670895045656317243549052360 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.11951337075149785341827770866687274475376531824639670895045656317243549052360
Directory /workspace/62.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.60682440017045804182437276138215211794614575150351414463397048858554648905866
Short name T1213
Test name
Test status
Simulation time 13999524073 ps
CPU time 479.99 seconds
Started Nov 22 03:09:11 PM PST 23
Finished Nov 22 03:17:11 PM PST 23
Peak memory 555696 kb
Host smart-88b7f279-e0d8-492e-90d3-3013c0f59896
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60682440017045804182437276138215211794614575150351414463397048858554648905866 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.60682440017045804182437276138215211794614575150351414463397048858554648905866
Directory /workspace/62.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.23888088566862454751038739491105958425727916051542163465646501902599847300893
Short name T1840
Test name
Test status
Simulation time 4815189184 ps
CPU time 390.57 seconds
Started Nov 22 03:09:18 PM PST 23
Finished Nov 22 03:15:49 PM PST 23
Peak memory 557252 kb
Host smart-5e5d1e86-4e58-4518-8cf1-071d2dfa8c45
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23888088566862454751038739491105958425727916051542163465646501902599847300893 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_rand_reset.23888088566862454751038739491105958425727916051542163465646501
902599847300893
Directory /workspace/62.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.109494074599337499140056037696747756021178767076671773319714797008739742537316
Short name T1627
Test name
Test status
Simulation time 4815189184 ps
CPU time 336.17 seconds
Started Nov 22 03:09:09 PM PST 23
Finished Nov 22 03:14:46 PM PST 23
Peak memory 559628 kb
Host smart-b30371a9-233c-4af2-924a-5be039879998
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109494074599337499140056037696747756021178767076671773319714797008739742537316 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_reset_error.10949407459933749914005603769674775602117876707667177331971
4797008739742537316
Directory /workspace/62.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.41212774653294409607410356611483422142889516838776810528604538952621535742159
Short name T1448
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.25 seconds
Started Nov 22 03:08:53 PM PST 23
Finished Nov 22 03:09:40 PM PST 23
Peak memory 553304 kb
Host smart-147514d8-b504-4394-a080-6c850a671a9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41212774653294409607410356611483422142889516838776810528604538952621535742159 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.41212774653294409607410356611483422142889516838776810528604538952621535742159
Directory /workspace/62.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device.62152590173245080799085509724837062285338935204793872983194702456475463418605
Short name T1160
Test name
Test status
Simulation time 2590995727 ps
CPU time 101.71 seconds
Started Nov 22 03:09:05 PM PST 23
Finished Nov 22 03:10:47 PM PST 23
Peak memory 554764 kb
Host smart-a61478f9-5a82-4110-bde8-3aa41c1bf918
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62152590173245080799085509724837062285338935204793872983194702456475463418605 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device.62152590173245080799085509724837062285338935204793872983194702456475463418605
Directory /workspace/63.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.32756196625925843894503170249634348591272340338563877446850231113485792472795
Short name T1496
Test name
Test status
Simulation time 115195295727 ps
CPU time 1994.88 seconds
Started Nov 22 03:09:10 PM PST 23
Finished Nov 22 03:42:26 PM PST 23
Peak memory 554780 kb
Host smart-2fef6007-90d3-425f-919d-646772b793c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32756196625925843894503170249634348591272340338563877446850231113485792472795 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device_slow_rsp.32756196625925843894503170249634348591272340338563877446850231113485792472795
Directory /workspace/63.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.51623294320178228787559738492467138722940779832330679790618480169358207518279
Short name T374
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.28 seconds
Started Nov 22 03:09:10 PM PST 23
Finished Nov 22 03:09:56 PM PST 23
Peak memory 553460 kb
Host smart-1679adba-2c54-465b-9fdf-d968efc1fd10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51623294320178228787559738492467138722940779832330679790618480169358207518279 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr.51623294320178228787559738492467138722940779832330679790618480169358207518279
Directory /workspace/63.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_random.99075966026043424415306394476420446045308727138434637158496848976047653842527
Short name T1045
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.82 seconds
Started Nov 22 03:09:17 PM PST 23
Finished Nov 22 03:10:34 PM PST 23
Peak memory 553528 kb
Host smart-ace6a043-9162-419a-b74f-7eb56e173777
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99075966026043424415306394476420446045308727138434637158496848976047653842527 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 63.xbar_error_random.99075966026043424415306394476420446045308727138434637158496848976047653842527
Directory /workspace/63.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random.8972274616446956997693498677162474534398506678020950020305211022555587396267
Short name T1211
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.35 seconds
Started Nov 22 03:09:11 PM PST 23
Finished Nov 22 03:10:34 PM PST 23
Peak memory 553808 kb
Host smart-c4b5f0cf-6b46-4def-baf9-8389098dd6d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8972274616446956997693498677162474534398506678020950020305211022555587396267 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 63.xbar_random.8972274616446956997693498677162474534398506678020950020305211022555587396267
Directory /workspace/63.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.108494377920499327406363306863680883307435452196241446415086359098026904771440
Short name T456
Test name
Test status
Simulation time 97702135727 ps
CPU time 1159.26 seconds
Started Nov 22 03:09:20 PM PST 23
Finished Nov 22 03:28:40 PM PST 23
Peak memory 553680 kb
Host smart-cfee50e0-6a7a-4577-af0d-6b62b81b021b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108494377920499327406363306863680883307435452196241446415086359098026904771440 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.108494377920499327406363306863680883307435452196241446415086359098026904771440
Directory /workspace/63.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.96463763879111600109622343261717974454898714029074795238389747352511368818294
Short name T1299
Test name
Test status
Simulation time 60576345727 ps
CPU time 1148 seconds
Started Nov 22 03:09:07 PM PST 23
Finished Nov 22 03:28:15 PM PST 23
Peak memory 553760 kb
Host smart-b4cc2903-61d3-4d89-8aac-835cb1fb46b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96463763879111600109622343261717974454898714029074795238389747352511368818294 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.96463763879111600109622343261717974454898714029074795238389747352511368818294
Directory /workspace/63.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.40999568242199854777685267500961661263674856622182046331466649432537868681998
Short name T1207
Test name
Test status
Simulation time 556965727 ps
CPU time 48.92 seconds
Started Nov 22 03:09:18 PM PST 23
Finished Nov 22 03:10:07 PM PST 23
Peak memory 553692 kb
Host smart-0badec64-23b8-4cdd-814c-4b5b50997279
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40999568242199854777685267500961661263674856622182046331466649432537868681998 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_delays.40999568242199854777685267500961661263674856622182046331466649432537868681998
Directory /workspace/63.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_same_source.72388642035183081608204312152876725855741908087939952680461589417586462527904
Short name T1124
Test name
Test status
Simulation time 2498784073 ps
CPU time 80.6 seconds
Started Nov 22 03:09:05 PM PST 23
Finished Nov 22 03:10:26 PM PST 23
Peak memory 553832 kb
Host smart-a0193ba2-e2ae-4168-8022-d0ff0f66a82b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72388642035183081608204312152876725855741908087939952680461589417586462527904 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.72388642035183081608204312152876725855741908087939952680461589417586462527904
Directory /workspace/63.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke.84530662845967334430099262538617295436593923805824756897715397992340622501624
Short name T969
Test name
Test status
Simulation time 196985727 ps
CPU time 9.05 seconds
Started Nov 22 03:09:15 PM PST 23
Finished Nov 22 03:09:25 PM PST 23
Peak memory 552360 kb
Host smart-20075731-2c79-4bb5-846f-4cc0a1a3ab8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84530662845967334430099262538617295436593923805824756897715397992340622501624 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 63.xbar_smoke.84530662845967334430099262538617295436593923805824756897715397992340622501624
Directory /workspace/63.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.112719285855448454251270439984398826191071805969148475320399762331296384178431
Short name T1466
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.42 seconds
Started Nov 22 03:09:12 PM PST 23
Finished Nov 22 03:10:45 PM PST 23
Peak memory 552320 kb
Host smart-e563e140-3cef-4599-ae63-e9303a14c7c7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112719285855448454251270439984398826191071805969148475320399762331296384178431 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.112719285855448454251270439984398826191071805969148475320399762331296384178431
Directory /workspace/63.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.78833713446909343283886121679497285581449911596615070394771546371303775852168
Short name T188
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.05 seconds
Started Nov 22 03:09:10 PM PST 23
Finished Nov 22 03:10:41 PM PST 23
Peak memory 552376 kb
Host smart-e1f7a1f2-3bfe-4e65-a3d8-4e6120053252
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78833713446909343283886121679497285581449911596615070394771546371303775852168 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.78833713446909343283886121679497285581449911596615070394771546371303775852168
Directory /workspace/63.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.21954289151328755872646753529568179872443416441054142401988951783979724020800
Short name T1904
Test name
Test status
Simulation time 45555727 ps
CPU time 5.93 seconds
Started Nov 22 03:09:17 PM PST 23
Finished Nov 22 03:09:23 PM PST 23
Peak memory 552364 kb
Host smart-3dac4346-a5d7-4154-ba0c-27f5bd5930db
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21954289151328755872646753529568179872443416441054142401988951783979724020800 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays.21954289151328755872646753529568179872443416441054142401988951783979724020800
Directory /workspace/63.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all.39828948689211215239061259584862429378898569448568096622721617742340891837329
Short name T182
Test name
Test status
Simulation time 13992004073 ps
CPU time 519.16 seconds
Started Nov 22 03:09:16 PM PST 23
Finished Nov 22 03:17:56 PM PST 23
Peak memory 555928 kb
Host smart-be671725-c11e-40e4-8f7e-3cf2d7a44376
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39828948689211215239061259584862429378898569448568096622721617742340891837329 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.39828948689211215239061259584862429378898569448568096622721617742340891837329
Directory /workspace/63.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.53586839620952703793667727081834571300609799346822323436988744282301401361818
Short name T1576
Test name
Test status
Simulation time 13999524073 ps
CPU time 537.26 seconds
Started Nov 22 03:09:16 PM PST 23
Finished Nov 22 03:18:14 PM PST 23
Peak memory 555644 kb
Host smart-6d9106b1-6ed2-4ccb-8d84-f075148eeb46
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53586839620952703793667727081834571300609799346822323436988744282301401361818 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.53586839620952703793667727081834571300609799346822323436988744282301401361818
Directory /workspace/63.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.30523673979013165830947648011538929824489583823706658650707880892999906018790
Short name T263
Test name
Test status
Simulation time 4815189184 ps
CPU time 388.98 seconds
Started Nov 22 03:09:06 PM PST 23
Finished Nov 22 03:15:36 PM PST 23
Peak memory 557348 kb
Host smart-bcba8f1c-e60d-4779-b3fc-51c72a057746
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523673979013165830947648011538929824489583823706658650707880892999906018790 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_rand_reset.30523673979013165830947648011538929824489583823706658650707880
892999906018790
Directory /workspace/63.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.54523634749825341766477280265084662599725873113130644652340243229509454320245
Short name T639
Test name
Test status
Simulation time 4815189184 ps
CPU time 317.73 seconds
Started Nov 22 03:09:12 PM PST 23
Finished Nov 22 03:14:30 PM PST 23
Peak memory 559780 kb
Host smart-0316f699-f08a-4743-a737-60a863a0bcee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54523634749825341766477280265084662599725873113130644652340243229509454320245 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_reset_error.545236347498253417664772802650846625997258731131306446523402
43229509454320245
Directory /workspace/63.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.95286057420349252034162759086479589893956990511824384193768396412779014404829
Short name T512
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.74 seconds
Started Nov 22 03:09:20 PM PST 23
Finished Nov 22 03:10:06 PM PST 23
Peak memory 553736 kb
Host smart-047cc028-6341-40f9-933f-94dbcf866a9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95286057420349252034162759086479589893956990511824384193768396412779014404829 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.95286057420349252034162759086479589893956990511824384193768396412779014404829
Directory /workspace/63.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device.27605264153832777180471591880019544288348666042311881528496141831992772936975
Short name T782
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.4 seconds
Started Nov 22 03:09:45 PM PST 23
Finished Nov 22 03:11:32 PM PST 23
Peak memory 554776 kb
Host smart-9377cf75-413b-4b8e-989d-6da76dff1988
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27605264153832777180471591880019544288348666042311881528496141831992772936975 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device.27605264153832777180471591880019544288348666042311881528496141831992772936975
Directory /workspace/64.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.6263417091492716377944110832226301065335876404763288834230018621250079738992
Short name T464
Test name
Test status
Simulation time 115195295727 ps
CPU time 2040.66 seconds
Started Nov 22 03:09:45 PM PST 23
Finished Nov 22 03:43:47 PM PST 23
Peak memory 554768 kb
Host smart-b55e6f66-0ab7-4fa0-abf5-408e435c971d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6263417091492716377944110832226301065335876404763288834230018621250079738992 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device_slow_rsp.6263417091492716377944110832226301065335876404763288834230018621250079738992
Directory /workspace/64.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.26561822186447075198960335304171132393321550542959327993944387011332682434209
Short name T179
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.65 seconds
Started Nov 22 03:09:45 PM PST 23
Finished Nov 22 03:10:31 PM PST 23
Peak memory 553448 kb
Host smart-9d813dbc-7510-4fd9-b079-bb5f7f108028
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26561822186447075198960335304171132393321550542959327993944387011332682434209 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr.26561822186447075198960335304171132393321550542959327993944387011332682434209
Directory /workspace/64.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_random.114601996472136974687015492677757757416036587500399827989198154640150127370239
Short name T1734
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.35 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:11:05 PM PST 23
Peak memory 553620 kb
Host smart-5a45269c-6dcc-4795-b58d-06ca2fd26d71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114601996472136974687015492677757757416036587500399827989198154640150127370239 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 64.xbar_error_random.114601996472136974687015492677757757416036587500399827989198154640150127370239
Directory /workspace/64.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random.10984219297521104880424072425245362389262639736439108937728666437135828286179
Short name T428
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.99 seconds
Started Nov 22 03:09:48 PM PST 23
Finished Nov 22 03:11:10 PM PST 23
Peak memory 553776 kb
Host smart-5d81572f-dbfc-42e2-8f2f-b27d24a933b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10984219297521104880424072425245362389262639736439108937728666437135828286179 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 64.xbar_random.10984219297521104880424072425245362389262639736439108937728666437135828286179
Directory /workspace/64.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.14945842040064492156184614120050820129735016458576965619289162152483668115669
Short name T1165
Test name
Test status
Simulation time 97702135727 ps
CPU time 1147.77 seconds
Started Nov 22 03:09:45 PM PST 23
Finished Nov 22 03:28:53 PM PST 23
Peak memory 553588 kb
Host smart-44b91465-6b07-4aa4-9269-0133465e5a09
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14945842040064492156184614120050820129735016458576965619289162152483668115669 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.14945842040064492156184614120050820129735016458576965619289162152483668115669
Directory /workspace/64.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.35230314088029787905312628793256364077184033086577260060731559729421906616608
Short name T1518
Test name
Test status
Simulation time 60576345727 ps
CPU time 1126.64 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:28:33 PM PST 23
Peak memory 553700 kb
Host smart-f5d646ba-1336-4b79-b88b-a2138539d06d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35230314088029787905312628793256364077184033086577260060731559729421906616608 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.35230314088029787905312628793256364077184033086577260060731559729421906616608
Directory /workspace/64.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.71831272929774489475206835191830495096031593082972564531098919524811741573082
Short name T885
Test name
Test status
Simulation time 556965727 ps
CPU time 48.82 seconds
Started Nov 22 03:09:44 PM PST 23
Finished Nov 22 03:10:34 PM PST 23
Peak memory 553644 kb
Host smart-3c2f18aa-6838-4cde-b64c-f2419f914fba
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71831272929774489475206835191830495096031593082972564531098919524811741573082 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_delays.71831272929774489475206835191830495096031593082972564531098919524811741573082
Directory /workspace/64.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_same_source.64247556141641623662922358167316402353671710105805531819828822500921612078272
Short name T927
Test name
Test status
Simulation time 2498784073 ps
CPU time 77 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:11:03 PM PST 23
Peak memory 553828 kb
Host smart-3f68926e-52f9-4ffc-9b1f-f13025aa4bf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64247556141641623662922358167316402353671710105805531819828822500921612078272 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.64247556141641623662922358167316402353671710105805531819828822500921612078272
Directory /workspace/64.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke.109528859215098209408640157648578616231219767480694651200015495210406250923977
Short name T97
Test name
Test status
Simulation time 196985727 ps
CPU time 8.66 seconds
Started Nov 22 03:09:21 PM PST 23
Finished Nov 22 03:09:31 PM PST 23
Peak memory 552464 kb
Host smart-f729920e-ed7e-4db5-b66f-33f48db445a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109528859215098209408640157648578616231219767480694651200015495210406250923977 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 64.xbar_smoke.109528859215098209408640157648578616231219767480694651200015495210406250923977
Directory /workspace/64.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.76284062455510224360377692696039741071256865425298942885693324773339040331948
Short name T319
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.68 seconds
Started Nov 22 03:09:06 PM PST 23
Finished Nov 22 03:10:38 PM PST 23
Peak memory 552304 kb
Host smart-3a7df186-6943-4ec0-9f80-05adce5b2141
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76284062455510224360377692696039741071256865425298942885693324773339040331948 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.76284062455510224360377692696039741071256865425298942885693324773339040331948
Directory /workspace/64.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.114992152543768962666600280104020322840270020009742521091151596333094267550605
Short name T587
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.83 seconds
Started Nov 22 03:09:24 PM PST 23
Finished Nov 22 03:10:54 PM PST 23
Peak memory 552212 kb
Host smart-0701e148-c65e-48a7-a917-863866f3b059
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114992152543768962666600280104020322840270020009742521091151596333094267550605 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.114992152543768962666600280104020322840270020009742521091151596333094267550605
Directory /workspace/64.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.93837515636684714541171270791813305899825152228058534651474674628581603896784
Short name T141
Test name
Test status
Simulation time 45555727 ps
CPU time 6.35 seconds
Started Nov 22 03:09:09 PM PST 23
Finished Nov 22 03:09:16 PM PST 23
Peak memory 552276 kb
Host smart-959c5123-3842-441a-8602-6b46d6a262f0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93837515636684714541171270791813305899825152228058534651474674628581603896784 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays.93837515636684714541171270791813305899825152228058534651474674628581603896784
Directory /workspace/64.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all.13658428599965730957394392190553481524927178226980960071660770761581380988380
Short name T1796
Test name
Test status
Simulation time 13992004073 ps
CPU time 513.52 seconds
Started Nov 22 03:09:47 PM PST 23
Finished Nov 22 03:18:21 PM PST 23
Peak memory 555880 kb
Host smart-1ad136c8-c311-4031-b29b-1922efce95e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13658428599965730957394392190553481524927178226980960071660770761581380988380 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.13658428599965730957394392190553481524927178226980960071660770761581380988380
Directory /workspace/64.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.36683837485808231063388725345473146100840989528344752609236832417788397502172
Short name T344
Test name
Test status
Simulation time 13999524073 ps
CPU time 518.02 seconds
Started Nov 22 03:09:49 PM PST 23
Finished Nov 22 03:18:28 PM PST 23
Peak memory 555836 kb
Host smart-4faf1d4a-5f23-48e4-b2a8-29d237bef59e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36683837485808231063388725345473146100840989528344752609236832417788397502172 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.36683837485808231063388725345473146100840989528344752609236832417788397502172
Directory /workspace/64.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3871689791929359855114376640217613640012206190321139295796719225361467186424
Short name T719
Test name
Test status
Simulation time 4815189184 ps
CPU time 383.22 seconds
Started Nov 22 03:09:49 PM PST 23
Finished Nov 22 03:16:13 PM PST 23
Peak memory 557292 kb
Host smart-31092204-d0ce-43f0-bf0e-05dd141565b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871689791929359855114376640217613640012206190321139295796719225361467186424 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_rand_reset.387168979192935985511437664021761364001220619032113929579671922
5361467186424
Directory /workspace/64.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.21342965285329171936309641286529704898741409157871227527101141946001228287272
Short name T1109
Test name
Test status
Simulation time 4815189184 ps
CPU time 315.63 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:15:02 PM PST 23
Peak memory 559812 kb
Host smart-299e43e4-23df-4feb-8e03-2c5a08d93ea9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342965285329171936309641286529704898741409157871227527101141946001228287272 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_reset_error.213429652853291719363096412865297048987414091578712275271011
41946001228287272
Directory /workspace/64.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.21271040321623016945837814665390779385946989102689109931758217278583548802099
Short name T850
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.61 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:10:37 PM PST 23
Peak memory 553752 kb
Host smart-8901abec-8aca-48c9-92f4-4a9b8a16689e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21271040321623016945837814665390779385946989102689109931758217278583548802099 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.21271040321623016945837814665390779385946989102689109931758217278583548802099
Directory /workspace/64.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device.29643922165282733432697057632825072931297972963542945389521506661062627055057
Short name T1889
Test name
Test status
Simulation time 2590995727 ps
CPU time 111.91 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:11:39 PM PST 23
Peak memory 554764 kb
Host smart-2bf7bce1-5a3c-471e-8cd7-409edc902ffe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29643922165282733432697057632825072931297972963542945389521506661062627055057 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.29643922165282733432697057632825072931297972963542945389521506661062627055057
Directory /workspace/65.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.107146440824555528537405453660476792558750424846249016036983044466703989462975
Short name T1279
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.59 seconds
Started Nov 22 03:09:44 PM PST 23
Finished Nov 22 03:10:28 PM PST 23
Peak memory 553408 kb
Host smart-ab581c23-0fe0-4ecf-b001-0d3e337a322a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107146440824555528537405453660476792558750424846249016036983044466703989462975 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.107146440824555528537405453660476792558750424846249016036983044466703989462975
Directory /workspace/65.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_random.38651816539146742351845181975780731181173975224091349394882335894134172986939
Short name T1525
Test name
Test status
Simulation time 2231375727 ps
CPU time 79 seconds
Started Nov 22 03:09:44 PM PST 23
Finished Nov 22 03:11:03 PM PST 23
Peak memory 553560 kb
Host smart-8a4e1fea-66e5-40eb-824a-6bc226ff3d79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38651816539146742351845181975780731181173975224091349394882335894134172986939 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 65.xbar_error_random.38651816539146742351845181975780731181173975224091349394882335894134172986939
Directory /workspace/65.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random.98643242968577333590444609833501793107668021253155491301538005193952828027773
Short name T1615
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.56 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:11:04 PM PST 23
Peak memory 553752 kb
Host smart-8e9f585f-0b4e-4ede-b984-2b2069187b93
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98643242968577333590444609833501793107668021253155491301538005193952828027773 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 65.xbar_random.98643242968577333590444609833501793107668021253155491301538005193952828027773
Directory /workspace/65.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.108751758477151193290022390798700142986704716283031536903223862925379639831618
Short name T1830
Test name
Test status
Simulation time 97702135727 ps
CPU time 1156.01 seconds
Started Nov 22 03:09:47 PM PST 23
Finished Nov 22 03:29:03 PM PST 23
Peak memory 553680 kb
Host smart-8bdc2981-b00b-4152-b169-615ae0f40a83
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108751758477151193290022390798700142986704716283031536903223862925379639831618 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.108751758477151193290022390798700142986704716283031536903223862925379639831618
Directory /workspace/65.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.18870690772444107332408393150489942008361716424944334637377901641399499093255
Short name T101
Test name
Test status
Simulation time 60576345727 ps
CPU time 1098.66 seconds
Started Nov 22 03:09:47 PM PST 23
Finished Nov 22 03:28:06 PM PST 23
Peak memory 553700 kb
Host smart-308a6c1f-1377-4fd4-99a3-bceb165412c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18870690772444107332408393150489942008361716424944334637377901641399499093255 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.18870690772444107332408393150489942008361716424944334637377901641399499093255
Directory /workspace/65.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.82684594810776390219589612963092071065152930326937478066081742907880921373515
Short name T547
Test name
Test status
Simulation time 556965727 ps
CPU time 48.4 seconds
Started Nov 22 03:09:44 PM PST 23
Finished Nov 22 03:10:33 PM PST 23
Peak memory 553616 kb
Host smart-536a8055-a0b0-45f8-a206-58bdc04b7d1a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82684594810776390219589612963092071065152930326937478066081742907880921373515 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delays.82684594810776390219589612963092071065152930326937478066081742907880921373515
Directory /workspace/65.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_same_source.55550974111182255217418263693688116557418335632849757223554018747270374138218
Short name T325
Test name
Test status
Simulation time 2498784073 ps
CPU time 78.92 seconds
Started Nov 22 03:09:47 PM PST 23
Finished Nov 22 03:11:06 PM PST 23
Peak memory 553748 kb
Host smart-8cada386-ea51-4a2c-b7f9-0fb1009416e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55550974111182255217418263693688116557418335632849757223554018747270374138218 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.55550974111182255217418263693688116557418335632849757223554018747270374138218
Directory /workspace/65.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke.58364461819767683264575738215034764040336129295115593921007198929680712727476
Short name T1306
Test name
Test status
Simulation time 196985727 ps
CPU time 8.79 seconds
Started Nov 22 03:09:48 PM PST 23
Finished Nov 22 03:09:57 PM PST 23
Peak memory 552424 kb
Host smart-1ef8c404-ce12-41e9-a3c8-3d304348e0f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58364461819767683264575738215034764040336129295115593921007198929680712727476 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 65.xbar_smoke.58364461819767683264575738215034764040336129295115593921007198929680712727476
Directory /workspace/65.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.8849788182225987604365958810641095296638598747288305115098020987174684934199
Short name T1197
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.43 seconds
Started Nov 22 03:09:44 PM PST 23
Finished Nov 22 03:11:17 PM PST 23
Peak memory 552332 kb
Host smart-406f20b0-dc8f-4198-bbbc-31524166a2f0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8849788182225987604365958810641095296638598747288305115098020987174684934199 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.8849788182225987604365958810641095296638598747288305115098020987174684934199
Directory /workspace/65.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.28582848370360256751531578141907881718509507407957349721906152615776323788378
Short name T231
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.69 seconds
Started Nov 22 03:09:46 PM PST 23
Finished Nov 22 03:11:13 PM PST 23
Peak memory 552396 kb
Host smart-bfb42d0a-605b-402f-828d-581bd21f7373
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28582848370360256751531578141907881718509507407957349721906152615776323788378 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.28582848370360256751531578141907881718509507407957349721906152615776323788378
Directory /workspace/65.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.23814373721476280152275382406634596604930198110260444775649930515985956325024
Short name T1658
Test name
Test status
Simulation time 45555727 ps
CPU time 6.06 seconds
Started Nov 22 03:09:43 PM PST 23
Finished Nov 22 03:09:49 PM PST 23
Peak memory 552360 kb
Host smart-816b4f08-6e69-450d-863c-9fa2c7f12a1f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23814373721476280152275382406634596604930198110260444775649930515985956325024 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays.23814373721476280152275382406634596604930198110260444775649930515985956325024
Directory /workspace/65.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all.59950827680222288851643148418590009481989042381227337709235221789200348419014
Short name T947
Test name
Test status
Simulation time 13992004073 ps
CPU time 482.83 seconds
Started Nov 22 03:09:58 PM PST 23
Finished Nov 22 03:18:01 PM PST 23
Peak memory 555872 kb
Host smart-abdf5957-9088-4048-b000-dc7db999b4c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59950827680222288851643148418590009481989042381227337709235221789200348419014 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.59950827680222288851643148418590009481989042381227337709235221789200348419014
Directory /workspace/65.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.75541786785702975226791196153274993054346858263499519679484999074475245481640
Short name T88
Test name
Test status
Simulation time 13999524073 ps
CPU time 517.8 seconds
Started Nov 22 03:09:54 PM PST 23
Finished Nov 22 03:18:33 PM PST 23
Peak memory 555704 kb
Host smart-6cd2fd1a-630d-4a43-bf92-27e327868e39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75541786785702975226791196153274993054346858263499519679484999074475245481640 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.75541786785702975226791196153274993054346858263499519679484999074475245481640
Directory /workspace/65.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.29869818127130452083984587582237736175993897447156464611902739930200363675745
Short name T1205
Test name
Test status
Simulation time 4815189184 ps
CPU time 362.54 seconds
Started Nov 22 03:09:49 PM PST 23
Finished Nov 22 03:15:52 PM PST 23
Peak memory 557224 kb
Host smart-b70cb015-b54d-4938-ba21-42bdfa630746
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29869818127130452083984587582237736175993897447156464611902739930200363675745 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_rand_reset.29869818127130452083984587582237736175993897447156464611902739
930200363675745
Directory /workspace/65.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.15678550212240873451795401704185631748557794095718781717075901055632961258865
Short name T1454
Test name
Test status
Simulation time 4815189184 ps
CPU time 316.67 seconds
Started Nov 22 03:09:50 PM PST 23
Finished Nov 22 03:15:08 PM PST 23
Peak memory 559720 kb
Host smart-f8e2fdd6-6021-46b8-a486-3e6d2d566d63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678550212240873451795401704185631748557794095718781717075901055632961258865 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_reset_error.156785502122408734517954017041856317485577940957187817170759
01055632961258865
Directory /workspace/65.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.87980177913419397971215260319579130670360436753480768980737688499791013830443
Short name T1400
Test name
Test status
Simulation time 1176995727 ps
CPU time 53.59 seconds
Started Nov 22 03:09:48 PM PST 23
Finished Nov 22 03:10:42 PM PST 23
Peak memory 553696 kb
Host smart-2a6894ab-007f-43f8-bacf-4defef36cf76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87980177913419397971215260319579130670360436753480768980737688499791013830443 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.87980177913419397971215260319579130670360436753480768980737688499791013830443
Directory /workspace/65.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device.87033082433375693246143091136069724213900089107907250668269626122310103419280
Short name T167
Test name
Test status
Simulation time 2590995727 ps
CPU time 120.58 seconds
Started Nov 22 03:09:58 PM PST 23
Finished Nov 22 03:11:59 PM PST 23
Peak memory 554904 kb
Host smart-da5c97ac-7bef-43c6-ac21-31b713c2837e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87033082433375693246143091136069724213900089107907250668269626122310103419280 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.87033082433375693246143091136069724213900089107907250668269626122310103419280
Directory /workspace/66.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.108392286245251968258669976919609719515486761520184366969214794626756953627468
Short name T415
Test name
Test status
Simulation time 115195295727 ps
CPU time 2110.21 seconds
Started Nov 22 03:09:49 PM PST 23
Finished Nov 22 03:45:00 PM PST 23
Peak memory 554748 kb
Host smart-d65e0ec3-af85-4476-ba6b-b628d6515460
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108392286245251968258669976919609719515486761520184366969214794626756953627468 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device_slow_rsp.108392286245251968258669976919609719515486761520184366969214794626756953627468
Directory /workspace/66.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.100867509457033938752330209210135282176763021413169069137475218361463106899290
Short name T1257
Test name
Test status
Simulation time 1171215727 ps
CPU time 49.92 seconds
Started Nov 22 03:09:51 PM PST 23
Finished Nov 22 03:10:41 PM PST 23
Peak memory 553484 kb
Host smart-0a9f2619-1840-4544-a4a7-0a8432fbbfd6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100867509457033938752330209210135282176763021413169069137475218361463106899290 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr.100867509457033938752330209210135282176763021413169069137475218361463106899290
Directory /workspace/66.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_random.48969866232914687562251886437766132525389494174207301268044322074669632343057
Short name T1323
Test name
Test status
Simulation time 2231375727 ps
CPU time 69.39 seconds
Started Nov 22 03:09:58 PM PST 23
Finished Nov 22 03:11:08 PM PST 23
Peak memory 553500 kb
Host smart-ffaaf1fb-ace5-40a7-8022-3e5c552a09ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48969866232914687562251886437766132525389494174207301268044322074669632343057 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 66.xbar_error_random.48969866232914687562251886437766132525389494174207301268044322074669632343057
Directory /workspace/66.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random.53209533512093180562790546910639961893243746054935400743181288317653680871178
Short name T61
Test name
Test status
Simulation time 2231375727 ps
CPU time 89.18 seconds
Started Nov 22 03:09:50 PM PST 23
Finished Nov 22 03:11:19 PM PST 23
Peak memory 553768 kb
Host smart-ad92beb8-6980-4712-9a7d-0c6b16cbbd4c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53209533512093180562790546910639961893243746054935400743181288317653680871178 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 66.xbar_random.53209533512093180562790546910639961893243746054935400743181288317653680871178
Directory /workspace/66.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.113398602220949987787120722063199238003572026652739949066620101842896358085920
Short name T999
Test name
Test status
Simulation time 97702135727 ps
CPU time 1175.24 seconds
Started Nov 22 03:09:50 PM PST 23
Finished Nov 22 03:29:26 PM PST 23
Peak memory 553592 kb
Host smart-eaeb3867-a46e-482b-8599-5ac159c61d30
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113398602220949987787120722063199238003572026652739949066620101842896358085920 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.113398602220949987787120722063199238003572026652739949066620101842896358085920
Directory /workspace/66.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.77041613479978175737195465502239847624681045813451367058986583176811407695962
Short name T1094
Test name
Test status
Simulation time 60576345727 ps
CPU time 1111.07 seconds
Started Nov 22 03:09:58 PM PST 23
Finished Nov 22 03:28:29 PM PST 23
Peak memory 553812 kb
Host smart-0793bced-6d05-4383-91fb-8a2fa43a44be
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77041613479978175737195465502239847624681045813451367058986583176811407695962 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.77041613479978175737195465502239847624681045813451367058986583176811407695962
Directory /workspace/66.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.20575421612573683834880376478879362161032511102113700784881862811929794900993
Short name T777
Test name
Test status
Simulation time 556965727 ps
CPU time 49.79 seconds
Started Nov 22 03:09:50 PM PST 23
Finished Nov 22 03:10:41 PM PST 23
Peak memory 553672 kb
Host smart-f07ead55-9197-4fc1-8024-cab088c36907
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20575421612573683834880376478879362161032511102113700784881862811929794900993 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_delays.20575421612573683834880376478879362161032511102113700784881862811929794900993
Directory /workspace/66.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_same_source.57725308090490488090569864263133116264480679286735190645865281983350501160953
Short name T921
Test name
Test status
Simulation time 2498784073 ps
CPU time 74.9 seconds
Started Nov 22 03:09:51 PM PST 23
Finished Nov 22 03:11:07 PM PST 23
Peak memory 553804 kb
Host smart-46720cdb-eb81-47c2-b526-ee0a89fe8cd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57725308090490488090569864263133116264480679286735190645865281983350501160953 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.57725308090490488090569864263133116264480679286735190645865281983350501160953
Directory /workspace/66.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke.26184883135162748255019668263364093801229265306311132415092561610156552027874
Short name T194
Test name
Test status
Simulation time 196985727 ps
CPU time 9 seconds
Started Nov 22 03:09:53 PM PST 23
Finished Nov 22 03:10:02 PM PST 23
Peak memory 552288 kb
Host smart-e3404b26-06c7-402b-89c0-08a14cb3b8c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26184883135162748255019668263364093801229265306311132415092561610156552027874 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 66.xbar_smoke.26184883135162748255019668263364093801229265306311132415092561610156552027874
Directory /workspace/66.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.71376011048050208654233315613116135138163473303616393079960098625294779322911
Short name T679
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.27 seconds
Started Nov 22 03:09:49 PM PST 23
Finished Nov 22 03:11:20 PM PST 23
Peak memory 552476 kb
Host smart-53abf43a-26d0-46cd-98f9-841a16594b3b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71376011048050208654233315613116135138163473303616393079960098625294779322911 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.71376011048050208654233315613116135138163473303616393079960098625294779322911
Directory /workspace/66.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.18007993260996506025320720485568879790323287355474167652515620552863086738311
Short name T183
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.68 seconds
Started Nov 22 03:09:52 PM PST 23
Finished Nov 22 03:11:22 PM PST 23
Peak memory 552480 kb
Host smart-650e7917-85fb-4260-a249-5174d158f0ca
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18007993260996506025320720485568879790323287355474167652515620552863086738311 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.18007993260996506025320720485568879790323287355474167652515620552863086738311
Directory /workspace/66.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.21273094662827024706004277434898300002977779387480389624009435409028251986028
Short name T217
Test name
Test status
Simulation time 45555727 ps
CPU time 6.15 seconds
Started Nov 22 03:09:53 PM PST 23
Finished Nov 22 03:10:00 PM PST 23
Peak memory 552176 kb
Host smart-c0e918f1-7da1-4d58-bf06-6551c710d004
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21273094662827024706004277434898300002977779387480389624009435409028251986028 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays.21273094662827024706004277434898300002977779387480389624009435409028251986028
Directory /workspace/66.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all.54753011709754332493301691578124020734447216589735466981808111876846398855004
Short name T1638
Test name
Test status
Simulation time 13992004073 ps
CPU time 491.27 seconds
Started Nov 22 03:09:55 PM PST 23
Finished Nov 22 03:18:07 PM PST 23
Peak memory 555880 kb
Host smart-9f0b40c5-b1ed-4d08-81d4-a86386053d72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54753011709754332493301691578124020734447216589735466981808111876846398855004 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.54753011709754332493301691578124020734447216589735466981808111876846398855004
Directory /workspace/66.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.39518753045334737733536415170909771270641820182111818972536319537505742889173
Short name T583
Test name
Test status
Simulation time 13999524073 ps
CPU time 495.24 seconds
Started Nov 22 03:09:51 PM PST 23
Finished Nov 22 03:18:07 PM PST 23
Peak memory 555740 kb
Host smart-86ca22d2-99b7-4741-980e-076f37e34065
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39518753045334737733536415170909771270641820182111818972536319537505742889173 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.39518753045334737733536415170909771270641820182111818972536319537505742889173
Directory /workspace/66.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.78654269532187548314944859342210444243632105182697215024589587713385048719430
Short name T1800
Test name
Test status
Simulation time 4815189184 ps
CPU time 392.28 seconds
Started Nov 22 03:09:53 PM PST 23
Finished Nov 22 03:16:26 PM PST 23
Peak memory 557168 kb
Host smart-b357ad4d-d1ef-4118-8527-c6ce569936ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78654269532187548314944859342210444243632105182697215024589587713385048719430 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_rand_reset.78654269532187548314944859342210444243632105182697215024589587
713385048719430
Directory /workspace/66.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.5570442911789414266511420259808047061783710591450180013381835434698000279822
Short name T1716
Test name
Test status
Simulation time 4815189184 ps
CPU time 315.91 seconds
Started Nov 22 03:09:51 PM PST 23
Finished Nov 22 03:15:07 PM PST 23
Peak memory 559768 kb
Host smart-e3d33534-ca7f-4c88-9933-21e813aa5f7e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5570442911789414266511420259808047061783710591450180013381835434698000279822 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_reset_error.5570442911789414266511420259808047061783710591450180013381835
434698000279822
Directory /workspace/66.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.59223717962043992520261417154801301058301592889373168234132037217147432327492
Short name T515
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.95 seconds
Started Nov 22 03:09:53 PM PST 23
Finished Nov 22 03:10:41 PM PST 23
Peak memory 553532 kb
Host smart-a4a5bdbf-5c80-49d1-abfa-82f1ccf7e609
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59223717962043992520261417154801301058301592889373168234132037217147432327492 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.59223717962043992520261417154801301058301592889373168234132037217147432327492
Directory /workspace/66.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device.16915183057907333908802201336294854418287254291079346409290381423348677868495
Short name T1491
Test name
Test status
Simulation time 2590995727 ps
CPU time 110.85 seconds
Started Nov 22 03:10:02 PM PST 23
Finished Nov 22 03:11:54 PM PST 23
Peak memory 554792 kb
Host smart-572e2354-5ddd-4a3a-96eb-6075202397a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915183057907333908802201336294854418287254291079346409290381423348677868495 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device.16915183057907333908802201336294854418287254291079346409290381423348677868495
Directory /workspace/67.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.105767471607045948729108417674965273649379385302768655065349802584606860164227
Short name T1612
Test name
Test status
Simulation time 115195295727 ps
CPU time 2108.88 seconds
Started Nov 22 03:09:57 PM PST 23
Finished Nov 22 03:45:07 PM PST 23
Peak memory 554796 kb
Host smart-814a8c6e-9ebd-4d31-900b-9a14ca70c4b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105767471607045948729108417674965273649379385302768655065349802584606860164227 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device_slow_rsp.105767471607045948729108417674965273649379385302768655065349802584606860164227
Directory /workspace/67.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.5417678241552102139567416568029149634574148615835811690795814691236025350551
Short name T236
Test name
Test status
Simulation time 1171215727 ps
CPU time 48.07 seconds
Started Nov 22 03:09:57 PM PST 23
Finished Nov 22 03:10:46 PM PST 23
Peak memory 553544 kb
Host smart-74f629ba-76d5-4fbc-8fa7-d78699956d73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5417678241552102139567416568029149634574148615835811690795814691236025350551 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr.5417678241552102139567416568029149634574148615835811690795814691236025350551
Directory /workspace/67.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_random.54981400494850669014912806221781114167290308451542504757931908217472441317515
Short name T1048
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.24 seconds
Started Nov 22 03:09:57 PM PST 23
Finished Nov 22 03:11:14 PM PST 23
Peak memory 553524 kb
Host smart-d8af60ec-3f5b-4c29-bf81-6725f8e8aace
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54981400494850669014912806221781114167290308451542504757931908217472441317515 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 67.xbar_error_random.54981400494850669014912806221781114167290308451542504757931908217472441317515
Directory /workspace/67.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random.76570200018261097276741109806613529974377920317897390206865657260103586946231
Short name T1231
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.2 seconds
Started Nov 22 03:09:57 PM PST 23
Finished Nov 22 03:11:20 PM PST 23
Peak memory 553844 kb
Host smart-d197ffdc-b6e0-4a0e-8ecc-41d11d4a61ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76570200018261097276741109806613529974377920317897390206865657260103586946231 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 67.xbar_random.76570200018261097276741109806613529974377920317897390206865657260103586946231
Directory /workspace/67.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.56726062825365132494816805397300510973717860161333718639543307125695627427634
Short name T1218
Test name
Test status
Simulation time 97702135727 ps
CPU time 1156.44 seconds
Started Nov 22 03:10:04 PM PST 23
Finished Nov 22 03:29:21 PM PST 23
Peak memory 553672 kb
Host smart-3e925253-d9ef-4bcc-a8fe-f6106bf990b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56726062825365132494816805397300510973717860161333718639543307125695627427634 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.56726062825365132494816805397300510973717860161333718639543307125695627427634
Directory /workspace/67.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.78519074472925907835217379683546429271194241903606171188632415719450473238723
Short name T1236
Test name
Test status
Simulation time 60576345727 ps
CPU time 1149.13 seconds
Started Nov 22 03:09:56 PM PST 23
Finished Nov 22 03:29:06 PM PST 23
Peak memory 553652 kb
Host smart-cb459a4d-a4e8-4aca-9d8a-a1917e6e8363
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78519074472925907835217379683546429271194241903606171188632415719450473238723 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.78519074472925907835217379683546429271194241903606171188632415719450473238723
Directory /workspace/67.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.72176831282002239686814756100334188185996611619626527475727469517324977388859
Short name T1837
Test name
Test status
Simulation time 556965727 ps
CPU time 46.55 seconds
Started Nov 22 03:09:58 PM PST 23
Finished Nov 22 03:10:45 PM PST 23
Peak memory 553632 kb
Host smart-35da4887-9734-4ab0-89e8-d92ecd4f8247
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72176831282002239686814756100334188185996611619626527475727469517324977388859 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delays.72176831282002239686814756100334188185996611619626527475727469517324977388859
Directory /workspace/67.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_same_source.81029602438191053893257606643694618910306865344560005156856656689300383812463
Short name T1557
Test name
Test status
Simulation time 2498784073 ps
CPU time 78.07 seconds
Started Nov 22 03:10:00 PM PST 23
Finished Nov 22 03:11:19 PM PST 23
Peak memory 553744 kb
Host smart-62d803e8-57ec-43d2-b908-db4efb7dc7f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81029602438191053893257606643694618910306865344560005156856656689300383812463 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.81029602438191053893257606643694618910306865344560005156856656689300383812463
Directory /workspace/67.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke.2261583384032374779945480613701409401162804107558747251165259007850496153128
Short name T247
Test name
Test status
Simulation time 196985727 ps
CPU time 9.08 seconds
Started Nov 22 03:09:52 PM PST 23
Finished Nov 22 03:10:01 PM PST 23
Peak memory 552380 kb
Host smart-e9cac997-20ef-4f22-84e1-269ecfaf3bc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261583384032374779945480613701409401162804107558747251165259007850496153128 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 67.xbar_smoke.2261583384032374779945480613701409401162804107558747251165259007850496153128
Directory /workspace/67.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.105908136690461634282677688325167952386129200301174801612505757137825962147061
Short name T1841
Test name
Test status
Simulation time 7758585727 ps
CPU time 84.63 seconds
Started Nov 22 03:09:52 PM PST 23
Finished Nov 22 03:11:17 PM PST 23
Peak memory 552364 kb
Host smart-277e3f3f-2100-47b5-bfc0-a83ab3f938cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105908136690461634282677688325167952386129200301174801612505757137825962147061 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.105908136690461634282677688325167952386129200301174801612505757137825962147061
Directory /workspace/67.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.74222208401836651054360102767158168598913609237031725838037967181567601146548
Short name T84
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.59 seconds
Started Nov 22 03:09:52 PM PST 23
Finished Nov 22 03:11:13 PM PST 23
Peak memory 552380 kb
Host smart-bc4c90a8-157f-48b7-b56e-d3051db350c4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74222208401836651054360102767158168598913609237031725838037967181567601146548 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.74222208401836651054360102767158168598913609237031725838037967181567601146548
Directory /workspace/67.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.91880193523420848520287932539950567877795409911041128266403214497090097346299
Short name T1248
Test name
Test status
Simulation time 45555727 ps
CPU time 6.04 seconds
Started Nov 22 03:09:51 PM PST 23
Finished Nov 22 03:09:57 PM PST 23
Peak memory 552372 kb
Host smart-4033ad03-294c-4584-9a97-b8cabe8053ab
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91880193523420848520287932539950567877795409911041128266403214497090097346299 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays.91880193523420848520287932539950567877795409911041128266403214497090097346299
Directory /workspace/67.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all.44531493015703659996241547377446183293577419357268756928075473142115219849698
Short name T1230
Test name
Test status
Simulation time 13992004073 ps
CPU time 534.84 seconds
Started Nov 22 03:09:57 PM PST 23
Finished Nov 22 03:18:53 PM PST 23
Peak memory 555904 kb
Host smart-6e97c1d5-4754-45c3-b551-72a49b893eb5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44531493015703659996241547377446183293577419357268756928075473142115219849698 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.44531493015703659996241547377446183293577419357268756928075473142115219849698
Directory /workspace/67.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.96930465943836011506881850214917337342767104698278029841743271415145017079535
Short name T408
Test name
Test status
Simulation time 13999524073 ps
CPU time 530.97 seconds
Started Nov 22 03:10:03 PM PST 23
Finished Nov 22 03:18:54 PM PST 23
Peak memory 555728 kb
Host smart-dd94e505-976a-417c-89e8-c0477e95d33f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96930465943836011506881850214917337342767104698278029841743271415145017079535 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.96930465943836011506881850214917337342767104698278029841743271415145017079535
Directory /workspace/67.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.42137450184861027092044880969817056916586713203798408125769052651293892614929
Short name T146
Test name
Test status
Simulation time 4815189184 ps
CPU time 367.61 seconds
Started Nov 22 03:09:57 PM PST 23
Finished Nov 22 03:16:06 PM PST 23
Peak memory 557352 kb
Host smart-5dca1af2-1bf9-4cae-b966-bb4242c929db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137450184861027092044880969817056916586713203798408125769052651293892614929 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_rand_reset.42137450184861027092044880969817056916586713203798408125769052
651293892614929
Directory /workspace/67.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.108542584318997089676422699630118096644648034906047638057850441136391435531231
Short name T419
Test name
Test status
Simulation time 4815189184 ps
CPU time 310.49 seconds
Started Nov 22 03:10:04 PM PST 23
Finished Nov 22 03:15:15 PM PST 23
Peak memory 559720 kb
Host smart-13152a30-47a6-487c-a5c8-118e06136541
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108542584318997089676422699630118096644648034906047638057850441136391435531231 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_reset_error.10854258431899708967642269963011809664464803490604763805785
0441136391435531231
Directory /workspace/67.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.78152304564123196494031131022897446879900732170233198827971780366624466448678
Short name T1413
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.41 seconds
Started Nov 22 03:10:02 PM PST 23
Finished Nov 22 03:10:51 PM PST 23
Peak memory 553720 kb
Host smart-fddcf57f-8d34-431c-8a8c-7cccec8970fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78152304564123196494031131022897446879900732170233198827971780366624466448678 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.78152304564123196494031131022897446879900732170233198827971780366624466448678
Directory /workspace/67.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device.55983519415529162111118125976243778502998336130031528430689840246270449928444
Short name T1034
Test name
Test status
Simulation time 2590995727 ps
CPU time 110.86 seconds
Started Nov 22 03:09:58 PM PST 23
Finished Nov 22 03:11:49 PM PST 23
Peak memory 554780 kb
Host smart-9b2f544a-a18e-4e22-a2f2-1de97c615ae1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55983519415529162111118125976243778502998336130031528430689840246270449928444 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.55983519415529162111118125976243778502998336130031528430689840246270449928444
Directory /workspace/68.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.94355499724589511823225301790699738384458703363428895677114023411817639626476
Short name T1390
Test name
Test status
Simulation time 115195295727 ps
CPU time 2093.56 seconds
Started Nov 22 03:10:12 PM PST 23
Finished Nov 22 03:45:06 PM PST 23
Peak memory 554764 kb
Host smart-55075b4b-bcdf-4310-b4b4-309316335e3b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94355499724589511823225301790699738384458703363428895677114023411817639626476 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device_slow_rsp.94355499724589511823225301790699738384458703363428895677114023411817639626476
Directory /workspace/68.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.51169985417308052129942116143141941871593887217407649089640593044616353503208
Short name T1135
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.43 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:10:54 PM PST 23
Peak memory 553452 kb
Host smart-3a33acde-bdab-4130-bafd-3f511fe07aed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51169985417308052129942116143141941871593887217407649089640593044616353503208 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr.51169985417308052129942116143141941871593887217407649089640593044616353503208
Directory /workspace/68.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_random.103678793944511763489347374851031307454280398521412231487338536366841477974051
Short name T1393
Test name
Test status
Simulation time 2231375727 ps
CPU time 70.31 seconds
Started Nov 22 03:10:08 PM PST 23
Finished Nov 22 03:11:19 PM PST 23
Peak memory 553540 kb
Host smart-c00d2bca-68f2-42fd-95b6-12e027b32d1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103678793944511763489347374851031307454280398521412231487338536366841477974051 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 68.xbar_error_random.103678793944511763489347374851031307454280398521412231487338536366841477974051
Directory /workspace/68.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random.82896230502260120281622432938669698284061048604744074036518105971352903261231
Short name T722
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.45 seconds
Started Nov 22 03:10:02 PM PST 23
Finished Nov 22 03:11:21 PM PST 23
Peak memory 553756 kb
Host smart-b376e9fa-4269-4edd-bd58-55fb9fc7041a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82896230502260120281622432938669698284061048604744074036518105971352903261231 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 68.xbar_random.82896230502260120281622432938669698284061048604744074036518105971352903261231
Directory /workspace/68.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.33228765820024248391064139000022885414999816836368959174633118732030167498207
Short name T673
Test name
Test status
Simulation time 97702135727 ps
CPU time 1162.24 seconds
Started Nov 22 03:10:01 PM PST 23
Finished Nov 22 03:29:24 PM PST 23
Peak memory 553668 kb
Host smart-482a07e9-e363-4a6c-8bbc-cc7f59a8e10a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228765820024248391064139000022885414999816836368959174633118732030167498207 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.33228765820024248391064139000022885414999816836368959174633118732030167498207
Directory /workspace/68.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.57900580856292248869401373124251671462521790379415867348568004920881544655706
Short name T64
Test name
Test status
Simulation time 60576345727 ps
CPU time 1129.58 seconds
Started Nov 22 03:09:55 PM PST 23
Finished Nov 22 03:28:46 PM PST 23
Peak memory 553532 kb
Host smart-6b850f23-862d-4b7f-a72f-2f497b68d30b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57900580856292248869401373124251671462521790379415867348568004920881544655706 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.57900580856292248869401373124251671462521790379415867348568004920881544655706
Directory /workspace/68.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.87874155231865518212004179580835837013385783587064561849496257939239615357422
Short name T279
Test name
Test status
Simulation time 556965727 ps
CPU time 47.42 seconds
Started Nov 22 03:09:58 PM PST 23
Finished Nov 22 03:10:46 PM PST 23
Peak memory 553708 kb
Host smart-5def7886-740a-4c89-a0fb-14985857e2f0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87874155231865518212004179580835837013385783587064561849496257939239615357422 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_delays.87874155231865518212004179580835837013385783587064561849496257939239615357422
Directory /workspace/68.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_same_source.84869954483057186247550497160097174995381470244030809405798941236969015930185
Short name T1320
Test name
Test status
Simulation time 2498784073 ps
CPU time 80.32 seconds
Started Nov 22 03:10:10 PM PST 23
Finished Nov 22 03:11:31 PM PST 23
Peak memory 553732 kb
Host smart-eb7e071b-418a-4c3a-bc91-a1ecc4e8bf58
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84869954483057186247550497160097174995381470244030809405798941236969015930185 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.84869954483057186247550497160097174995381470244030809405798941236969015930185
Directory /workspace/68.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke.60838466457901741777955281896408593001662056623436831834852849197783249991307
Short name T349
Test name
Test status
Simulation time 196985727 ps
CPU time 9.31 seconds
Started Nov 22 03:09:59 PM PST 23
Finished Nov 22 03:10:09 PM PST 23
Peak memory 552380 kb
Host smart-2eb2453e-e808-4113-82f1-6678f4b81acf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60838466457901741777955281896408593001662056623436831834852849197783249991307 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 68.xbar_smoke.60838466457901741777955281896408593001662056623436831834852849197783249991307
Directory /workspace/68.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.102864668655247435085704830917259173182191567564688075781777213810647638951422
Short name T966
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.16 seconds
Started Nov 22 03:10:02 PM PST 23
Finished Nov 22 03:11:34 PM PST 23
Peak memory 552380 kb
Host smart-745759ae-bd82-4896-b385-5deffa34f42a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102864668655247435085704830917259173182191567564688075781777213810647638951422 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.102864668655247435085704830917259173182191567564688075781777213810647638951422
Directory /workspace/68.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.114991798383974813809736007852013613408229987066019904211811453498855975120534
Short name T933
Test name
Test status
Simulation time 4856075727 ps
CPU time 91.65 seconds
Started Nov 22 03:09:57 PM PST 23
Finished Nov 22 03:11:29 PM PST 23
Peak memory 552380 kb
Host smart-b73249b1-ea04-4901-a0cb-63457ed156b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114991798383974813809736007852013613408229987066019904211811453498855975120534 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.114991798383974813809736007852013613408229987066019904211811453498855975120534
Directory /workspace/68.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.61018842622931186592085024594625941078155005895020337923050945349244563326343
Short name T1173
Test name
Test status
Simulation time 45555727 ps
CPU time 5.99 seconds
Started Nov 22 03:10:03 PM PST 23
Finished Nov 22 03:10:09 PM PST 23
Peak memory 552364 kb
Host smart-429932d2-4318-49cd-a913-95dd4677edc6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61018842622931186592085024594625941078155005895020337923050945349244563326343 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.61018842622931186592085024594625941078155005895020337923050945349244563326343
Directory /workspace/68.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all.44758046263909229469919438641139021246677305601659716253144232775701001069844
Short name T574
Test name
Test status
Simulation time 13992004073 ps
CPU time 535.23 seconds
Started Nov 22 03:10:13 PM PST 23
Finished Nov 22 03:19:09 PM PST 23
Peak memory 555880 kb
Host smart-06336851-5444-454e-8e03-e3ee60435598
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44758046263909229469919438641139021246677305601659716253144232775701001069844 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.44758046263909229469919438641139021246677305601659716253144232775701001069844
Directory /workspace/68.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.94227735659431889811985542417025682295070498908289372604795593058002352054538
Short name T1418
Test name
Test status
Simulation time 13999524073 ps
CPU time 525.99 seconds
Started Nov 22 03:10:13 PM PST 23
Finished Nov 22 03:19:00 PM PST 23
Peak memory 555716 kb
Host smart-af5377c9-4dd5-46d7-b95e-c37f85f662cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94227735659431889811985542417025682295070498908289372604795593058002352054538 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.94227735659431889811985542417025682295070498908289372604795593058002352054538
Directory /workspace/68.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.84052551398871867341936007404518775849759287099918851651414132665254662572668
Short name T681
Test name
Test status
Simulation time 4815189184 ps
CPU time 383.85 seconds
Started Nov 22 03:10:07 PM PST 23
Finished Nov 22 03:16:32 PM PST 23
Peak memory 557184 kb
Host smart-3066078b-0b60-401f-8191-c18f9b488a04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84052551398871867341936007404518775849759287099918851651414132665254662572668 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_rand_reset.84052551398871867341936007404518775849759287099918851651414132
665254662572668
Directory /workspace/68.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.48346782610986300186297970263634585412410029821985426379344465997589758502416
Short name T592
Test name
Test status
Simulation time 4815189184 ps
CPU time 324.23 seconds
Started Nov 22 03:10:13 PM PST 23
Finished Nov 22 03:15:38 PM PST 23
Peak memory 559680 kb
Host smart-30514710-939e-40da-937e-93d603d8f05f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48346782610986300186297970263634585412410029821985426379344465997589758502416 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_reset_error.483467826109863001862979702636345854124100298219854263793444
65997589758502416
Directory /workspace/68.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.35412533961475070771549682106733173172777155314097309848319769901328331508820
Short name T1725
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.8 seconds
Started Nov 22 03:10:12 PM PST 23
Finished Nov 22 03:11:02 PM PST 23
Peak memory 553712 kb
Host smart-9d0f135b-5ed2-45cb-91e9-c7a3087b18b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412533961475070771549682106733173172777155314097309848319769901328331508820 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.35412533961475070771549682106733173172777155314097309848319769901328331508820
Directory /workspace/68.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device.4222474282802112293990413578648216142384426269427458148605731410194298465034
Short name T922
Test name
Test status
Simulation time 2590995727 ps
CPU time 104.36 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:11:54 PM PST 23
Peak memory 554792 kb
Host smart-3b1b47aa-b694-440e-9e9b-c22f738868fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222474282802112293990413578648216142384426269427458148605731410194298465034 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.4222474282802112293990413578648216142384426269427458148605731410194298465034
Directory /workspace/69.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.45837931866264911546327319321571922754404254660856154361026910171067325187858
Short name T926
Test name
Test status
Simulation time 115195295727 ps
CPU time 2080.35 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:44:50 PM PST 23
Peak memory 554820 kb
Host smart-073739a6-f9ef-4497-a82e-d76c4fc925dd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45837931866264911546327319321571922754404254660856154361026910171067325187858 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device_slow_rsp.45837931866264911546327319321571922754404254660856154361026910171067325187858
Directory /workspace/69.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.20191300693352334509911345694153721076858240210418824247991674578241643823894
Short name T352
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.13 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:10:53 PM PST 23
Peak memory 553488 kb
Host smart-542b3232-912b-42f5-97b8-9673280c73d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20191300693352334509911345694153721076858240210418824247991674578241643823894 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr.20191300693352334509911345694153721076858240210418824247991674578241643823894
Directory /workspace/69.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_random.6191156753662228696601804498760680174344548841132091817329800640563961179424
Short name T1562
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.87 seconds
Started Nov 22 03:10:10 PM PST 23
Finished Nov 22 03:11:25 PM PST 23
Peak memory 553616 kb
Host smart-aa8bb73c-5ffe-4045-8f17-81d23b3cf530
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6191156753662228696601804498760680174344548841132091817329800640563961179424 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 69.xbar_error_random.6191156753662228696601804498760680174344548841132091817329800640563961179424
Directory /workspace/69.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random.112666676954967294389289939268983575893059654299126716897999176101817456052722
Short name T108
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.7 seconds
Started Nov 22 03:10:10 PM PST 23
Finished Nov 22 03:11:31 PM PST 23
Peak memory 553792 kb
Host smart-b6ae5e11-0229-47dd-b0ad-a57db8534bff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112666676954967294389289939268983575893059654299126716897999176101817456052722 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 69.xbar_random.112666676954967294389289939268983575893059654299126716897999176101817456052722
Directory /workspace/69.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.86074616114067101784268160847156914680837167890744978581459394348181770378201
Short name T893
Test name
Test status
Simulation time 97702135727 ps
CPU time 1081.58 seconds
Started Nov 22 03:10:10 PM PST 23
Finished Nov 22 03:28:12 PM PST 23
Peak memory 553660 kb
Host smart-a65675d4-634e-48ef-960c-e890b6a75445
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86074616114067101784268160847156914680837167890744978581459394348181770378201 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.86074616114067101784268160847156914680837167890744978581459394348181770378201
Directory /workspace/69.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2515342586751286722445426829680019495282739526890332789830853641739198332924
Short name T1066
Test name
Test status
Simulation time 60576345727 ps
CPU time 1102.35 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:28:33 PM PST 23
Peak memory 553704 kb
Host smart-fee7a130-30d3-4a10-8fb5-94275bf1c7cc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515342586751286722445426829680019495282739526890332789830853641739198332924 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.2515342586751286722445426829680019495282739526890332789830853641739198332924
Directory /workspace/69.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.59961139297058614388850493526110512017916187122813258177016185701008145409054
Short name T1227
Test name
Test status
Simulation time 556965727 ps
CPU time 48.18 seconds
Started Nov 22 03:10:06 PM PST 23
Finished Nov 22 03:10:55 PM PST 23
Peak memory 553736 kb
Host smart-3b9dff5d-2048-4614-8317-8943d36bd93a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59961139297058614388850493526110512017916187122813258177016185701008145409054 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_delays.59961139297058614388850493526110512017916187122813258177016185701008145409054
Directory /workspace/69.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_same_source.93930099140978160140102523632142849952708864897489301175391170044455102211424
Short name T801
Test name
Test status
Simulation time 2498784073 ps
CPU time 68.84 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:11:18 PM PST 23
Peak memory 553724 kb
Host smart-1ddda3f0-3a44-43ea-a0d5-2bed2f017e24
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93930099140978160140102523632142849952708864897489301175391170044455102211424 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.93930099140978160140102523632142849952708864897489301175391170044455102211424
Directory /workspace/69.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke.106959142860232650255948559359753637855044028401540273079704411562245690748664
Short name T1474
Test name
Test status
Simulation time 196985727 ps
CPU time 8.81 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:10:18 PM PST 23
Peak memory 552388 kb
Host smart-db26fe19-8895-4737-bafb-42a5bd359a5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106959142860232650255948559359753637855044028401540273079704411562245690748664 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 69.xbar_smoke.106959142860232650255948559359753637855044028401540273079704411562245690748664
Directory /workspace/69.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.108545434004923013371259409891050312938406778300029665065162281017037264402267
Short name T1784
Test name
Test status
Simulation time 7758585727 ps
CPU time 87.15 seconds
Started Nov 22 03:10:08 PM PST 23
Finished Nov 22 03:11:36 PM PST 23
Peak memory 552364 kb
Host smart-bb371467-c5fa-43af-b124-ab903cc779fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108545434004923013371259409891050312938406778300029665065162281017037264402267 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.108545434004923013371259409891050312938406778300029665065162281017037264402267
Directory /workspace/69.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.6269294977684219555335114136971430590547040637677078494666433480247264644043
Short name T932
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.94 seconds
Started Nov 22 03:10:06 PM PST 23
Finished Nov 22 03:11:36 PM PST 23
Peak memory 552360 kb
Host smart-4f3b07eb-2c08-45b3-bb7d-403014bf5419
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6269294977684219555335114136971430590547040637677078494666433480247264644043 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.6269294977684219555335114136971430590547040637677078494666433480247264644043
Directory /workspace/69.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.102493748534967926251546250632467025133670998327628913624502650155135194163091
Short name T1908
Test name
Test status
Simulation time 45555727 ps
CPU time 6.14 seconds
Started Nov 22 03:10:08 PM PST 23
Finished Nov 22 03:10:15 PM PST 23
Peak memory 552376 kb
Host smart-f8b5b3b7-a39d-4cfe-b832-2ab00707f67e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102493748534967926251546250632467025133670998327628913624502650155135194163091 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays.102493748534967926251546250632467025133670998327628913624502650155135194163091
Directory /workspace/69.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all.104541381223998523443371181126604351855310563641115783054210623528592392959760
Short name T935
Test name
Test status
Simulation time 13992004073 ps
CPU time 549.06 seconds
Started Nov 22 03:10:11 PM PST 23
Finished Nov 22 03:19:20 PM PST 23
Peak memory 555828 kb
Host smart-cd91c8e2-145c-439e-82d5-7cc6b7cabf2d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104541381223998523443371181126604351855310563641115783054210623528592392959760 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.104541381223998523443371181126604351855310563641115783054210623528592392959760
Directory /workspace/69.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.49887985690750256336649754915581477441170573392352834419120617226048228986727
Short name T697
Test name
Test status
Simulation time 13999524073 ps
CPU time 506.39 seconds
Started Nov 22 03:10:09 PM PST 23
Finished Nov 22 03:18:36 PM PST 23
Peak memory 555728 kb
Host smart-d065775f-656c-44f7-ab84-9feb52f28314
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49887985690750256336649754915581477441170573392352834419120617226048228986727 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.49887985690750256336649754915581477441170573392352834419120617226048228986727
Directory /workspace/69.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.24027945029470027004181302765406176445999441425519895242381250576386839943260
Short name T1584
Test name
Test status
Simulation time 4815189184 ps
CPU time 370.11 seconds
Started Nov 22 03:10:08 PM PST 23
Finished Nov 22 03:16:18 PM PST 23
Peak memory 557240 kb
Host smart-10c8ac70-cf1e-4bfa-81ff-eb308b7e9dff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24027945029470027004181302765406176445999441425519895242381250576386839943260 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_rand_reset.24027945029470027004181302765406176445999441425519895242381250
576386839943260
Directory /workspace/69.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.43268520726186906307243303059789933575941427566673617599508110138313314295358
Short name T1867
Test name
Test status
Simulation time 4815189184 ps
CPU time 305.22 seconds
Started Nov 22 03:10:08 PM PST 23
Finished Nov 22 03:15:14 PM PST 23
Peak memory 559728 kb
Host smart-66e620ca-baad-4b7a-9e45-e5e4ac8b1b0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43268520726186906307243303059789933575941427566673617599508110138313314295358 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_reset_error.432685207261869063072433030597899335759414275666736175995081
10138313314295358
Directory /workspace/69.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.88422929092229810405687338955177594556437701734243216680162533665737463781482
Short name T973
Test name
Test status
Simulation time 1176995727 ps
CPU time 55 seconds
Started Nov 22 03:10:08 PM PST 23
Finished Nov 22 03:11:04 PM PST 23
Peak memory 553716 kb
Host smart-26a643d8-a03a-4667-8f8b-73477a5ee95a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88422929092229810405687338955177594556437701734243216680162533665737463781482 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.88422929092229810405687338955177594556437701734243216680162533665737463781482
Directory /workspace/69.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.103721715804798042960159634419883113967994729962547965814075217927213087241814
Short name T43
Test name
Test status
Simulation time 7234930891 ps
CPU time 313.29 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:08:57 PM PST 23
Peak memory 622492 kb
Host smart-ff7a7cbc-61a9-4aa8-80ed-999c58583735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037217158047980429601596344198
83113967994729962547965814075217927213087241814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.103721715804
798042960159634419883113967994729962547965814075217927213087241814
Directory /workspace/7.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_rw.74425735649555522203358150916035761279190038985101737919179904762607993363824
Short name T1440
Test name
Test status
Simulation time 5924944675 ps
CPU time 526.69 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:12:29 PM PST 23
Peak memory 580496 kb
Host smart-50cd486e-2f1f-41f6-9074-f34d0df9f351
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74425735649555522203358150916035761279190038985101737919179904762607993363824 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.74425735649555522203358150916035761279190038985101737919179904762607993363824
Directory /workspace/7.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.38863156161981540130965966892176416420876204311432073984635770845213693124525
Short name T1699
Test name
Test status
Simulation time 30604932618 ps
CPU time 3159.25 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:56:36 PM PST 23
Peak memory 580632 kb
Host smart-2bde0402-8ca1-4049-8c4f-a01c903cbc6b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886315616198154013096596689217641642
0876204311432073984635770845213693124525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3886315616198154013096596
6892176416420876204311432073984635770845213693124525
Directory /workspace/7.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.chip_tl_errors.64805994962929046699555024926820068210152225121003514078313922881305053222818
Short name T86
Test name
Test status
Simulation time 3069924257 ps
CPU time 176.28 seconds
Started Nov 22 03:03:42 PM PST 23
Finished Nov 22 03:06:40 PM PST 23
Peak memory 580484 kb
Host smart-cb7248a9-5f62-449d-9708-efd4eb99cdb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64805994962929046699555024926820068210152225121003514078313922881305053222818 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.64805994962929046699555024926820068210152225121003514078313922881305053222818
Directory /workspace/7.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device.94343518272731381811532080478882051258647640210980705799724361560443181549997
Short name T1631
Test name
Test status
Simulation time 2590995727 ps
CPU time 100.41 seconds
Started Nov 22 03:03:44 PM PST 23
Finished Nov 22 03:05:26 PM PST 23
Peak memory 554388 kb
Host smart-e08b13a4-e4a6-4ad7-a475-2ddfb5d5fcc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94343518272731381811532080478882051258647640210980705799724361560443181549997 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.94343518272731381811532080478882051258647640210980705799724361560443181549997
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.52776878235492581331604974631749807399543434559614620341495462927191670314652
Short name T1447
Test name
Test status
Simulation time 115195295727 ps
CPU time 1837.15 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:34:18 PM PST 23
Peak memory 554744 kb
Host smart-66fa1677-1c4c-4165-b9ab-156b4f1552a7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52776878235492581331604974631749807399543434559614620341495462927191670314652 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.52776878235492581331604974631749807399543434559614620341495462927191670314652
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.41061559685045358706938364714701968516109164020820653852809205029112806899756
Short name T1552
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.14 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:04:23 PM PST 23
Peak memory 553480 kb
Host smart-38a4ee22-60ba-4a63-bbbf-46ccb3644777
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41061559685045358706938364714701968516109164020820653852809205029112806899756 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.41061559685045358706938364714701968516109164020820653852809205029112806899756
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_random.33163761770983132802206777789615710278360856935485799938773831314201405788897
Short name T580
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.21 seconds
Started Nov 22 03:03:29 PM PST 23
Finished Nov 22 03:04:41 PM PST 23
Peak memory 553540 kb
Host smart-3ecfa205-a298-419f-a65d-aa888d990885
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33163761770983132802206777789615710278360856935485799938773831314201405788897 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.xbar_error_random.33163761770983132802206777789615710278360856935485799938773831314201405788897
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random.63502709031155863249644150821034913739536089948740715160588681796233218495942
Short name T1030
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.78 seconds
Started Nov 22 03:03:58 PM PST 23
Finished Nov 22 03:05:10 PM PST 23
Peak memory 553664 kb
Host smart-86526dc1-3010-404b-806f-557e3d335e0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63502709031155863249644150821034913739536089948740715160588681796233218495942 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.xbar_random.63502709031155863249644150821034913739536089948740715160588681796233218495942
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.31075025651342474321565317352957609297637522596129269499386902227792206042211
Short name T1263
Test name
Test status
Simulation time 97702135727 ps
CPU time 1155.69 seconds
Started Nov 22 03:03:45 PM PST 23
Finished Nov 22 03:23:02 PM PST 23
Peak memory 553672 kb
Host smart-af85fcb4-ee39-4e23-8ec3-a718aa810599
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31075025651342474321565317352957609297637522596129269499386902227792206042211 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.31075025651342474321565317352957609297637522596129269499386902227792206042211
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.83111825313927504393655332519543022338146617023607289520865686377776829816188
Short name T1859
Test name
Test status
Simulation time 60576345727 ps
CPU time 1075.1 seconds
Started Nov 22 03:04:00 PM PST 23
Finished Nov 22 03:21:56 PM PST 23
Peak memory 553700 kb
Host smart-af376dcc-88e9-4b07-bd73-c082f0f25e53
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83111825313927504393655332519543022338146617023607289520865686377776829816188 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.83111825313927504393655332519543022338146617023607289520865686377776829816188
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.30556379665855956177524804714109826760166166927716745010986279862180413225793
Short name T813
Test name
Test status
Simulation time 556965727 ps
CPU time 45.51 seconds
Started Nov 22 03:03:54 PM PST 23
Finished Nov 22 03:04:40 PM PST 23
Peak memory 553712 kb
Host smart-e2289b37-576d-4d48-80dc-ed5c6d2b9be8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30556379665855956177524804714109826760166166927716745010986279862180413225793 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.30556379665855956177524804714109826760166166927716745010986279862180413225793
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_same_source.29998157347862347267160981629613995569310366229585148602787630120861927992793
Short name T216
Test name
Test status
Simulation time 2498784073 ps
CPU time 70.5 seconds
Started Nov 22 03:03:39 PM PST 23
Finished Nov 22 03:04:50 PM PST 23
Peak memory 553728 kb
Host smart-daa8af82-c339-4f11-99ca-c9a8e01c94d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29998157347862347267160981629613995569310366229585148602787630120861927992793 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.29998157347862347267160981629613995569310366229585148602787630120861927992793
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke.4644101245506458657074149117809137963374638951481475845727301730253240235675
Short name T1812
Test name
Test status
Simulation time 196985727 ps
CPU time 7.87 seconds
Started Nov 22 03:03:54 PM PST 23
Finished Nov 22 03:04:02 PM PST 23
Peak memory 552348 kb
Host smart-339222a7-d903-4e98-a551-40703ec1c5b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4644101245506458657074149117809137963374638951481475845727301730253240235675 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.xbar_smoke.4644101245506458657074149117809137963374638951481475845727301730253240235675
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.27981021607925569944420447853891188514244014792103750084509934090653305984858
Short name T1272
Test name
Test status
Simulation time 7758585727 ps
CPU time 86.39 seconds
Started Nov 22 03:03:58 PM PST 23
Finished Nov 22 03:05:25 PM PST 23
Peak memory 552324 kb
Host smart-01a29273-759c-4cbc-a079-2a9dec99e714
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27981021607925569944420447853891188514244014792103750084509934090653305984858 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.27981021607925569944420447853891188514244014792103750084509934090653305984858
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.96789258675366080168440805695255936268130814986113860718063682006145626677549
Short name T1201
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.51 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:05:07 PM PST 23
Peak memory 552444 kb
Host smart-38bdd28b-8126-43dd-aa1f-6542caeea2fe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96789258675366080168440805695255936268130814986113860718063682006145626677549 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.96789258675366080168440805695255936268130814986113860718063682006145626677549
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.4298731015959857638216777748798190776116531214874973894448517997187331686098
Short name T832
Test name
Test status
Simulation time 45555727 ps
CPU time 5.68 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:04:02 PM PST 23
Peak memory 552296 kb
Host smart-10336a9e-8a9f-489d-8df3-d49d50bdf763
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4298731015959857638216777748798190776116531214874973894448517997187331686098 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.4298731015959857638216777748798190776116531214874973894448517997187331686098
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all.62764102854076986661277296844785487277979214492211461713832625415448392740109
Short name T1139
Test name
Test status
Simulation time 13992004073 ps
CPU time 487.13 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:11:49 PM PST 23
Peak memory 555896 kb
Host smart-81f575f8-9045-41b7-81b5-b97b48b77c5f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62764102854076986661277296844785487277979214492211461713832625415448392740109 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.62764102854076986661277296844785487277979214492211461713832625415448392740109
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.17803858453174296047282707740271890626128026351247975069845898812533474102054
Short name T1430
Test name
Test status
Simulation time 13999524073 ps
CPU time 534.43 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:12:33 PM PST 23
Peak memory 555724 kb
Host smart-e2cd26cc-b7bb-43dd-8155-121c821181a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17803858453174296047282707740271890626128026351247975069845898812533474102054 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.17803858453174296047282707740271890626128026351247975069845898812533474102054
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.41736016245970786124564822717679806612930348480365554452679894446129362338724
Short name T367
Test name
Test status
Simulation time 4815189184 ps
CPU time 371.14 seconds
Started Nov 22 03:03:30 PM PST 23
Finished Nov 22 03:09:42 PM PST 23
Peak memory 557244 kb
Host smart-7becf9d3-bc30-4581-8ab4-62214772fed4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41736016245970786124564822717679806612930348480365554452679894446129362338724 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.417360162459707861245648227176798066129303484803655544526798944
46129362338724
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.26898409089412441694886178111108724093724352633548874387880981566054895597237
Short name T1308
Test name
Test status
Simulation time 4815189184 ps
CPU time 308.86 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:08:50 PM PST 23
Peak memory 559676 kb
Host smart-a4853d67-ecb8-405a-914b-a6bb184b9818
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26898409089412441694886178111108724093724352633548874387880981566054895597237 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2689840908941244169488617811110872409372435263354887438788098
1566054895597237
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.110551555456957871160458396411402820315429674353708449598151497908154598676139
Short name T1277
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.3 seconds
Started Nov 22 03:03:39 PM PST 23
Finished Nov 22 03:04:25 PM PST 23
Peak memory 553680 kb
Host smart-c1f6e110-2790-4a89-87d5-a9c004e2d7fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110551555456957871160458396411402820315429674353708449598151497908154598676139 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.110551555456957871160458396411402820315429674353708449598151497908154598676139
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device.67981412619390557575376165121821362663851072615511110144070458433229811839875
Short name T1834
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.84 seconds
Started Nov 22 03:10:19 PM PST 23
Finished Nov 22 03:12:06 PM PST 23
Peak memory 554780 kb
Host smart-f4ce93fa-0a46-474d-9fbb-fb82865e44df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67981412619390557575376165121821362663851072615511110144070458433229811839875 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.67981412619390557575376165121821362663851072615511110144070458433229811839875
Directory /workspace/70.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.99128944945145584071817191949067391658570452419941376618835378533426395662551
Short name T486
Test name
Test status
Simulation time 115195295727 ps
CPU time 2041.05 seconds
Started Nov 22 03:10:20 PM PST 23
Finished Nov 22 03:44:22 PM PST 23
Peak memory 554772 kb
Host smart-7c6d42ed-43d3-4ddb-85b5-1972b4fc4acf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99128944945145584071817191949067391658570452419941376618835378533426395662551 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device_slow_rsp.99128944945145584071817191949067391658570452419941376618835378533426395662551
Directory /workspace/70.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.42762961385773674294049921489738503052976475905717322197271194410424117070715
Short name T214
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.78 seconds
Started Nov 22 03:10:18 PM PST 23
Finished Nov 22 03:11:02 PM PST 23
Peak memory 553464 kb
Host smart-d1ada2fc-84c1-4013-ab1e-a74c9b215cf9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42762961385773674294049921489738503052976475905717322197271194410424117070715 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr.42762961385773674294049921489738503052976475905717322197271194410424117070715
Directory /workspace/70.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_random.78434754542873879376985385886767681685908550068639304110011844903381559483788
Short name T1153
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.03 seconds
Started Nov 22 03:10:18 PM PST 23
Finished Nov 22 03:11:36 PM PST 23
Peak memory 553460 kb
Host smart-dfca9d57-3d70-4ccd-a2aa-11a1225cabeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78434754542873879376985385886767681685908550068639304110011844903381559483788 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 70.xbar_error_random.78434754542873879376985385886767681685908550068639304110011844903381559483788
Directory /workspace/70.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random.32016762509549252413469934735207721439043273860724577091434220374563257661755
Short name T309
Test name
Test status
Simulation time 2231375727 ps
CPU time 85.48 seconds
Started Nov 22 03:10:19 PM PST 23
Finished Nov 22 03:11:45 PM PST 23
Peak memory 553852 kb
Host smart-a35db67c-8c29-4bd2-ac08-3115af1cec4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32016762509549252413469934735207721439043273860724577091434220374563257661755 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 70.xbar_random.32016762509549252413469934735207721439043273860724577091434220374563257661755
Directory /workspace/70.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.58984410213618510766504158805527647335988322209591928514164549062847503739436
Short name T1274
Test name
Test status
Simulation time 97702135727 ps
CPU time 1125.04 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:29:12 PM PST 23
Peak memory 553664 kb
Host smart-11a166da-8a74-4aa2-87c6-ed61d6b35dc8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58984410213618510766504158805527647335988322209591928514164549062847503739436 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.58984410213618510766504158805527647335988322209591928514164549062847503739436
Directory /workspace/70.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.18749102202687657759939455571848433163128703111046831279976676786925377642714
Short name T354
Test name
Test status
Simulation time 60576345727 ps
CPU time 1111.76 seconds
Started Nov 22 03:10:25 PM PST 23
Finished Nov 22 03:28:57 PM PST 23
Peak memory 553812 kb
Host smart-51b8c86d-7d2d-4bc6-9ff1-ee046e70a41e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18749102202687657759939455571848433163128703111046831279976676786925377642714 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.18749102202687657759939455571848433163128703111046831279976676786925377642714
Directory /workspace/70.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.16970202173122022854073285182946380315750112272157263110664784265441539017325
Short name T838
Test name
Test status
Simulation time 556965727 ps
CPU time 47.95 seconds
Started Nov 22 03:10:23 PM PST 23
Finished Nov 22 03:11:12 PM PST 23
Peak memory 553824 kb
Host smart-3522208d-62d5-466d-b568-fbb272ef7859
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16970202173122022854073285182946380315750112272157263110664784265441539017325 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_delays.16970202173122022854073285182946380315750112272157263110664784265441539017325
Directory /workspace/70.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_same_source.68868876391737046558026916352379222449808308878483785216704605997204554520182
Short name T1365
Test name
Test status
Simulation time 2498784073 ps
CPU time 75 seconds
Started Nov 22 03:10:20 PM PST 23
Finished Nov 22 03:11:36 PM PST 23
Peak memory 553616 kb
Host smart-808f0ce9-4252-46e9-988a-fe4cdefc66a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68868876391737046558026916352379222449808308878483785216704605997204554520182 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.68868876391737046558026916352379222449808308878483785216704605997204554520182
Directory /workspace/70.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke.49477049045699658944377447862357980813341411100525725215492984904143638868303
Short name T153
Test name
Test status
Simulation time 196985727 ps
CPU time 8.4 seconds
Started Nov 22 03:10:12 PM PST 23
Finished Nov 22 03:10:21 PM PST 23
Peak memory 552368 kb
Host smart-22c079e9-f5e2-43f9-9122-0a8948210e65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49477049045699658944377447862357980813341411100525725215492984904143638868303 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 70.xbar_smoke.49477049045699658944377447862357980813341411100525725215492984904143638868303
Directory /workspace/70.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.93941745950631423883858540071691275212742745204055311733306377368306768041399
Short name T482
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.63 seconds
Started Nov 22 03:10:07 PM PST 23
Finished Nov 22 03:11:36 PM PST 23
Peak memory 552380 kb
Host smart-19764bd1-3ba0-4576-9320-2f58f4f12818
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93941745950631423883858540071691275212742745204055311733306377368306768041399 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.93941745950631423883858540071691275212742745204055311733306377368306768041399
Directory /workspace/70.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.68394849443400878161141356266161825494714190360605010613222682758098316104
Short name T258
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.81 seconds
Started Nov 22 03:10:07 PM PST 23
Finished Nov 22 03:11:38 PM PST 23
Peak memory 552372 kb
Host smart-11deaea4-f24a-4af5-be56-37618acf8fda
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68394849443400878161141356266161825494714190360605010613222682758098316104 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.68394849443400878161141356266161825494714190360605010613222682758098316104
Directory /workspace/70.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.86890986431218628887339753523929124414056417622016992941236999321119235138489
Short name T1657
Test name
Test status
Simulation time 45555727 ps
CPU time 6.04 seconds
Started Nov 22 03:10:07 PM PST 23
Finished Nov 22 03:10:14 PM PST 23
Peak memory 552360 kb
Host smart-a71035d5-5bdf-43b1-966a-6a66125b5e32
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86890986431218628887339753523929124414056417622016992941236999321119235138489 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays.86890986431218628887339753523929124414056417622016992941236999321119235138489
Directory /workspace/70.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all.39165005908455642752109359676269016898854127380899127632439402991358261369012
Short name T1090
Test name
Test status
Simulation time 13992004073 ps
CPU time 553.2 seconds
Started Nov 22 03:10:24 PM PST 23
Finished Nov 22 03:19:38 PM PST 23
Peak memory 555912 kb
Host smart-a86657ea-acde-4704-a6f0-4aaaee7078a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165005908455642752109359676269016898854127380899127632439402991358261369012 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.39165005908455642752109359676269016898854127380899127632439402991358261369012
Directory /workspace/70.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.99636969700994652495910911538604039675633681189252063512187325633421562415213
Short name T1469
Test name
Test status
Simulation time 13999524073 ps
CPU time 522.27 seconds
Started Nov 22 03:10:18 PM PST 23
Finished Nov 22 03:19:01 PM PST 23
Peak memory 555708 kb
Host smart-e6e44402-5812-4611-ac90-53b5c06fb4cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99636969700994652495910911538604039675633681189252063512187325633421562415213 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.99636969700994652495910911538604039675633681189252063512187325633421562415213
Directory /workspace/70.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.105120576328850869084175937448288245646952834270188950843244661171403789280054
Short name T477
Test name
Test status
Simulation time 4815189184 ps
CPU time 371.37 seconds
Started Nov 22 03:10:17 PM PST 23
Finished Nov 22 03:16:29 PM PST 23
Peak memory 557252 kb
Host smart-2f4608e8-3271-481b-af80-1f9e7a9d608f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105120576328850869084175937448288245646952834270188950843244661171403789280054 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_rand_reset.1051205763288508690841759374482882456469528342701889508432446
61171403789280054
Directory /workspace/70.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.67739230596722405355499168983239828867662012335616686564485944102340587437089
Short name T830
Test name
Test status
Simulation time 4815189184 ps
CPU time 313.87 seconds
Started Nov 22 03:10:17 PM PST 23
Finished Nov 22 03:15:32 PM PST 23
Peak memory 559724 kb
Host smart-83f7d570-abea-4a21-8435-d3e1a3e82d73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67739230596722405355499168983239828867662012335616686564485944102340587437089 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_reset_error.677392305967224053554991689832398288676620123356166865644859
44102340587437089
Directory /workspace/70.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.89620760881287245871727994149055562069227789429718046045393358122887065001546
Short name T1246
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.97 seconds
Started Nov 22 03:10:18 PM PST 23
Finished Nov 22 03:11:06 PM PST 23
Peak memory 553716 kb
Host smart-4a94a30f-ebaf-45fc-a487-105b4e23ba77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89620760881287245871727994149055562069227789429718046045393358122887065001546 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.89620760881287245871727994149055562069227789429718046045393358122887065001546
Directory /workspace/70.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device.9656215432316166099692295187252159869584557688440546559398400761708314716356
Short name T1117
Test name
Test status
Simulation time 2590995727 ps
CPU time 116.51 seconds
Started Nov 22 03:10:24 PM PST 23
Finished Nov 22 03:12:21 PM PST 23
Peak memory 554752 kb
Host smart-b213332f-cafd-429e-a250-f79ef046246e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9656215432316166099692295187252159869584557688440546559398400761708314716356 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.9656215432316166099692295187252159869584557688440546559398400761708314716356
Directory /workspace/71.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.52427066780713830685094341467138669362216970449396599422943730259172844534839
Short name T1253
Test name
Test status
Simulation time 115195295727 ps
CPU time 2013.06 seconds
Started Nov 22 03:10:18 PM PST 23
Finished Nov 22 03:43:52 PM PST 23
Peak memory 554760 kb
Host smart-bcf2501c-d3bf-4e3a-ad08-6753b9509273
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52427066780713830685094341467138669362216970449396599422943730259172844534839 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device_slow_rsp.52427066780713830685094341467138669362216970449396599422943730259172844534839
Directory /workspace/71.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.43636538334677232089052183991990056796287106323651931275410670357283264766795
Short name T1885
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.9 seconds
Started Nov 22 03:10:23 PM PST 23
Finished Nov 22 03:11:10 PM PST 23
Peak memory 553572 kb
Host smart-6f8f71c7-2027-43a5-a4ea-65204bfa9c58
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43636538334677232089052183991990056796287106323651931275410670357283264766795 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.43636538334677232089052183991990056796287106323651931275410670357283264766795
Directory /workspace/71.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_random.48160014415257374309481673058314612436808463628159922828162077939829854465757
Short name T1860
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.86 seconds
Started Nov 22 03:10:20 PM PST 23
Finished Nov 22 03:11:32 PM PST 23
Peak memory 553516 kb
Host smart-a5d3e4eb-b55c-4f96-8cd4-176ce9112fc3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48160014415257374309481673058314612436808463628159922828162077939829854465757 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 71.xbar_error_random.48160014415257374309481673058314612436808463628159922828162077939829854465757
Directory /workspace/71.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random.47497913953565695667498950049475187105910095506680324383224717806586810589404
Short name T436
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.6 seconds
Started Nov 22 03:10:17 PM PST 23
Finished Nov 22 03:11:36 PM PST 23
Peak memory 553724 kb
Host smart-ed5e67eb-401e-4e7c-ae74-f93a85ecd333
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47497913953565695667498950049475187105910095506680324383224717806586810589404 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 71.xbar_random.47497913953565695667498950049475187105910095506680324383224717806586810589404
Directory /workspace/71.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.99998461688622483485045994367517743821611659827854930117090680282163499420419
Short name T962
Test name
Test status
Simulation time 97702135727 ps
CPU time 1167.37 seconds
Started Nov 22 03:10:22 PM PST 23
Finished Nov 22 03:29:50 PM PST 23
Peak memory 553780 kb
Host smart-8637531b-df2d-4407-89b1-70881a7f762c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99998461688622483485045994367517743821611659827854930117090680282163499420419 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.99998461688622483485045994367517743821611659827854930117090680282163499420419
Directory /workspace/71.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.27120385348928805416400364260089506495447951501161582104444509810737761975939
Short name T1061
Test name
Test status
Simulation time 60576345727 ps
CPU time 1108.64 seconds
Started Nov 22 03:10:23 PM PST 23
Finished Nov 22 03:28:52 PM PST 23
Peak memory 553800 kb
Host smart-b6f6be35-1b89-4657-a37a-3c05700ea7e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27120385348928805416400364260089506495447951501161582104444509810737761975939 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.27120385348928805416400364260089506495447951501161582104444509810737761975939
Directory /workspace/71.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.95156568766000637314090350713344897252321892172973478697332603787087958225562
Short name T631
Test name
Test status
Simulation time 556965727 ps
CPU time 45.9 seconds
Started Nov 22 03:10:22 PM PST 23
Finished Nov 22 03:11:09 PM PST 23
Peak memory 553596 kb
Host smart-611539ae-adcd-433e-84ec-00e4f66eb642
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95156568766000637314090350713344897252321892172973478697332603787087958225562 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delays.95156568766000637314090350713344897252321892172973478697332603787087958225562
Directory /workspace/71.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_same_source.112064133540571400901580112591819672606579896152764477617362964459567713790272
Short name T502
Test name
Test status
Simulation time 2498784073 ps
CPU time 79.43 seconds
Started Nov 22 03:10:23 PM PST 23
Finished Nov 22 03:11:43 PM PST 23
Peak memory 553840 kb
Host smart-43d9f61b-2a2a-4600-8a31-e0ef77ad02ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112064133540571400901580112591819672606579896152764477617362964459567713790272 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.112064133540571400901580112591819672606579896152764477617362964459567713790272
Directory /workspace/71.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke.1522993263471272449858690159601571500140559340456400743419255682585437664283
Short name T789
Test name
Test status
Simulation time 196985727 ps
CPU time 8.61 seconds
Started Nov 22 03:10:24 PM PST 23
Finished Nov 22 03:10:33 PM PST 23
Peak memory 552332 kb
Host smart-b1f2ec43-a4e6-4632-80ac-b51b910d23a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522993263471272449858690159601571500140559340456400743419255682585437664283 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 71.xbar_smoke.1522993263471272449858690159601571500140559340456400743419255682585437664283
Directory /workspace/71.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.78762963355235292829549703175357731865733921385425713938202052503987526273697
Short name T1434
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.77 seconds
Started Nov 22 03:10:17 PM PST 23
Finished Nov 22 03:11:48 PM PST 23
Peak memory 552384 kb
Host smart-29ee536c-c0bd-4b57-aca4-95763e058ef3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78762963355235292829549703175357731865733921385425713938202052503987526273697 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.78762963355235292829549703175357731865733921385425713938202052503987526273697
Directory /workspace/71.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.36438951878440590047208332802403048913811861225851555635235642887151026770097
Short name T825
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.34 seconds
Started Nov 22 03:10:23 PM PST 23
Finished Nov 22 03:11:53 PM PST 23
Peak memory 552392 kb
Host smart-6d63cc7f-6e07-4031-88f8-0ffee96cbc45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36438951878440590047208332802403048913811861225851555635235642887151026770097 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.36438951878440590047208332802403048913811861225851555635235642887151026770097
Directory /workspace/71.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.47598258622082797863226512608517153818050266277503248802318337171970852427903
Short name T1186
Test name
Test status
Simulation time 45555727 ps
CPU time 6.11 seconds
Started Nov 22 03:10:30 PM PST 23
Finished Nov 22 03:10:36 PM PST 23
Peak memory 552312 kb
Host smart-b789538a-0b80-4745-b9f4-766dce0df23d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47598258622082797863226512608517153818050266277503248802318337171970852427903 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays.47598258622082797863226512608517153818050266277503248802318337171970852427903
Directory /workspace/71.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all.92134678416898056973843806605855440572472408149464884907041738337978221312618
Short name T1005
Test name
Test status
Simulation time 13992004073 ps
CPU time 500.38 seconds
Started Nov 22 03:10:21 PM PST 23
Finished Nov 22 03:18:42 PM PST 23
Peak memory 555792 kb
Host smart-bda3fa84-21e8-4da3-b21b-7bf176514b3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92134678416898056973843806605855440572472408149464884907041738337978221312618 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.92134678416898056973843806605855440572472408149464884907041738337978221312618
Directory /workspace/71.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.98577000759089595336288872693073053426264747095533808590636646891471451956505
Short name T705
Test name
Test status
Simulation time 13999524073 ps
CPU time 532.85 seconds
Started Nov 22 03:10:20 PM PST 23
Finished Nov 22 03:19:14 PM PST 23
Peak memory 555608 kb
Host smart-3fb072ca-0652-450f-b2eb-c2241667ea0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98577000759089595336288872693073053426264747095533808590636646891471451956505 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.98577000759089595336288872693073053426264747095533808590636646891471451956505
Directory /workspace/71.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.42377014691500423654841881563284122123274831899951173473974853390466457106051
Short name T513
Test name
Test status
Simulation time 4815189184 ps
CPU time 365.01 seconds
Started Nov 22 03:10:24 PM PST 23
Finished Nov 22 03:16:30 PM PST 23
Peak memory 557368 kb
Host smart-f97fa6ce-fdce-4153-a1bf-024faef9ee20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42377014691500423654841881563284122123274831899951173473974853390466457106051 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_rand_reset.42377014691500423654841881563284122123274831899951173473974853
390466457106051
Directory /workspace/71.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.48678665609284719809722417917497593728434412494922548278842192633264371882270
Short name T1514
Test name
Test status
Simulation time 4815189184 ps
CPU time 324.88 seconds
Started Nov 22 03:10:26 PM PST 23
Finished Nov 22 03:15:52 PM PST 23
Peak memory 559720 kb
Host smart-a2371b8f-f956-456b-84ba-a18e1e395a6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48678665609284719809722417917497593728434412494922548278842192633264371882270 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_reset_error.486786656092847198097224179174975937284344124949225482788421
92633264371882270
Directory /workspace/71.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.112004356286477087557324947906328093820582250403662126723979473764770011782261
Short name T1360
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.69 seconds
Started Nov 22 03:10:17 PM PST 23
Finished Nov 22 03:11:07 PM PST 23
Peak memory 553752 kb
Host smart-5398f96a-b61a-4ed3-9ce8-94baff6917a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112004356286477087557324947906328093820582250403662126723979473764770011782261 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.112004356286477087557324947906328093820582250403662126723979473764770011782261
Directory /workspace/71.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device.96316399433088531182969505939341557845615870528135530366874042149243060168064
Short name T1623
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.05 seconds
Started Nov 22 03:10:24 PM PST 23
Finished Nov 22 03:12:13 PM PST 23
Peak memory 554748 kb
Host smart-ae04aed8-1c95-41c6-a3e9-bf43e26b5579
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96316399433088531182969505939341557845615870528135530366874042149243060168064 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device.96316399433088531182969505939341557845615870528135530366874042149243060168064
Directory /workspace/72.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.79693149546121698807444516480186682491902238881339703187820313376084809244999
Short name T143
Test name
Test status
Simulation time 115195295727 ps
CPU time 2035.97 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:44:23 PM PST 23
Peak memory 554776 kb
Host smart-56f2b38e-9028-4913-a7dd-b0c00cf8624d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79693149546121698807444516480186682491902238881339703187820313376084809244999 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device_slow_rsp.79693149546121698807444516480186682491902238881339703187820313376084809244999
Directory /workspace/72.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.63466524266187404439355540552321479304010565036228353270053823362196212452239
Short name T335
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.88 seconds
Started Nov 22 03:10:28 PM PST 23
Finished Nov 22 03:11:15 PM PST 23
Peak memory 553504 kb
Host smart-a382b956-7b91-4622-b7e5-93fc0b0ce957
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63466524266187404439355540552321479304010565036228353270053823362196212452239 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr.63466524266187404439355540552321479304010565036228353270053823362196212452239
Directory /workspace/72.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_random.52575784305194322143646242121190414254963777809363059058640092987623054621197
Short name T1891
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.88 seconds
Started Nov 22 03:10:30 PM PST 23
Finished Nov 22 03:11:46 PM PST 23
Peak memory 553480 kb
Host smart-f19b3bed-2545-4473-8b0d-77f56bd157c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52575784305194322143646242121190414254963777809363059058640092987623054621197 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 72.xbar_error_random.52575784305194322143646242121190414254963777809363059058640092987623054621197
Directory /workspace/72.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random.17414553996944233588699274420744260779456938734352866582060305402166926803696
Short name T1303
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.31 seconds
Started Nov 22 03:10:26 PM PST 23
Finished Nov 22 03:11:46 PM PST 23
Peak memory 553756 kb
Host smart-56003c83-411a-41e6-b6bc-e261d1a0dc5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17414553996944233588699274420744260779456938734352866582060305402166926803696 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 72.xbar_random.17414553996944233588699274420744260779456938734352866582060305402166926803696
Directory /workspace/72.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.73046442743417511101411292807943011524656337225348335249645689037633228114000
Short name T655
Test name
Test status
Simulation time 97702135727 ps
CPU time 1139.81 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:29:27 PM PST 23
Peak memory 553676 kb
Host smart-d0550c9d-c2bb-4300-bea4-7c38c2efa14b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73046442743417511101411292807943011524656337225348335249645689037633228114000 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.73046442743417511101411292807943011524656337225348335249645689037633228114000
Directory /workspace/72.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.42745932900864113683028282282686602245267914808114948667859751220922422836554
Short name T399
Test name
Test status
Simulation time 60576345727 ps
CPU time 1115.83 seconds
Started Nov 22 03:10:30 PM PST 23
Finished Nov 22 03:29:06 PM PST 23
Peak memory 553652 kb
Host smart-11502e82-4aa7-4e10-8422-719251986e95
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42745932900864113683028282282686602245267914808114948667859751220922422836554 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.42745932900864113683028282282686602245267914808114948667859751220922422836554
Directory /workspace/72.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.107206384924512626566939468156311982355234362886008116946618962082509296338166
Short name T1221
Test name
Test status
Simulation time 556965727 ps
CPU time 45.46 seconds
Started Nov 22 03:10:21 PM PST 23
Finished Nov 22 03:11:07 PM PST 23
Peak memory 553672 kb
Host smart-8fdd97df-caff-4b18-b405-0341bccb6b39
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107206384924512626566939468156311982355234362886008116946618962082509296338166 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_delays.107206384924512626566939468156311982355234362886008116946618962082509296338166
Directory /workspace/72.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_same_source.34268545211745850481446797875264379752502637485950385801632053624701040003247
Short name T1535
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.45 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:11:41 PM PST 23
Peak memory 553736 kb
Host smart-9914ad13-01e9-4da5-9e0a-949c7ad4ab70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34268545211745850481446797875264379752502637485950385801632053624701040003247 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.34268545211745850481446797875264379752502637485950385801632053624701040003247
Directory /workspace/72.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke.64256615482310563916424944712147322054834292158885896245126727633349733526767
Short name T379
Test name
Test status
Simulation time 196985727 ps
CPU time 8.71 seconds
Started Nov 22 03:10:30 PM PST 23
Finished Nov 22 03:10:39 PM PST 23
Peak memory 552316 kb
Host smart-45762f11-1e59-47db-8441-fe6d43e02127
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64256615482310563916424944712147322054834292158885896245126727633349733526767 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 72.xbar_smoke.64256615482310563916424944712147322054834292158885896245126727633349733526767
Directory /workspace/72.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.107257178689620802285895476205239226675035729105407422775519894511564935639625
Short name T974
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.35 seconds
Started Nov 22 03:10:28 PM PST 23
Finished Nov 22 03:12:01 PM PST 23
Peak memory 552400 kb
Host smart-73b8f99f-537f-4129-84f3-bf9a03c7e78a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107257178689620802285895476205239226675035729105407422775519894511564935639625 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.107257178689620802285895476205239226675035729105407422775519894511564935639625
Directory /workspace/72.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.36575844124098084856134597824224449320781389961866590304017934470521850119409
Short name T1289
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.82 seconds
Started Nov 22 03:10:21 PM PST 23
Finished Nov 22 03:11:46 PM PST 23
Peak memory 552356 kb
Host smart-4acaa648-f958-4cac-8310-ef5c18a3d112
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575844124098084856134597824224449320781389961866590304017934470521850119409 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.36575844124098084856134597824224449320781389961866590304017934470521850119409
Directory /workspace/72.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.31952978112927371914329705927753504509019684742626521437875077769261670629681
Short name T207
Test name
Test status
Simulation time 45555727 ps
CPU time 5.8 seconds
Started Nov 22 03:10:23 PM PST 23
Finished Nov 22 03:10:30 PM PST 23
Peak memory 552316 kb
Host smart-a86909ee-f40b-4252-bf75-bace4b780181
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31952978112927371914329705927753504509019684742626521437875077769261670629681 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays.31952978112927371914329705927753504509019684742626521437875077769261670629681
Directory /workspace/72.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all.31126741355748239408463597319478192593684444210882264069438499963466045099729
Short name T1260
Test name
Test status
Simulation time 13992004073 ps
CPU time 518.94 seconds
Started Nov 22 03:10:23 PM PST 23
Finished Nov 22 03:19:03 PM PST 23
Peak memory 555864 kb
Host smart-a317b37b-783e-42f0-9942-c022ec293afe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126741355748239408463597319478192593684444210882264069438499963466045099729 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.31126741355748239408463597319478192593684444210882264069438499963466045099729
Directory /workspace/72.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.15600943075054341543204170629354705021641821315904325326942652900728776490956
Short name T959
Test name
Test status
Simulation time 13999524073 ps
CPU time 459.8 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:18:08 PM PST 23
Peak memory 555728 kb
Host smart-a85b52c7-1b57-4764-b113-e24cac2448ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15600943075054341543204170629354705021641821315904325326942652900728776490956 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.15600943075054341543204170629354705021641821315904325326942652900728776490956
Directory /workspace/72.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.47343225804120815375662095648012491343920295782730106041919342818885101803188
Short name T1529
Test name
Test status
Simulation time 4815189184 ps
CPU time 383.59 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:16:51 PM PST 23
Peak memory 557272 kb
Host smart-84749228-edc4-4a63-be32-30eadd9d614b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47343225804120815375662095648012491343920295782730106041919342818885101803188 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_rand_reset.47343225804120815375662095648012491343920295782730106041919342
818885101803188
Directory /workspace/72.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.93213670643887402647150166093674574252401256398570868278050083851680002566190
Short name T571
Test name
Test status
Simulation time 4815189184 ps
CPU time 306.83 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:15:34 PM PST 23
Peak memory 559708 kb
Host smart-852105ce-f79f-40b3-8e77-a1f1efbb000f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93213670643887402647150166093674574252401256398570868278050083851680002566190 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_reset_error.932136706438874026471501660936745742524012563985708682780500
83851680002566190
Directory /workspace/72.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.108490369016208615241527465309476711245031456986298775977239439459058110089367
Short name T997
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.26 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:11:13 PM PST 23
Peak memory 553720 kb
Host smart-d8a9ed7d-3dc1-4b17-aa7e-c8ba42bc7185
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108490369016208615241527465309476711245031456986298775977239439459058110089367 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.108490369016208615241527465309476711245031456986298775977239439459058110089367
Directory /workspace/72.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device.115598382742062777851998469895849292731906198283912252726126676618603408061925
Short name T1464
Test name
Test status
Simulation time 2590995727 ps
CPU time 106.54 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:12:19 PM PST 23
Peak memory 554792 kb
Host smart-ecf730cb-502d-4aa3-9f78-2956d78d70d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115598382742062777851998469895849292731906198283912252726126676618603408061925 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device.115598382742062777851998469895849292731906198283912252726126676618603408061925
Directory /workspace/73.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.104217725949935000100094522367846595742477314362018030461644925131209028581370
Short name T1890
Test name
Test status
Simulation time 115195295727 ps
CPU time 1989.13 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:43:42 PM PST 23
Peak memory 554780 kb
Host smart-38e8d3cc-8afc-49c5-9c16-ca46366f1df8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104217725949935000100094522367846595742477314362018030461644925131209028581370 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device_slow_rsp.104217725949935000100094522367846595742477314362018030461644925131209028581370
Directory /workspace/73.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.109061749293206121390712489649683720689609913079385601785046126792124245568342
Short name T1111
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.42 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:11:18 PM PST 23
Peak memory 553460 kb
Host smart-93f42140-2888-49de-99bd-6d02cd8e8925
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109061749293206121390712489649683720689609913079385601785046126792124245568342 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr.109061749293206121390712489649683720689609913079385601785046126792124245568342
Directory /workspace/73.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_random.6649627601843916160741839802527670073227464084282101935037894705393518818426
Short name T1670
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.38 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:11:48 PM PST 23
Peak memory 553560 kb
Host smart-f2a1d05e-4178-4a11-ac19-20699f08ce51
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6649627601843916160741839802527670073227464084282101935037894705393518818426 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 73.xbar_error_random.6649627601843916160741839802527670073227464084282101935037894705393518818426
Directory /workspace/73.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random.94705578120857514883585731027267123949859672092840483993319403342258796876955
Short name T360
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.89 seconds
Started Nov 22 03:10:33 PM PST 23
Finished Nov 22 03:11:55 PM PST 23
Peak memory 553776 kb
Host smart-8c94efbc-a6ed-4235-9029-79dedb007e7e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94705578120857514883585731027267123949859672092840483993319403342258796876955 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 73.xbar_random.94705578120857514883585731027267123949859672092840483993319403342258796876955
Directory /workspace/73.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.8162791637659262711384553376328223314862590500923700909393194228098287242510
Short name T1419
Test name
Test status
Simulation time 97702135727 ps
CPU time 1170.63 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:30:04 PM PST 23
Peak memory 553684 kb
Host smart-b8b136fb-a707-40c3-bed7-02c415835fc6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8162791637659262711384553376328223314862590500923700909393194228098287242510 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.8162791637659262711384553376328223314862590500923700909393194228098287242510
Directory /workspace/73.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.106927551155800263602321703660153884696914219892703176296187193123449754241971
Short name T1571
Test name
Test status
Simulation time 60576345727 ps
CPU time 1122.74 seconds
Started Nov 22 03:10:33 PM PST 23
Finished Nov 22 03:29:17 PM PST 23
Peak memory 553652 kb
Host smart-a993c326-2c96-4d2b-872e-f28e44359530
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106927551155800263602321703660153884696914219892703176296187193123449754241971 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.106927551155800263602321703660153884696914219892703176296187193123449754241971
Directory /workspace/73.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.32591282824316582663942944778747859724115485583129476039720976389929378300091
Short name T733
Test name
Test status
Simulation time 556965727 ps
CPU time 49.47 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:11:24 PM PST 23
Peak memory 553640 kb
Host smart-df02c823-b91c-4485-921c-3f7e9d96fd87
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591282824316582663942944778747859724115485583129476039720976389929378300091 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_delays.32591282824316582663942944778747859724115485583129476039720976389929378300091
Directory /workspace/73.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_same_source.35574270853309530943340955075510046936601638990306563911741852799684101459643
Short name T1242
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.42 seconds
Started Nov 22 03:10:33 PM PST 23
Finished Nov 22 03:11:46 PM PST 23
Peak memory 553696 kb
Host smart-3175a9c8-86f6-4484-b2f0-4e5f9764fa1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35574270853309530943340955075510046936601638990306563911741852799684101459643 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.35574270853309530943340955075510046936601638990306563911741852799684101459643
Directory /workspace/73.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke.1058005742042725912422818981559809506864145093921420551614565975566377578019
Short name T570
Test name
Test status
Simulation time 196985727 ps
CPU time 8.87 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:10:36 PM PST 23
Peak memory 552384 kb
Host smart-aa77684e-ca16-480b-ab33-0057171d72d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058005742042725912422818981559809506864145093921420551614565975566377578019 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 73.xbar_smoke.1058005742042725912422818981559809506864145093921420551614565975566377578019
Directory /workspace/73.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.57525092591795732123993926676322293509761371107474981944271867491786216591574
Short name T133
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.19 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:12:04 PM PST 23
Peak memory 552492 kb
Host smart-f2b3e29f-76f8-443f-b792-9f4d03fd2b01
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57525092591795732123993926676322293509761371107474981944271867491786216591574 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.57525092591795732123993926676322293509761371107474981944271867491786216591574
Directory /workspace/73.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.50110933450182880856704156651883521458816263311226795112601426155553590740193
Short name T1921
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.52 seconds
Started Nov 22 03:10:31 PM PST 23
Finished Nov 22 03:12:01 PM PST 23
Peak memory 552396 kb
Host smart-e0f29403-65da-4478-9bb0-1ee1bbf0ccd7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50110933450182880856704156651883521458816263311226795112601426155553590740193 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.50110933450182880856704156651883521458816263311226795112601426155553590740193
Directory /workspace/73.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.100899870892467063192502403601691292029467772206556082871320265683826641151927
Short name T345
Test name
Test status
Simulation time 45555727 ps
CPU time 5.77 seconds
Started Nov 22 03:10:27 PM PST 23
Finished Nov 22 03:10:34 PM PST 23
Peak memory 552348 kb
Host smart-734bacef-b419-4c28-abf3-4996770c7116
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100899870892467063192502403601691292029467772206556082871320265683826641151927 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays.100899870892467063192502403601691292029467772206556082871320265683826641151927
Directory /workspace/73.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all.79496389773811980749375716333357148936257865084428499016171708055102126219169
Short name T1000
Test name
Test status
Simulation time 13992004073 ps
CPU time 525.95 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:19:21 PM PST 23
Peak memory 555924 kb
Host smart-15a50fd5-92fb-4ec8-9fd9-0b0a00215276
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79496389773811980749375716333357148936257865084428499016171708055102126219169 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.79496389773811980749375716333357148936257865084428499016171708055102126219169
Directory /workspace/73.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.88558322275841748399109515658430915661350944883407272406071619238116363692468
Short name T1861
Test name
Test status
Simulation time 13999524073 ps
CPU time 503.31 seconds
Started Nov 22 03:10:35 PM PST 23
Finished Nov 22 03:18:59 PM PST 23
Peak memory 555708 kb
Host smart-1b594f65-c6e6-4ce2-abf8-001285a3b0a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88558322275841748399109515658430915661350944883407272406071619238116363692468 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.88558322275841748399109515658430915661350944883407272406071619238116363692468
Directory /workspace/73.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.33485510702992697731374059621801209778429972217377517925886076241716350891363
Short name T632
Test name
Test status
Simulation time 4815189184 ps
CPU time 357.18 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:16:29 PM PST 23
Peak memory 557300 kb
Host smart-a284eee4-30ce-4185-9e6a-3ddf496fb254
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33485510702992697731374059621801209778429972217377517925886076241716350891363 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_rand_reset.33485510702992697731374059621801209778429972217377517925886076
241716350891363
Directory /workspace/73.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.12961966831780292658719060004534970981351405340175025020375206434997695098634
Short name T1577
Test name
Test status
Simulation time 4815189184 ps
CPU time 312.09 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:15:44 PM PST 23
Peak memory 559696 kb
Host smart-aa68fc9e-35a5-48a3-9ec1-a14a1095d71d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12961966831780292658719060004534970981351405340175025020375206434997695098634 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_reset_error.129619668317802926587190600045349709813514053401750250203752
06434997695098634
Directory /workspace/73.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.33804792818491404065583048550407973982925770232541062937704363154555570154901
Short name T1179
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.93 seconds
Started Nov 22 03:10:31 PM PST 23
Finished Nov 22 03:11:22 PM PST 23
Peak memory 553708 kb
Host smart-2bdf3d0d-d545-4f56-9614-d27742e509d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804792818491404065583048550407973982925770232541062937704363154555570154901 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.33804792818491404065583048550407973982925770232541062937704363154555570154901
Directory /workspace/73.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device.35817350861231396661685798591948127878388641379049316295983375151875921178587
Short name T1240
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.2 seconds
Started Nov 22 03:10:35 PM PST 23
Finished Nov 22 03:12:23 PM PST 23
Peak memory 554760 kb
Host smart-6ddb13ec-7e1e-4a54-8fb3-3becda0ea7d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35817350861231396661685798591948127878388641379049316295983375151875921178587 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.35817350861231396661685798591948127878388641379049316295983375151875921178587
Directory /workspace/74.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.22689876196057073586361174408447805062779719738027386052292507081374583979716
Short name T1265
Test name
Test status
Simulation time 115195295727 ps
CPU time 1988.94 seconds
Started Nov 22 03:10:39 PM PST 23
Finished Nov 22 03:43:48 PM PST 23
Peak memory 554664 kb
Host smart-ab560dcf-94b4-4d48-b6f8-4a7adeb497bb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22689876196057073586361174408447805062779719738027386052292507081374583979716 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device_slow_rsp.22689876196057073586361174408447805062779719738027386052292507081374583979716
Directory /workspace/74.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.72367744014060132505416347771557862187248670706847830359819356875061448274412
Short name T411
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.33 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:11:20 PM PST 23
Peak memory 553436 kb
Host smart-dbcba131-6ac5-4e15-ac91-5db5a535a318
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72367744014060132505416347771557862187248670706847830359819356875061448274412 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr.72367744014060132505416347771557862187248670706847830359819356875061448274412
Directory /workspace/74.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_random.68416775232392330977902399944408896483345861645430256073507016543173112182200
Short name T147
Test name
Test status
Simulation time 2231375727 ps
CPU time 74.59 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:11:47 PM PST 23
Peak memory 553612 kb
Host smart-3700d712-ca1c-47c9-be4b-1137e231d279
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68416775232392330977902399944408896483345861645430256073507016543173112182200 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 74.xbar_error_random.68416775232392330977902399944408896483345861645430256073507016543173112182200
Directory /workspace/74.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random.27272736096583878889713011620992939129650926947892511454226724540955754597656
Short name T1458
Test name
Test status
Simulation time 2231375727 ps
CPU time 83.9 seconds
Started Nov 22 03:10:36 PM PST 23
Finished Nov 22 03:12:00 PM PST 23
Peak memory 553768 kb
Host smart-e502f5df-787b-4b77-afcd-a02dfc6c10d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27272736096583878889713011620992939129650926947892511454226724540955754597656 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 74.xbar_random.27272736096583878889713011620992939129650926947892511454226724540955754597656
Directory /workspace/74.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.14820723362858360159934106244023588589026018677701771769039761535334064005190
Short name T599
Test name
Test status
Simulation time 97702135727 ps
CPU time 1146.97 seconds
Started Nov 22 03:10:33 PM PST 23
Finished Nov 22 03:29:41 PM PST 23
Peak memory 553692 kb
Host smart-dc73c829-67af-42fe-9518-82f260442004
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14820723362858360159934106244023588589026018677701771769039761535334064005190 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.14820723362858360159934106244023588589026018677701771769039761535334064005190
Directory /workspace/74.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.30000041809927494049028779623383569367901670245842037489178593769344463998096
Short name T1850
Test name
Test status
Simulation time 60576345727 ps
CPU time 1098.36 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:28:53 PM PST 23
Peak memory 553700 kb
Host smart-df2749d1-20c5-42de-b6cc-fbb1f54d5278
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000041809927494049028779623383569367901670245842037489178593769344463998096 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.30000041809927494049028779623383569367901670245842037489178593769344463998096
Directory /workspace/74.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.47193872429476743379063818013012662364736890395142575167593380919977206483909
Short name T1824
Test name
Test status
Simulation time 556965727 ps
CPU time 47.42 seconds
Started Nov 22 03:10:41 PM PST 23
Finished Nov 22 03:11:29 PM PST 23
Peak memory 553708 kb
Host smart-3eeb6956-f4e2-46b8-9e33-2db912595b54
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47193872429476743379063818013012662364736890395142575167593380919977206483909 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delays.47193872429476743379063818013012662364736890395142575167593380919977206483909
Directory /workspace/74.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_same_source.40405837955876103387516044982339722620077316872727486293888208648596163089665
Short name T200
Test name
Test status
Simulation time 2498784073 ps
CPU time 77.25 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:11:55 PM PST 23
Peak memory 553716 kb
Host smart-95ae017a-b5b5-4f4d-8e16-ac6c3fdfd1b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40405837955876103387516044982339722620077316872727486293888208648596163089665 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.40405837955876103387516044982339722620077316872727486293888208648596163089665
Directory /workspace/74.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke.103172059936605793661512890294883448723239382902258104733681817199485011872334
Short name T1737
Test name
Test status
Simulation time 196985727 ps
CPU time 8.28 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:10:43 PM PST 23
Peak memory 552340 kb
Host smart-ccb18441-d767-46c4-9249-627befe48e70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103172059936605793661512890294883448723239382902258104733681817199485011872334 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 74.xbar_smoke.103172059936605793661512890294883448723239382902258104733681817199485011872334
Directory /workspace/74.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.5637420518164816391527080557564741842256158576101973756547273002144277317116
Short name T1738
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.5 seconds
Started Nov 22 03:10:31 PM PST 23
Finished Nov 22 03:12:03 PM PST 23
Peak memory 552300 kb
Host smart-8afcd65c-3acd-4e3f-97e7-9d432f4b9a54
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5637420518164816391527080557564741842256158576101973756547273002144277317116 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.5637420518164816391527080557564741842256158576101973756547273002144277317116
Directory /workspace/74.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.53083609689813199209769368456718476974733995207664056169803978367152425207404
Short name T1043
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.06 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:12:03 PM PST 23
Peak memory 552280 kb
Host smart-d39bb739-d036-45f8-a25c-7d565a680241
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53083609689813199209769368456718476974733995207664056169803978367152425207404 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.53083609689813199209769368456718476974733995207664056169803978367152425207404
Directory /workspace/74.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.88776245416141196043144378129109523664513874244824799880840099422510302923854
Short name T1522
Test name
Test status
Simulation time 45555727 ps
CPU time 5.94 seconds
Started Nov 22 03:10:31 PM PST 23
Finished Nov 22 03:10:37 PM PST 23
Peak memory 552276 kb
Host smart-dae2b73b-75ab-43f2-80dd-cfdfed4de4ad
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88776245416141196043144378129109523664513874244824799880840099422510302923854 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays.88776245416141196043144378129109523664513874244824799880840099422510302923854
Directory /workspace/74.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all.20823299020906431953967877243431988922406257463168340091769309047713261047466
Short name T472
Test name
Test status
Simulation time 13992004073 ps
CPU time 559.77 seconds
Started Nov 22 03:10:36 PM PST 23
Finished Nov 22 03:19:57 PM PST 23
Peak memory 555920 kb
Host smart-7466b3fe-f483-4cf5-950b-80e59499a745
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20823299020906431953967877243431988922406257463168340091769309047713261047466 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.20823299020906431953967877243431988922406257463168340091769309047713261047466
Directory /workspace/74.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.52217210985438573400853481944738283747170566192248070661492856413297899651709
Short name T230
Test name
Test status
Simulation time 13999524073 ps
CPU time 484.31 seconds
Started Nov 22 03:10:38 PM PST 23
Finished Nov 22 03:18:43 PM PST 23
Peak memory 555616 kb
Host smart-bf70a2d9-d8a7-4d18-9651-9bfbf3907338
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52217210985438573400853481944738283747170566192248070661492856413297899651709 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.52217210985438573400853481944738283747170566192248070661492856413297899651709
Directory /workspace/74.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.10279137323135216143390741254351764251355816945304937417906571763635407678383
Short name T1789
Test name
Test status
Simulation time 4815189184 ps
CPU time 373.65 seconds
Started Nov 22 03:10:36 PM PST 23
Finished Nov 22 03:16:50 PM PST 23
Peak memory 557216 kb
Host smart-60bdc6b9-15c4-4bf5-b8b1-2b7c47bd325e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279137323135216143390741254351764251355816945304937417906571763635407678383 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_rand_reset.10279137323135216143390741254351764251355816945304937417906571
763635407678383
Directory /workspace/74.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.34520955403158971611382531601684393794426537533141634342904330975963897781016
Short name T1235
Test name
Test status
Simulation time 4815189184 ps
CPU time 316.37 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:15:51 PM PST 23
Peak memory 559692 kb
Host smart-94e5acb5-3b68-4ddb-aee8-2197ab17ea1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34520955403158971611382531601684393794426537533141634342904330975963897781016 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_reset_error.345209554031589716113825316016843937944265375331416343429043
30975963897781016
Directory /workspace/74.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.28905121356157637030945348548006275308317350695896638434673059649762701913432
Short name T1915
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.27 seconds
Started Nov 22 03:10:32 PM PST 23
Finished Nov 22 03:11:21 PM PST 23
Peak memory 553808 kb
Host smart-6a3f1815-a311-4ac8-b6db-0ecda34ff5f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28905121356157637030945348548006275308317350695896638434673059649762701913432 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.28905121356157637030945348548006275308317350695896638434673059649762701913432
Directory /workspace/74.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device.95156759861848735084448091505088519660463152248485858783017589362190671578699
Short name T336
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.77 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:12:27 PM PST 23
Peak memory 554792 kb
Host smart-36239fd5-82ec-4795-bcb1-7c7ab451c951
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95156759861848735084448091505088519660463152248485858783017589362190671578699 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.95156759861848735084448091505088519660463152248485858783017589362190671578699
Directory /workspace/75.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3347541223056431737152867827311646139996160685756337249722306251397258881878
Short name T1807
Test name
Test status
Simulation time 115195295727 ps
CPU time 2026.29 seconds
Started Nov 22 03:10:45 PM PST 23
Finished Nov 22 03:44:32 PM PST 23
Peak memory 554788 kb
Host smart-7ded8337-3102-418a-a22b-39f9fef450f6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347541223056431737152867827311646139996160685756337249722306251397258881878 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device_slow_rsp.3347541223056431737152867827311646139996160685756337249722306251397258881878
Directory /workspace/75.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.48417883154318396812692113082369647385157191314386570692251994610959190948198
Short name T1105
Test name
Test status
Simulation time 1171215727 ps
CPU time 49.52 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:11:45 PM PST 23
Peak memory 553396 kb
Host smart-79f7c514-aed6-4d90-9d0b-29b14850bf50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48417883154318396812692113082369647385157191314386570692251994610959190948198 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr.48417883154318396812692113082369647385157191314386570692251994610959190948198
Directory /workspace/75.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_random.40672293268682547064102817573658976535490156713990175284294656119782627496046
Short name T489
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.98 seconds
Started Nov 22 03:10:36 PM PST 23
Finished Nov 22 03:11:48 PM PST 23
Peak memory 553516 kb
Host smart-ca056ac8-6b49-4e8b-b1c6-9bd18005d615
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672293268682547064102817573658976535490156713990175284294656119782627496046 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 75.xbar_error_random.40672293268682547064102817573658976535490156713990175284294656119782627496046
Directory /workspace/75.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random.78791329651578375457142022196535046531159810318308307660508366051938395547611
Short name T1357
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.46 seconds
Started Nov 22 03:10:34 PM PST 23
Finished Nov 22 03:11:50 PM PST 23
Peak memory 553760 kb
Host smart-455cecb0-c09b-4ff9-9c27-c84d7d878598
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78791329651578375457142022196535046531159810318308307660508366051938395547611 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 75.xbar_random.78791329651578375457142022196535046531159810318308307660508366051938395547611
Directory /workspace/75.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.58267623509075561849558701977690066416520778543592945881003197840437941084172
Short name T1624
Test name
Test status
Simulation time 97702135727 ps
CPU time 1151.11 seconds
Started Nov 22 03:10:41 PM PST 23
Finished Nov 22 03:29:53 PM PST 23
Peak memory 553640 kb
Host smart-4da2e8af-6391-4bc0-b000-2cfff7f96773
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58267623509075561849558701977690066416520778543592945881003197840437941084172 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.58267623509075561849558701977690066416520778543592945881003197840437941084172
Directory /workspace/75.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.72471774894037162659440837134736833297501999973534677578032930433660101500398
Short name T205
Test name
Test status
Simulation time 60576345727 ps
CPU time 1097.29 seconds
Started Nov 22 03:10:42 PM PST 23
Finished Nov 22 03:29:01 PM PST 23
Peak memory 553592 kb
Host smart-8e8f0c52-1711-4dba-9c7f-879d499f3d58
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72471774894037162659440837134736833297501999973534677578032930433660101500398 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.72471774894037162659440837134736833297501999973534677578032930433660101500398
Directory /workspace/75.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.73653605252833828911724226412302547307282971188506867636931087922254218533834
Short name T866
Test name
Test status
Simulation time 556965727 ps
CPU time 53.09 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:11:49 PM PST 23
Peak memory 553616 kb
Host smart-e6600eee-8e21-4446-8515-26523184009c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73653605252833828911724226412302547307282971188506867636931087922254218533834 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_delays.73653605252833828911724226412302547307282971188506867636931087922254218533834
Directory /workspace/75.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_same_source.109605523653492239414950419436183277027938229571160322391246475019950380060875
Short name T1324
Test name
Test status
Simulation time 2498784073 ps
CPU time 81.21 seconds
Started Nov 22 03:10:51 PM PST 23
Finished Nov 22 03:12:14 PM PST 23
Peak memory 553736 kb
Host smart-61c9413b-8595-4437-b53d-0775a20e90a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109605523653492239414950419436183277027938229571160322391246475019950380060875 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.109605523653492239414950419436183277027938229571160322391246475019950380060875
Directory /workspace/75.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke.15381622203686125899952779275678602810673139865966945718323240289856676114663
Short name T1547
Test name
Test status
Simulation time 196985727 ps
CPU time 8.35 seconds
Started Nov 22 03:10:36 PM PST 23
Finished Nov 22 03:10:45 PM PST 23
Peak memory 552356 kb
Host smart-72515761-8323-4c2c-8e1f-32c5395e493c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15381622203686125899952779275678602810673139865966945718323240289856676114663 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 75.xbar_smoke.15381622203686125899952779275678602810673139865966945718323240289856676114663
Directory /workspace/75.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.3392437565830535207156352490221835200374112554854651946008377578338086237850
Short name T1009
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.4 seconds
Started Nov 22 03:10:31 PM PST 23
Finished Nov 22 03:12:00 PM PST 23
Peak memory 552388 kb
Host smart-696a97c1-c9ef-4b4a-840c-cf53b64736d0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392437565830535207156352490221835200374112554854651946008377578338086237850 -assert nopost
proc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.3392437565830535207156352490221835200374112554854651946008377578338086237850
Directory /workspace/75.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.77942405680566385627630490811068649478072469077963567249046431224610480511860
Short name T1581
Test name
Test status
Simulation time 4856075727 ps
CPU time 91.08 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:12:09 PM PST 23
Peak memory 552376 kb
Host smart-478ca8a8-cc76-4fb3-bd8b-7ad08b9c94de
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77942405680566385627630490811068649478072469077963567249046431224610480511860 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.77942405680566385627630490811068649478072469077963567249046431224610480511860
Directory /workspace/75.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.27426454197915256242158898044285979587150113052055561470670439792816300358273
Short name T139
Test name
Test status
Simulation time 45555727 ps
CPU time 6.21 seconds
Started Nov 22 03:10:33 PM PST 23
Finished Nov 22 03:10:40 PM PST 23
Peak memory 552280 kb
Host smart-5609158f-10a5-48c6-ad85-2c7b3933d3f6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27426454197915256242158898044285979587150113052055561470670439792816300358273 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.27426454197915256242158898044285979587150113052055561470670439792816300358273
Directory /workspace/75.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all.51659858781358322632979387950996785000747585903189320218987164232918546543592
Short name T1012
Test name
Test status
Simulation time 13992004073 ps
CPU time 537.87 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:19:36 PM PST 23
Peak memory 555880 kb
Host smart-e631e63d-f36a-4d61-a54a-8bb2ff2935a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51659858781358322632979387950996785000747585903189320218987164232918546543592 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.51659858781358322632979387950996785000747585903189320218987164232918546543592
Directory /workspace/75.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.59682291857072122289882350004081188119371836655481310697310318122813156041969
Short name T1150
Test name
Test status
Simulation time 13999524073 ps
CPU time 461.41 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:18:41 PM PST 23
Peak memory 555636 kb
Host smart-319e7c28-145e-4441-ac80-726ae2881491
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59682291857072122289882350004081188119371836655481310697310318122813156041969 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.59682291857072122289882350004081188119371836655481310697310318122813156041969
Directory /workspace/75.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.88538108289671319976563349328448899442326374204534432812436218430375820112187
Short name T359
Test name
Test status
Simulation time 4815189184 ps
CPU time 365.98 seconds
Started Nov 22 03:10:38 PM PST 23
Finished Nov 22 03:16:45 PM PST 23
Peak memory 557220 kb
Host smart-b4390d08-be59-4391-9f44-b486e97eb483
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88538108289671319976563349328448899442326374204534432812436218430375820112187 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_rand_reset.88538108289671319976563349328448899442326374204534432812436218
430375820112187
Directory /workspace/75.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.51643502682066745782527165809862723190869877606762952885202360702127440257085
Short name T500
Test name
Test status
Simulation time 4815189184 ps
CPU time 300.95 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:15:46 PM PST 23
Peak memory 559708 kb
Host smart-c761e348-72aa-4e39-b9d3-299ed6fb7b86
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51643502682066745782527165809862723190869877606762952885202360702127440257085 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_reset_error.516435026820667457825271658098627231908698776067629528852023
60702127440257085
Directory /workspace/75.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.72342379535191207192155295348438173753207021096612730927388493694214530629167
Short name T826
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.54 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:11:32 PM PST 23
Peak memory 553712 kb
Host smart-3412f562-97c7-4219-b85d-b3e1234d7333
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72342379535191207192155295348438173753207021096612730927388493694214530629167 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.72342379535191207192155295348438173753207021096612730927388493694214530629167
Directory /workspace/75.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device.67730220930541299413077930321932907272445559905986047179636999729003638471747
Short name T600
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.69 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:12:44 PM PST 23
Peak memory 554708 kb
Host smart-3ce02482-332f-41d0-a3de-31fc621aa848
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67730220930541299413077930321932907272445559905986047179636999729003638471747 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device.67730220930541299413077930321932907272445559905986047179636999729003638471747
Directory /workspace/76.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.75545271051859519238974008974821010266032805056180270626746760998453918861026
Short name T208
Test name
Test status
Simulation time 115195295727 ps
CPU time 1936.96 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:43:13 PM PST 23
Peak memory 554684 kb
Host smart-e7a22ee8-e989-4313-aee4-9d20d58faef0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75545271051859519238974008974821010266032805056180270626746760998453918861026 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device_slow_rsp.75545271051859519238974008974821010266032805056180270626746760998453918861026
Directory /workspace/76.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.82207464927339134334168469476044235809972992410287528127211466529169423832944
Short name T1439
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.01 seconds
Started Nov 22 03:10:46 PM PST 23
Finished Nov 22 03:11:33 PM PST 23
Peak memory 553600 kb
Host smart-660c4394-1073-4e79-be41-c376113ce9a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82207464927339134334168469476044235809972992410287528127211466529169423832944 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr.82207464927339134334168469476044235809972992410287528127211466529169423832944
Directory /workspace/76.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_random.43773245581639169920946539011436944374413354986989560034376792393676618714454
Short name T429
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.31 seconds
Started Nov 22 03:10:53 PM PST 23
Finished Nov 22 03:12:14 PM PST 23
Peak memory 553440 kb
Host smart-90bef498-b5f9-44ce-a218-20ae013f47d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43773245581639169920946539011436944374413354986989560034376792393676618714454 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 76.xbar_error_random.43773245581639169920946539011436944374413354986989560034376792393676618714454
Directory /workspace/76.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random.82168412059522118604603547512458025005207192018591483777891060878880987564926
Short name T1501
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.48 seconds
Started Nov 22 03:10:38 PM PST 23
Finished Nov 22 03:11:57 PM PST 23
Peak memory 553748 kb
Host smart-fcb78d95-f883-4df8-b0db-193927ff4e03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82168412059522118604603547512458025005207192018591483777891060878880987564926 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 76.xbar_random.82168412059522118604603547512458025005207192018591483777891060878880987564926
Directory /workspace/76.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.94857514696522048002438233168739318761420763280716279325264640692853037071086
Short name T1594
Test name
Test status
Simulation time 97702135727 ps
CPU time 1147.48 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:29:53 PM PST 23
Peak memory 553664 kb
Host smart-5c697c9e-80ea-42f2-a4c9-9554985dcac1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94857514696522048002438233168739318761420763280716279325264640692853037071086 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.94857514696522048002438233168739318761420763280716279325264640692853037071086
Directory /workspace/76.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.8049825039029500178855311489976367439334711135163665631794278380537482360183
Short name T191
Test name
Test status
Simulation time 60576345727 ps
CPU time 1135.07 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:29:33 PM PST 23
Peak memory 553704 kb
Host smart-01a1a8b1-1c93-4c28-bdac-7cc2478eb4ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8049825039029500178855311489976367439334711135163665631794278380537482360183 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.8049825039029500178855311489976367439334711135163665631794278380537482360183
Directory /workspace/76.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.101444860847553122592603244398849837779944750819067152003738908196774373594679
Short name T1531
Test name
Test status
Simulation time 556965727 ps
CPU time 46.33 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:11:24 PM PST 23
Peak memory 553808 kb
Host smart-3c3d0858-1f2c-49c6-95f5-d500e0a16740
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101444860847553122592603244398849837779944750819067152003738908196774373594679 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_delays.101444860847553122592603244398849837779944750819067152003738908196774373594679
Directory /workspace/76.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_same_source.15900812967679858069067220181591820991754136341820010421358398328624817933661
Short name T671
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.69 seconds
Started Nov 22 03:10:36 PM PST 23
Finished Nov 22 03:11:52 PM PST 23
Peak memory 553716 kb
Host smart-8f387dab-e6b1-40fd-b001-732b1cf42f50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900812967679858069067220181591820991754136341820010421358398328624817933661 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.15900812967679858069067220181591820991754136341820010421358398328624817933661
Directory /workspace/76.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke.30577334744341661110197718607441811773421586269295561267159225095223715365778
Short name T1646
Test name
Test status
Simulation time 196985727 ps
CPU time 8.24 seconds
Started Nov 22 03:10:38 PM PST 23
Finished Nov 22 03:10:47 PM PST 23
Peak memory 552356 kb
Host smart-3dbc61c0-1990-40ac-bf5d-0d6b8435aa87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577334744341661110197718607441811773421586269295561267159225095223715365778 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 76.xbar_smoke.30577334744341661110197718607441811773421586269295561267159225095223715365778
Directory /workspace/76.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.31066172525800983410506227113564814076099169317404848198848956647889532365285
Short name T1410
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.64 seconds
Started Nov 22 03:10:41 PM PST 23
Finished Nov 22 03:12:10 PM PST 23
Peak memory 552320 kb
Host smart-a2b612d9-25d8-4806-8048-e6963625a966
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066172525800983410506227113564814076099169317404848198848956647889532365285 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.31066172525800983410506227113564814076099169317404848198848956647889532365285
Directory /workspace/76.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.111764804982657072245306782823665805465184554159244783379339672149809160428696
Short name T703
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.79 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:12:22 PM PST 23
Peak memory 552296 kb
Host smart-152359e1-25db-4638-9b58-67a12c570030
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111764804982657072245306782823665805465184554159244783379339672149809160428696 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.111764804982657072245306782823665805465184554159244783379339672149809160428696
Directory /workspace/76.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.78830825468559954343329770547687196001783751852410190781161168473726513402258
Short name T1592
Test name
Test status
Simulation time 45555727 ps
CPU time 5.93 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:10:43 PM PST 23
Peak memory 552372 kb
Host smart-cb7a0117-64ac-4c17-9574-ed15cd2afa86
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78830825468559954343329770547687196001783751852410190781161168473726513402258 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.78830825468559954343329770547687196001783751852410190781161168473726513402258
Directory /workspace/76.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all.97305616873048968099336947874598951048180484002007068584456490320955824327486
Short name T524
Test name
Test status
Simulation time 13992004073 ps
CPU time 550.67 seconds
Started Nov 22 03:10:52 PM PST 23
Finished Nov 22 03:20:04 PM PST 23
Peak memory 555908 kb
Host smart-ec30b141-2767-4f94-8789-2f60908d29aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97305616873048968099336947874598951048180484002007068584456490320955824327486 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.97305616873048968099336947874598951048180484002007068584456490320955824327486
Directory /workspace/76.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.60688915273773744286076733538610106737429134314259902823905191320336188177853
Short name T1268
Test name
Test status
Simulation time 13999524073 ps
CPU time 512.69 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:19:17 PM PST 23
Peak memory 555664 kb
Host smart-bdea4f7b-fcbc-4a40-b6a5-d8b1da53f8fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60688915273773744286076733538610106737429134314259902823905191320336188177853 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.60688915273773744286076733538610106737429134314259902823905191320336188177853
Directory /workspace/76.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.9338550203731403131828313873446347278557231229138641060440165216511620930220
Short name T126
Test name
Test status
Simulation time 4815189184 ps
CPU time 359.11 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:16:44 PM PST 23
Peak memory 557208 kb
Host smart-979b7be7-67b0-4345-b1a0-4d686f367a9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9338550203731403131828313873446347278557231229138641060440165216511620930220 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_rand_reset.933855020373140313182831387344634727855723122913864106044016521
6511620930220
Directory /workspace/76.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.88752380426436154461562457660170636001361717960450727218901591176193303133459
Short name T1524
Test name
Test status
Simulation time 4815189184 ps
CPU time 323.19 seconds
Started Nov 22 03:10:45 PM PST 23
Finished Nov 22 03:16:09 PM PST 23
Peak memory 559680 kb
Host smart-68fb334c-93be-4877-82ff-29bf10be5bf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88752380426436154461562457660170636001361717960450727218901591176193303133459 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_reset_error.887523804264361544615624576601706360013617179604507272189015
91176193303133459
Directory /workspace/76.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.81728192259154506456280375820403752114696406586049456138878824438874851054224
Short name T1778
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.92 seconds
Started Nov 22 03:10:37 PM PST 23
Finished Nov 22 03:11:28 PM PST 23
Peak memory 553732 kb
Host smart-30cabecf-a16c-4b6d-81dd-0e706b959d48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81728192259154506456280375820403752114696406586049456138878824438874851054224 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.81728192259154506456280375820403752114696406586049456138878824438874851054224
Directory /workspace/76.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device.25358280053022740658996050410809115088906921670741140057939528582595514495491
Short name T1313
Test name
Test status
Simulation time 2590995727 ps
CPU time 104.63 seconds
Started Nov 22 03:10:43 PM PST 23
Finished Nov 22 03:12:28 PM PST 23
Peak memory 554820 kb
Host smart-ddbedb8c-a1e8-49ee-810e-91ce17e0fa13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25358280053022740658996050410809115088906921670741140057939528582595514495491 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device.25358280053022740658996050410809115088906921670741140057939528582595514495491
Directory /workspace/77.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.55789985047021645587970821428304343732845203048894663919791341210292954704082
Short name T311
Test name
Test status
Simulation time 115195295727 ps
CPU time 2069.11 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:45:30 PM PST 23
Peak memory 554796 kb
Host smart-adaa4397-773b-4eeb-a4f6-dbcb9fb21fa8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55789985047021645587970821428304343732845203048894663919791341210292954704082 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device_slow_rsp.55789985047021645587970821428304343732845203048894663919791341210292954704082
Directory /workspace/77.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.31763633485052782803084024232197599159546067946942067159076264901543120844588
Short name T1149
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.14 seconds
Started Nov 22 03:10:56 PM PST 23
Finished Nov 22 03:11:48 PM PST 23
Peak memory 553492 kb
Host smart-31cdd121-ede1-4dbf-8445-ef858d58e62f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31763633485052782803084024232197599159546067946942067159076264901543120844588 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.31763633485052782803084024232197599159546067946942067159076264901543120844588
Directory /workspace/77.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_random.33883211170199315037448721333835521850464852785081673107312731074686510088690
Short name T1788
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.58 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:12:13 PM PST 23
Peak memory 553620 kb
Host smart-e24433b8-b271-497c-98a6-e347ae777898
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33883211170199315037448721333835521850464852785081673107312731074686510088690 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 77.xbar_error_random.33883211170199315037448721333835521850464852785081673107312731074686510088690
Directory /workspace/77.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random.37877053405612932676441676644980601822775050203293831248310058450885438959248
Short name T1521
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.67 seconds
Started Nov 22 03:10:43 PM PST 23
Finished Nov 22 03:12:04 PM PST 23
Peak memory 553664 kb
Host smart-afc35648-9157-4658-b010-7ee56dc7a47e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37877053405612932676441676644980601822775050203293831248310058450885438959248 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 77.xbar_random.37877053405612932676441676644980601822775050203293831248310058450885438959248
Directory /workspace/77.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.83057830168003396859822408039873447147304625913270160814370792959193477478907
Short name T698
Test name
Test status
Simulation time 97702135727 ps
CPU time 1149.93 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:29:55 PM PST 23
Peak memory 553664 kb
Host smart-81c7ade5-d2e5-4bec-a712-9ecc19e3ac8e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83057830168003396859822408039873447147304625913270160814370792959193477478907 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.83057830168003396859822408039873447147304625913270160814370792959193477478907
Directory /workspace/77.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.29853778325000693546968578771539586941926332422337107509195863683792904842014
Short name T902
Test name
Test status
Simulation time 60576345727 ps
CPU time 1124.54 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:29:29 PM PST 23
Peak memory 553768 kb
Host smart-2b8fa68b-1fed-4c94-8401-1d24d612577a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29853778325000693546968578771539586941926332422337107509195863683792904842014 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.29853778325000693546968578771539586941926332422337107509195863683792904842014
Directory /workspace/77.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.104938352516134590517647852678551317638528663539945134556762398237037921490639
Short name T435
Test name
Test status
Simulation time 556965727 ps
CPU time 49.98 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:11:35 PM PST 23
Peak memory 553688 kb
Host smart-ea6734e2-4335-4a1f-a9ef-09f52a3e94c4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104938352516134590517647852678551317638528663539945134556762398237037921490639 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_delays.104938352516134590517647852678551317638528663539945134556762398237037921490639
Directory /workspace/77.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_same_source.15673753528658262822870723097252125853491727038962236830049105029486580483064
Short name T1374
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.41 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:12:12 PM PST 23
Peak memory 553700 kb
Host smart-0822d955-f253-4dca-973d-6c3e0044bb3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673753528658262822870723097252125853491727038962236830049105029486580483064 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.15673753528658262822870723097252125853491727038962236830049105029486580483064
Directory /workspace/77.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke.9651980841719575782415320623890385127141001663097190932770062382664324877303
Short name T1839
Test name
Test status
Simulation time 196985727 ps
CPU time 8.82 seconds
Started Nov 22 03:10:43 PM PST 23
Finished Nov 22 03:10:53 PM PST 23
Peak memory 552348 kb
Host smart-e76dcd24-3e89-4817-b088-e6e2b6dd59f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9651980841719575782415320623890385127141001663097190932770062382664324877303 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 77.xbar_smoke.9651980841719575782415320623890385127141001663097190932770062382664324877303
Directory /workspace/77.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.25079182650084387484168486686047900593332242789200336382587942695885189123279
Short name T715
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.24 seconds
Started Nov 22 03:10:46 PM PST 23
Finished Nov 22 03:12:17 PM PST 23
Peak memory 552384 kb
Host smart-1f39a491-d823-4227-8272-33167c288790
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25079182650084387484168486686047900593332242789200336382587942695885189123279 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.25079182650084387484168486686047900593332242789200336382587942695885189123279
Directory /workspace/77.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.62635289400826322320650452106071031233708278535406792534444435000693468806609
Short name T1804
Test name
Test status
Simulation time 4856075727 ps
CPU time 92.19 seconds
Started Nov 22 03:10:49 PM PST 23
Finished Nov 22 03:12:22 PM PST 23
Peak memory 552344 kb
Host smart-5b28eedf-aefa-4de1-a7c7-acd500350e24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62635289400826322320650452106071031233708278535406792534444435000693468806609 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.62635289400826322320650452106071031233708278535406792534444435000693468806609
Directory /workspace/77.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.64998222810554362048803916697752762058296325542866353902282279785460125687796
Short name T1202
Test name
Test status
Simulation time 45555727 ps
CPU time 6.01 seconds
Started Nov 22 03:10:44 PM PST 23
Finished Nov 22 03:10:50 PM PST 23
Peak memory 552452 kb
Host smart-1eada583-306d-4233-a776-5cabe2e4d183
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64998222810554362048803916697752762058296325542866353902282279785460125687796 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays.64998222810554362048803916697752762058296325542866353902282279785460125687796
Directory /workspace/77.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all.44970096371577270374991139184431236168669271590907434076394299416830216079868
Short name T172
Test name
Test status
Simulation time 13992004073 ps
CPU time 518.16 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:19:34 PM PST 23
Peak memory 555856 kb
Host smart-46dc2e55-1781-4a20-84cf-2a5c8b06f93d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44970096371577270374991139184431236168669271590907434076394299416830216079868 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.44970096371577270374991139184431236168669271590907434076394299416830216079868
Directory /workspace/77.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.396592478770596381672826020026729175399688050039132972695352560242600679970
Short name T1383
Test name
Test status
Simulation time 13999524073 ps
CPU time 530.18 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:19:50 PM PST 23
Peak memory 555664 kb
Host smart-1d0af0fb-e221-4b8f-9f28-1054ba551e87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396592478770596381672826020026729175399688050039132972695352560242600679970 -assert nopostproc +UVM_T
ESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.396592478770596381672826020026729175399688050039132972695352560242600679970
Directory /workspace/77.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.51414521862112061690841810098845610683901799283536977551788341942407934819617
Short name T1490
Test name
Test status
Simulation time 4815189184 ps
CPU time 359.17 seconds
Started Nov 22 03:10:56 PM PST 23
Finished Nov 22 03:17:00 PM PST 23
Peak memory 557124 kb
Host smart-8725fe39-4c5d-4622-84ed-5ae9879a9097
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51414521862112061690841810098845610683901799283536977551788341942407934819617 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_rand_reset.51414521862112061690841810098845610683901799283536977551788341
942407934819617
Directory /workspace/77.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.68912111517023082025758750121730205972495784919526094802572995640723506312454
Short name T1832
Test name
Test status
Simulation time 4815189184 ps
CPU time 298.92 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:15:55 PM PST 23
Peak memory 559660 kb
Host smart-bb83e4df-6faa-43f8-9e8b-d9db0ddcf806
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68912111517023082025758750121730205972495784919526094802572995640723506312454 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_reset_error.689121115170230820257587501217302059724957849195260948025729
95640723506312454
Directory /workspace/77.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.12893806769708178593880338404755908453459223986351825865187856754300353963923
Short name T647
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.23 seconds
Started Nov 22 03:11:02 PM PST 23
Finished Nov 22 03:11:53 PM PST 23
Peak memory 553656 kb
Host smart-a2bc0077-2a65-4782-b221-921bc470dc2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12893806769708178593880338404755908453459223986351825865187856754300353963923 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.12893806769708178593880338404755908453459223986351825865187856754300353963923
Directory /workspace/77.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device.82995693082252902192902133251573511638287685308136706832814530268103941541880
Short name T1654
Test name
Test status
Simulation time 2590995727 ps
CPU time 112.52 seconds
Started Nov 22 03:10:58 PM PST 23
Finished Nov 22 03:12:54 PM PST 23
Peak memory 554780 kb
Host smart-888e6b4e-5ea5-45fa-bafb-c4ad6658a595
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82995693082252902192902133251573511638287685308136706832814530268103941541880 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device.82995693082252902192902133251573511638287685308136706832814530268103941541880
Directory /workspace/78.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.80123497813779115298527675344058720757833611219801451516840879444170695706218
Short name T469
Test name
Test status
Simulation time 115195295727 ps
CPU time 2018.76 seconds
Started Nov 22 03:10:56 PM PST 23
Finished Nov 22 03:44:41 PM PST 23
Peak memory 554792 kb
Host smart-35204b49-beb6-4dcf-ad94-9b6f75301709
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80123497813779115298527675344058720757833611219801451516840879444170695706218 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device_slow_rsp.80123497813779115298527675344058720757833611219801451516840879444170695706218
Directory /workspace/78.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.99574704927607689448756373362241559387068774093496681660260768244512665332321
Short name T670
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.29 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:11:42 PM PST 23
Peak memory 553472 kb
Host smart-10679a2c-be8f-413f-859e-d55f16956230
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99574704927607689448756373362241559387068774093496681660260768244512665332321 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.99574704927607689448756373362241559387068774093496681660260768244512665332321
Directory /workspace/78.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_random.99581172889075299352949116927625271440068493875176423190159486210322761292749
Short name T1711
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.89 seconds
Started Nov 22 03:10:57 PM PST 23
Finished Nov 22 03:12:15 PM PST 23
Peak memory 553496 kb
Host smart-3daea007-ff24-4dc3-bc97-9539a02a36b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99581172889075299352949116927625271440068493875176423190159486210322761292749 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 78.xbar_error_random.99581172889075299352949116927625271440068493875176423190159486210322761292749
Directory /workspace/78.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random.89234903700956213823126216541448371992480621879965911551586649663221387012337
Short name T262
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.62 seconds
Started Nov 22 03:10:57 PM PST 23
Finished Nov 22 03:12:23 PM PST 23
Peak memory 553756 kb
Host smart-f7fdca21-b0eb-4ce9-9116-e32735bbc471
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89234903700956213823126216541448371992480621879965911551586649663221387012337 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 78.xbar_random.89234903700956213823126216541448371992480621879965911551586649663221387012337
Directory /workspace/78.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.111218508519948092307748870438108214541205517552682252550985602857375336658944
Short name T1715
Test name
Test status
Simulation time 97702135727 ps
CPU time 1152.87 seconds
Started Nov 22 03:11:02 PM PST 23
Finished Nov 22 03:30:19 PM PST 23
Peak memory 553616 kb
Host smart-45c56eb8-3847-4f13-aec6-96dcc5b5e229
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111218508519948092307748870438108214541205517552682252550985602857375336658944 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.111218508519948092307748870438108214541205517552682252550985602857375336658944
Directory /workspace/78.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.103926383131502407537485563371801474830279489622163553413731182907655745809759
Short name T112
Test name
Test status
Simulation time 60576345727 ps
CPU time 1080.01 seconds
Started Nov 22 03:10:56 PM PST 23
Finished Nov 22 03:29:02 PM PST 23
Peak memory 553668 kb
Host smart-fc51dcf3-b704-4086-a36f-e0dcf1a5a66a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103926383131502407537485563371801474830279489622163553413731182907655745809759 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.103926383131502407537485563371801474830279489622163553413731182907655745809759
Directory /workspace/78.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.57373214230330075197445523959143526612912870184012290836546008634754908436929
Short name T1271
Test name
Test status
Simulation time 556965727 ps
CPU time 48.43 seconds
Started Nov 22 03:10:53 PM PST 23
Finished Nov 22 03:11:44 PM PST 23
Peak memory 553652 kb
Host smart-fd0d1479-9d81-42ff-a87b-f633c35031ad
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57373214230330075197445523959143526612912870184012290836546008634754908436929 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_delays.57373214230330075197445523959143526612912870184012290836546008634754908436929
Directory /workspace/78.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_same_source.95860260138046258560405728927199928357586195005650665322092141539050964194804
Short name T1052
Test name
Test status
Simulation time 2498784073 ps
CPU time 77.38 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:12:17 PM PST 23
Peak memory 553700 kb
Host smart-69bd1ddd-29b1-4101-a72e-c2187f6e6cf9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95860260138046258560405728927199928357586195005650665322092141539050964194804 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.95860260138046258560405728927199928357586195005650665322092141539050964194804
Directory /workspace/78.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke.82085731013181883756033814943529219882408590426727240282097712055184468304232
Short name T144
Test name
Test status
Simulation time 196985727 ps
CPU time 9.17 seconds
Started Nov 22 03:10:56 PM PST 23
Finished Nov 22 03:11:11 PM PST 23
Peak memory 552280 kb
Host smart-03e26fe4-4f88-47b2-8f3f-75d82e69338d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82085731013181883756033814943529219882408590426727240282097712055184468304232 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 78.xbar_smoke.82085731013181883756033814943529219882408590426727240282097712055184468304232
Directory /workspace/78.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.41961430378972323274530257624035514130174429631490620306399126613696124906077
Short name T458
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.15 seconds
Started Nov 22 03:10:58 PM PST 23
Finished Nov 22 03:12:34 PM PST 23
Peak memory 552368 kb
Host smart-3b38e59f-33c3-4a1b-9d77-78875d1b9978
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41961430378972323274530257624035514130174429631490620306399126613696124906077 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.41961430378972323274530257624035514130174429631490620306399126613696124906077
Directory /workspace/78.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.91295511873436268816376727282570757176975926286010935956080503644270841931166
Short name T1702
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.52 seconds
Started Nov 22 03:10:54 PM PST 23
Finished Nov 22 03:12:26 PM PST 23
Peak memory 552324 kb
Host smart-954672ea-b1d5-430c-8802-ee7e6638e27e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91295511873436268816376727282570757176975926286010935956080503644270841931166 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.91295511873436268816376727282570757176975926286010935956080503644270841931166
Directory /workspace/78.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.65164699121158441639561430356804594992549630365086673635293588603810197849880
Short name T891
Test name
Test status
Simulation time 45555727 ps
CPU time 6.05 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:11:06 PM PST 23
Peak memory 552360 kb
Host smart-561b9a40-4cfd-4d75-ae82-4b052e788b76
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65164699121158441639561430356804594992549630365086673635293588603810197849880 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays.65164699121158441639561430356804594992549630365086673635293588603810197849880
Directory /workspace/78.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all.70530259530728698059975603538158057785748287303260259995157024829922840816774
Short name T1662
Test name
Test status
Simulation time 13992004073 ps
CPU time 522.55 seconds
Started Nov 22 03:10:59 PM PST 23
Finished Nov 22 03:19:44 PM PST 23
Peak memory 555884 kb
Host smart-7e7f20e2-c19e-445d-b482-77ed7ad14c2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70530259530728698059975603538158057785748287303260259995157024829922840816774 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.70530259530728698059975603538158057785748287303260259995157024829922840816774
Directory /workspace/78.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.108606237484592142411340285114716578918506435850486077576073331324881783856773
Short name T224
Test name
Test status
Simulation time 13999524073 ps
CPU time 469.46 seconds
Started Nov 22 03:11:05 PM PST 23
Finished Nov 22 03:18:57 PM PST 23
Peak memory 555668 kb
Host smart-9adc10b6-4ae6-41b8-b80a-501901a09009
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108606237484592142411340285114716578918506435850486077576073331324881783856773 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.108606237484592142411340285114716578918506435850486077576073331324881783856773
Directory /workspace/78.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.95608809894124533029502468440021382810990726831931510330818879964315424157143
Short name T1266
Test name
Test status
Simulation time 4815189184 ps
CPU time 364.27 seconds
Started Nov 22 03:10:57 PM PST 23
Finished Nov 22 03:17:06 PM PST 23
Peak memory 557276 kb
Host smart-4ae0d990-4bf1-4dce-a012-3ac914a930c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95608809894124533029502468440021382810990726831931510330818879964315424157143 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_rand_reset.95608809894124533029502468440021382810990726831931510330818879
964315424157143
Directory /workspace/78.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.77139249438534222670067886040854455873662112770116261400235504450732849803282
Short name T181
Test name
Test status
Simulation time 4815189184 ps
CPU time 318.1 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:16:19 PM PST 23
Peak memory 559732 kb
Host smart-bcc2aecb-83cb-4fdf-9217-48a7aa9fdafa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77139249438534222670067886040854455873662112770116261400235504450732849803282 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_reset_error.771392494385342226700678860408544558736621127701162614002355
04450732849803282
Directory /workspace/78.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.71653245844282720206652132012249539617611941488567481483828618629275231746620
Short name T1533
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.76 seconds
Started Nov 22 03:10:58 PM PST 23
Finished Nov 22 03:11:49 PM PST 23
Peak memory 553588 kb
Host smart-2b954129-5269-4e61-b3d1-588d100f96ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71653245844282720206652132012249539617611941488567481483828618629275231746620 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.71653245844282720206652132012249539617611941488567481483828618629275231746620
Directory /workspace/78.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device.59231335451028723602617143170005024352782147020281780404481009745461118779730
Short name T756
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.31 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:12:47 PM PST 23
Peak memory 554884 kb
Host smart-cd0e99c3-861e-43ef-b19f-332b645ae226
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59231335451028723602617143170005024352782147020281780404481009745461118779730 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device.59231335451028723602617143170005024352782147020281780404481009745461118779730
Directory /workspace/79.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.63758645090890869442769744662915984736699991246531344484334343018456009750304
Short name T426
Test name
Test status
Simulation time 115195295727 ps
CPU time 2086.37 seconds
Started Nov 22 03:11:03 PM PST 23
Finished Nov 22 03:45:53 PM PST 23
Peak memory 554736 kb
Host smart-efcfc9bf-8346-4a21-80ae-08de75839b55
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63758645090890869442769744662915984736699991246531344484334343018456009750304 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device_slow_rsp.63758645090890869442769744662915984736699991246531344484334343018456009750304
Directory /workspace/79.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3873555167518474124459302308886571038576726621802410837428893347839663123510
Short name T91
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.03 seconds
Started Nov 22 03:11:08 PM PST 23
Finished Nov 22 03:11:54 PM PST 23
Peak memory 553464 kb
Host smart-ff6759c4-c20e-443c-b6f4-ba1c03ad65bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873555167518474124459302308886571038576726621802410837428893347839663123510 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr.3873555167518474124459302308886571038576726621802410837428893347839663123510
Directory /workspace/79.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_random.34207441895264437240250130068588734809065319243959471178564581790299349721425
Short name T196
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.65 seconds
Started Nov 22 03:11:11 PM PST 23
Finished Nov 22 03:12:25 PM PST 23
Peak memory 553496 kb
Host smart-eae77c29-6d08-4d12-a018-aa020e1cd566
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34207441895264437240250130068588734809065319243959471178564581790299349721425 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 79.xbar_error_random.34207441895264437240250130068588734809065319243959471178564581790299349721425
Directory /workspace/79.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random.95030419404880114928915875909462661156953668899038806613019305260884679085867
Short name T606
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.71 seconds
Started Nov 22 03:10:56 PM PST 23
Finished Nov 22 03:12:23 PM PST 23
Peak memory 553752 kb
Host smart-d37c01f2-f8b7-4a63-b7fe-0017a6621ee3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95030419404880114928915875909462661156953668899038806613019305260884679085867 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 79.xbar_random.95030419404880114928915875909462661156953668899038806613019305260884679085867
Directory /workspace/79.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.110194788441057384186129952802335357252964290762569947625562264617334412747106
Short name T184
Test name
Test status
Simulation time 97702135727 ps
CPU time 1180.66 seconds
Started Nov 22 03:10:57 PM PST 23
Finished Nov 22 03:30:42 PM PST 23
Peak memory 553688 kb
Host smart-ec91c8f5-b188-42f2-b0be-c4c8c9ee95ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110194788441057384186129952802335357252964290762569947625562264617334412747106 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.110194788441057384186129952802335357252964290762569947625562264617334412747106
Directory /workspace/79.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.53098453166828189663037191394261260152148774040959203375105387033385660673959
Short name T732
Test name
Test status
Simulation time 60576345727 ps
CPU time 1089.66 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:29:10 PM PST 23
Peak memory 553728 kb
Host smart-6827f7ba-4519-4cad-a20c-bb1f163200a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53098453166828189663037191394261260152148774040959203375105387033385660673959 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.53098453166828189663037191394261260152148774040959203375105387033385660673959
Directory /workspace/79.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.5256813257151192864375596457707920262853424822039949169410581569861403805089
Short name T721
Test name
Test status
Simulation time 556965727 ps
CPU time 43.49 seconds
Started Nov 22 03:10:55 PM PST 23
Finished Nov 22 03:11:44 PM PST 23
Peak memory 553712 kb
Host smart-7776b514-b031-4442-aa25-087f567f7659
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5256813257151192864375596457707920262853424822039949169410581569861403805089 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delays.5256813257151192864375596457707920262853424822039949169410581569861403805089
Directory /workspace/79.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_same_source.24380244430454436744814423710397885257683153342159244440999334265789881055142
Short name T375
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.46 seconds
Started Nov 22 03:11:17 PM PST 23
Finished Nov 22 03:12:34 PM PST 23
Peak memory 553696 kb
Host smart-06ff564d-9812-4f63-944e-fc702d5fb129
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24380244430454436744814423710397885257683153342159244440999334265789881055142 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.24380244430454436744814423710397885257683153342159244440999334265789881055142
Directory /workspace/79.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke.70874210208955976012641212190060189806343322888218326597565228826952620831221
Short name T895
Test name
Test status
Simulation time 196985727 ps
CPU time 8.48 seconds
Started Nov 22 03:10:56 PM PST 23
Finished Nov 22 03:11:10 PM PST 23
Peak memory 552368 kb
Host smart-b4540145-d070-4bd2-adc6-14a83073eb76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70874210208955976012641212190060189806343322888218326597565228826952620831221 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 79.xbar_smoke.70874210208955976012641212190060189806343322888218326597565228826952620831221
Directory /workspace/79.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.53345325883085656815821495612346286023368067204207100304811830644260277469913
Short name T1704
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.83 seconds
Started Nov 22 03:11:03 PM PST 23
Finished Nov 22 03:12:37 PM PST 23
Peak memory 552328 kb
Host smart-2d84392f-241e-4eff-8b2b-9f4b260a2a30
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53345325883085656815821495612346286023368067204207100304811830644260277469913 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.53345325883085656815821495612346286023368067204207100304811830644260277469913
Directory /workspace/79.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.113709235962225022981994383341299350052534939899329186853178247339951762931993
Short name T137
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.87 seconds
Started Nov 22 03:10:59 PM PST 23
Finished Nov 22 03:12:30 PM PST 23
Peak memory 552368 kb
Host smart-35c13b2f-9ffc-4023-bd77-341deda93caa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113709235962225022981994383341299350052534939899329186853178247339951762931993 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.113709235962225022981994383341299350052534939899329186853178247339951762931993
Directory /workspace/79.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.585584700729689982446279448193302881648117784843997198301393830401352384127
Short name T1559
Test name
Test status
Simulation time 45555727 ps
CPU time 6.04 seconds
Started Nov 22 03:10:53 PM PST 23
Finished Nov 22 03:11:01 PM PST 23
Peak memory 552340 kb
Host smart-97e28e4e-b732-4885-b76f-86466d9743ae
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585584700729689982446279448193302881648117784843997198301393830401352384127 -assert no
postproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays.585584700729689982446279448193302881648117784843997198301393830401352384127
Directory /workspace/79.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all.78930340725822261248214208817810875631290347484884244997706571496066963999334
Short name T1264
Test name
Test status
Simulation time 13992004073 ps
CPU time 496.75 seconds
Started Nov 22 03:11:04 PM PST 23
Finished Nov 22 03:19:24 PM PST 23
Peak memory 555852 kb
Host smart-abb95ae1-2486-4669-90a8-c46eaa46669f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78930340725822261248214208817810875631290347484884244997706571496066963999334 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.78930340725822261248214208817810875631290347484884244997706571496066963999334
Directory /workspace/79.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.53532919756053031661359106613811240841545122336857675353304847823455872816313
Short name T1136
Test name
Test status
Simulation time 13999524073 ps
CPU time 482.06 seconds
Started Nov 22 03:11:00 PM PST 23
Finished Nov 22 03:19:04 PM PST 23
Peak memory 555708 kb
Host smart-dbe21477-2ef4-4f11-af05-76953eeff73f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53532919756053031661359106613811240841545122336857675353304847823455872816313 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.53532919756053031661359106613811240841545122336857675353304847823455872816313
Directory /workspace/79.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2472493378308957653678866783890708546911179547957984564678399609429321219288
Short name T914
Test name
Test status
Simulation time 4815189184 ps
CPU time 364.26 seconds
Started Nov 22 03:11:13 PM PST 23
Finished Nov 22 03:17:18 PM PST 23
Peak memory 557148 kb
Host smart-afe8c843-a20f-49e5-8a9e-13820ae3406f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472493378308957653678866783890708546911179547957984564678399609429321219288 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_rand_reset.247249337830895765367886678389070854691117954795798456467839960
9429321219288
Directory /workspace/79.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.61123609653362601958532310954277034072194427115622281977348541269594919258874
Short name T946
Test name
Test status
Simulation time 4815189184 ps
CPU time 323.51 seconds
Started Nov 22 03:11:03 PM PST 23
Finished Nov 22 03:16:30 PM PST 23
Peak memory 559704 kb
Host smart-7ebca5a6-5890-44ba-a1a3-3b2adea4a3b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61123609653362601958532310954277034072194427115622281977348541269594919258874 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_reset_error.611236096533626019585323109542770340721944271156222819773485
41269594919258874
Directory /workspace/79.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.19662357703096923960639575723122623814348570092915261952532563857819567822163
Short name T293
Test name
Test status
Simulation time 1176995727 ps
CPU time 50 seconds
Started Nov 22 03:11:05 PM PST 23
Finished Nov 22 03:11:57 PM PST 23
Peak memory 553692 kb
Host smart-ca925598-fdcf-4072-975f-a8459a49d865
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19662357703096923960639575723122623814348570092915261952532563857819567822163 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.19662357703096923960639575723122623814348570092915261952532563857819567822163
Directory /workspace/79.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.85018438191674927755732754816342120776794702325305920678121196260437252106434
Short name T1311
Test name
Test status
Simulation time 7234930891 ps
CPU time 306.89 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:09:03 PM PST 23
Peak memory 622508 kb
Host smart-cbaea27e-b320-43af-9c29-95fa01172368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8501843819167492775573275481634
2120776794702325305920678121196260437252106434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.8501843819167
4927755732754816342120776794702325305920678121196260437252106434
Directory /workspace/8.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_rw.18132332744963005573086559101678261493640659065546704677646035649305847230275
Short name T857
Test name
Test status
Simulation time 5924944675 ps
CPU time 625.79 seconds
Started Nov 22 03:03:47 PM PST 23
Finished Nov 22 03:14:14 PM PST 23
Peak memory 580524 kb
Host smart-62988965-93bf-41f8-a638-8a54ada5c012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18132332744963005573086559101678261493640659065546704677646035649305847230275 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.18132332744963005573086559101678261493640659065546704677646035649305847230275
Directory /workspace/8.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.87989628804867333136777048487963092745812800542638371350145349488499350446542
Short name T25
Test name
Test status
Simulation time 30604932618 ps
CPU time 2870.83 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:51:32 PM PST 23
Peak memory 580524 kb
Host smart-0cefdd90-b34c-49a2-a815-f490c5352d51
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8798962880486733313677704848796309274
5812800542638371350145349488499350446542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.8798962880486733313677704
8487963092745812800542638371350145349488499350446542
Directory /workspace/8.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.chip_tl_errors.85662556874052004375080497660139758978129951568808932387788904737859585235832
Short name T1025
Test name
Test status
Simulation time 3069924257 ps
CPU time 187.53 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:06:49 PM PST 23
Peak memory 580516 kb
Host smart-1a1343f2-bfc8-4544-8d81-c320e9a8c63e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85662556874052004375080497660139758978129951568808932387788904737859585235832 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.85662556874052004375080497660139758978129951568808932387788904737859585235832
Directory /workspace/8.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device.67680765111384517288985986171606924991599060466682039411380880873497022995154
Short name T495
Test name
Test status
Simulation time 2590995727 ps
CPU time 105.84 seconds
Started Nov 22 03:03:57 PM PST 23
Finished Nov 22 03:05:43 PM PST 23
Peak memory 554784 kb
Host smart-96a3eaf8-f74f-4d03-afd1-a74ede124388
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67680765111384517288985986171606924991599060466682039411380880873497022995154 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.67680765111384517288985986171606924991599060466682039411380880873497022995154
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.111242193841746562039226428876009262149863606086701846079804158761528641711311
Short name T418
Test name
Test status
Simulation time 115195295727 ps
CPU time 2067.06 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:38:24 PM PST 23
Peak memory 554884 kb
Host smart-50850528-b097-4b80-8525-9f3f6f32e451
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111242193841746562039226428876009262149863606086701846079804158761528641711311 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.111242193841746562039226428876009262149863606086701846079804158761528641711311
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.45132261016986681053862848170801727441953940006398530634643076203598683356794
Short name T1505
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.29 seconds
Started Nov 22 03:03:49 PM PST 23
Finished Nov 22 03:04:37 PM PST 23
Peak memory 553492 kb
Host smart-1fc653a5-e2b3-485d-b094-a8866e2cbbe1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45132261016986681053862848170801727441953940006398530634643076203598683356794 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.45132261016986681053862848170801727441953940006398530634643076203598683356794
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_random.54019427759357270849250332500778613977547056332567964384545006648828383392479
Short name T169
Test name
Test status
Simulation time 2231375727 ps
CPU time 67.21 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:05:04 PM PST 23
Peak memory 553504 kb
Host smart-41f98416-7f7a-405b-9d0b-41b5e654127f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54019427759357270849250332500778613977547056332567964384545006648828383392479 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.xbar_error_random.54019427759357270849250332500778613977547056332567964384545006648828383392479
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random.98817754659555049503804033302799643918245493545861635697667830452458823869297
Short name T781
Test name
Test status
Simulation time 2231375727 ps
CPU time 68.65 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:04:49 PM PST 23
Peak memory 553744 kb
Host smart-46c0965e-2b40-42a7-b1a0-53dc6257c632
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98817754659555049503804033302799643918245493545861635697667830452458823869297 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.xbar_random.98817754659555049503804033302799643918245493545861635697667830452458823869297
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.72269243687560915038331910293697094736476298406874713387521326387634191022325
Short name T1817
Test name
Test status
Simulation time 97702135727 ps
CPU time 1087.94 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:21:52 PM PST 23
Peak memory 553684 kb
Host smart-4da7c9a3-4de7-4dbc-9c88-be4475799ca6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72269243687560915038331910293697094736476298406874713387521326387634191022325 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.72269243687560915038331910293697094736476298406874713387521326387634191022325
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.42250404538749928923338920344472029458210551006138197679434273853657497604187
Short name T918
Test name
Test status
Simulation time 60576345727 ps
CPU time 1044.35 seconds
Started Nov 22 03:03:57 PM PST 23
Finished Nov 22 03:21:22 PM PST 23
Peak memory 553680 kb
Host smart-e29f98d3-ef4c-4786-a43c-e3ebf7e3940c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42250404538749928923338920344472029458210551006138197679434273853657497604187 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.42250404538749928923338920344472029458210551006138197679434273853657497604187
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.17024854006918345565199143857664230420358014203463088879472454512346109898558
Short name T909
Test name
Test status
Simulation time 556965727 ps
CPU time 40.95 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:04:21 PM PST 23
Peak memory 553704 kb
Host smart-b54563b5-3fab-41ee-b8f2-a178755d1f14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17024854006918345565199143857664230420358014203463088879472454512346109898558 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.17024854006918345565199143857664230420358014203463088879472454512346109898558
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_same_source.13974152654782802302168322061365974596765669536837252245509601092485743764708
Short name T1120
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.09 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:05:10 PM PST 23
Peak memory 553708 kb
Host smart-f00a2d0b-1642-4a2b-b806-e9b0f64ca69b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13974152654782802302168322061365974596765669536837252245509601092485743764708 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.13974152654782802302168322061365974596765669536837252245509601092485743764708
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke.72906138975421182918875498580567400772710199074729130686993415680822553116043
Short name T267
Test name
Test status
Simulation time 196985727 ps
CPU time 8.22 seconds
Started Nov 22 03:03:29 PM PST 23
Finished Nov 22 03:03:38 PM PST 23
Peak memory 552360 kb
Host smart-273529aa-1724-4831-91f7-ba523310a420
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72906138975421182918875498580567400772710199074729130686993415680822553116043 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.xbar_smoke.72906138975421182918875498580567400772710199074729130686993415680822553116043
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.113623908455912323968952919508003883015277838787057987822879332853817123599424
Short name T595
Test name
Test status
Simulation time 7758585727 ps
CPU time 84.86 seconds
Started Nov 22 03:03:40 PM PST 23
Finished Nov 22 03:05:05 PM PST 23
Peak memory 552372 kb
Host smart-7e703189-1509-40a1-ad55-040d70cd22cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113623908455912323968952919508003883015277838787057987822879332853817123599424 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.113623908455912323968952919508003883015277838787057987822879332853817123599424
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.95761889632177715684421519387075111066000222674400596763756066163576654975231
Short name T1696
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.63 seconds
Started Nov 22 03:03:41 PM PST 23
Finished Nov 22 03:05:03 PM PST 23
Peak memory 552384 kb
Host smart-de4c7451-dfb1-4fb0-b176-f7d62907f467
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95761889632177715684421519387075111066000222674400596763756066163576654975231 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.95761889632177715684421519387075111066000222674400596763756066163576654975231
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.104484715173995368781616849981935872852777864161470648999419871403155833728218
Short name T285
Test name
Test status
Simulation time 45555727 ps
CPU time 5.85 seconds
Started Nov 22 03:03:38 PM PST 23
Finished Nov 22 03:03:44 PM PST 23
Peak memory 552356 kb
Host smart-c7cabcd5-5812-4cef-868b-742a5c0e2f27
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104484715173995368781616849981935872852777864161470648999419871403155833728218 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.104484715173995368781616849981935872852777864161470648999419871403155833728218
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all.71686388279830576950941744795487643828403424430056799379265704658468287950962
Short name T1863
Test name
Test status
Simulation time 13992004073 ps
CPU time 583.01 seconds
Started Nov 22 03:03:47 PM PST 23
Finished Nov 22 03:13:31 PM PST 23
Peak memory 555884 kb
Host smart-30ed7998-a723-41af-962a-9a50739ac0eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71686388279830576950941744795487643828403424430056799379265704658468287950962 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.71686388279830576950941744795487643828403424430056799379265704658468287950962
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.107653703829504372869153902686707474173598520387579838498607415353216531869989
Short name T1808
Test name
Test status
Simulation time 13999524073 ps
CPU time 481.6 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:11:58 PM PST 23
Peak memory 555700 kb
Host smart-24418f96-b8b2-4794-9b43-68ee660be70f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107653703829504372869153902686707474173598520387579838498607415353216531869989 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.107653703829504372869153902686707474173598520387579838498607415353216531869989
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.30730520349501464148276678629393450907658029921403273770485380203159243336597
Short name T1392
Test name
Test status
Simulation time 4815189184 ps
CPU time 373.83 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:10:11 PM PST 23
Peak memory 557236 kb
Host smart-08936532-614a-4bca-8266-4fe26a36b3e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30730520349501464148276678629393450907658029921403273770485380203159243336597 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.307305203495014641482766786293934509076580299214032737704853802
03159243336597
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.103368896908861926368628399955563215489765292059019980826749287442119973009255
Short name T1513
Test name
Test status
Simulation time 4815189184 ps
CPU time 330.22 seconds
Started Nov 22 03:03:42 PM PST 23
Finished Nov 22 03:09:14 PM PST 23
Peak memory 559660 kb
Host smart-ccd72fb1-2709-4dca-b7c2-fe2ee39ee899
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103368896908861926368628399955563215489765292059019980826749287442119973009255 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.103368896908861926368628399955563215489765292059019980826749
287442119973009255
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.38027236992592544963925267817425105733029746099995363539585128139901655615021
Short name T496
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.51 seconds
Started Nov 22 03:03:46 PM PST 23
Finished Nov 22 03:04:37 PM PST 23
Peak memory 553600 kb
Host smart-896a9e34-e687-47de-9847-af9465e0577b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027236992592544963925267817425105733029746099995363539585128139901655615021 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.38027236992592544963925267817425105733029746099995363539585128139901655615021
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device.98267941573124615270944353797784997573963665287910550174566417773935239372236
Short name T479
Test name
Test status
Simulation time 2590995727 ps
CPU time 119.26 seconds
Started Nov 22 03:11:10 PM PST 23
Finished Nov 22 03:13:10 PM PST 23
Peak memory 554764 kb
Host smart-ea41354d-4d15-496d-86a3-359aaecb0e72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98267941573124615270944353797784997573963665287910550174566417773935239372236 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.98267941573124615270944353797784997573963665287910550174566417773935239372236
Directory /workspace/80.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.80989944608962976260889976718056566326548692567515984616467939732781184215356
Short name T462
Test name
Test status
Simulation time 115195295727 ps
CPU time 2048.02 seconds
Started Nov 22 03:11:26 PM PST 23
Finished Nov 22 03:45:34 PM PST 23
Peak memory 554784 kb
Host smart-d8ddfab4-8368-4129-af75-41f8de8aed21
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80989944608962976260889976718056566326548692567515984616467939732781184215356 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device_slow_rsp.80989944608962976260889976718056566326548692567515984616467939732781184215356
Directory /workspace/80.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.85350639318107781637385830995408755772206506740973544201923697561102030792742
Short name T514
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.05 seconds
Started Nov 22 03:11:09 PM PST 23
Finished Nov 22 03:11:54 PM PST 23
Peak memory 553460 kb
Host smart-0b308582-24d4-4ea8-bfb3-b50043ffc792
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85350639318107781637385830995408755772206506740973544201923697561102030792742 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr.85350639318107781637385830995408755772206506740973544201923697561102030792742
Directory /workspace/80.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_random.103990912309068973769981281883127208141709740668990247028470377798647833227575
Short name T116
Test name
Test status
Simulation time 2231375727 ps
CPU time 68.85 seconds
Started Nov 22 03:11:10 PM PST 23
Finished Nov 22 03:12:19 PM PST 23
Peak memory 553536 kb
Host smart-ae6c7064-7659-4a6c-ab63-f166e4fa7ac9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103990912309068973769981281883127208141709740668990247028470377798647833227575 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 80.xbar_error_random.103990912309068973769981281883127208141709740668990247028470377798647833227575
Directory /workspace/80.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random.105527376805259442670171752918810495431933741392210418936965853958081229816830
Short name T215
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.8 seconds
Started Nov 22 03:11:10 PM PST 23
Finished Nov 22 03:12:30 PM PST 23
Peak memory 553840 kb
Host smart-3d2de23f-9ade-4eb1-9fa4-1689f3141d1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105527376805259442670171752918810495431933741392210418936965853958081229816830 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 80.xbar_random.105527376805259442670171752918810495431933741392210418936965853958081229816830
Directory /workspace/80.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.65128460030088257176756263974291713273892276339881285869802532139597576618417
Short name T1318
Test name
Test status
Simulation time 97702135727 ps
CPU time 1160.69 seconds
Started Nov 22 03:11:10 PM PST 23
Finished Nov 22 03:30:32 PM PST 23
Peak memory 553680 kb
Host smart-da29f7ff-5276-4d32-91b1-6785a09bb12e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65128460030088257176756263974291713273892276339881285869802532139597576618417 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.65128460030088257176756263974291713273892276339881285869802532139597576618417
Directory /workspace/80.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.69096573250518874509114930716181921669016655186953818654141869170182212849147
Short name T762
Test name
Test status
Simulation time 60576345727 ps
CPU time 1132.12 seconds
Started Nov 22 03:11:10 PM PST 23
Finished Nov 22 03:30:02 PM PST 23
Peak memory 553524 kb
Host smart-1d73cce7-9d82-44aa-9130-b1c410d3ba33
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69096573250518874509114930716181921669016655186953818654141869170182212849147 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.69096573250518874509114930716181921669016655186953818654141869170182212849147
Directory /workspace/80.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.18496636930576982374834891621692264124313123538880363147931672640551607507741
Short name T1665
Test name
Test status
Simulation time 556965727 ps
CPU time 50.43 seconds
Started Nov 22 03:11:11 PM PST 23
Finished Nov 22 03:12:02 PM PST 23
Peak memory 553692 kb
Host smart-f472c986-2b73-4043-8564-aabd1bf2de53
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18496636930576982374834891621692264124313123538880363147931672640551607507741 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_delays.18496636930576982374834891621692264124313123538880363147931672640551607507741
Directory /workspace/80.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_same_source.58988931537238022597149282509134681605443596057689274651893416565794168321830
Short name T651
Test name
Test status
Simulation time 2498784073 ps
CPU time 80.1 seconds
Started Nov 22 03:11:10 PM PST 23
Finished Nov 22 03:12:30 PM PST 23
Peak memory 553724 kb
Host smart-ad1e137e-def5-4858-afc7-a9e719f66eb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58988931537238022597149282509134681605443596057689274651893416565794168321830 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.58988931537238022597149282509134681605443596057689274651893416565794168321830
Directory /workspace/80.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke.99093733594440056621208474791610090762080383867869419938605380338519556079908
Short name T851
Test name
Test status
Simulation time 196985727 ps
CPU time 8.36 seconds
Started Nov 22 03:11:11 PM PST 23
Finished Nov 22 03:11:20 PM PST 23
Peak memory 552392 kb
Host smart-69131302-5e46-471e-9709-2325e2bbc85e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99093733594440056621208474791610090762080383867869419938605380338519556079908 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 80.xbar_smoke.99093733594440056621208474791610090762080383867869419938605380338519556079908
Directory /workspace/80.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.46729885179686024263909144136187715538523302451499413436387229610952294803095
Short name T1175
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.31 seconds
Started Nov 22 03:11:09 PM PST 23
Finished Nov 22 03:12:40 PM PST 23
Peak memory 552400 kb
Host smart-5dd39476-88a5-4d26-9e11-4877f6535c9d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46729885179686024263909144136187715538523302451499413436387229610952294803095 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.46729885179686024263909144136187715538523302451499413436387229610952294803095
Directory /workspace/80.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.113665858601159174999834420860776984064740154235477332897926179845135565260177
Short name T649
Test name
Test status
Simulation time 4856075727 ps
CPU time 91.37 seconds
Started Nov 22 03:11:11 PM PST 23
Finished Nov 22 03:12:44 PM PST 23
Peak memory 552380 kb
Host smart-a28e2ba8-6b48-4a41-b6d2-ef042428fcbd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113665858601159174999834420860776984064740154235477332897926179845135565260177 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.113665858601159174999834420860776984064740154235477332897926179845135565260177
Directory /workspace/80.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.12732445425905571452684665465383666120930586045502344702138455034150246214086
Short name T1610
Test name
Test status
Simulation time 45555727 ps
CPU time 6.01 seconds
Started Nov 22 03:11:10 PM PST 23
Finished Nov 22 03:11:17 PM PST 23
Peak memory 552360 kb
Host smart-b270fc9b-3975-44a3-9571-bd01b8a9cfec
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732445425905571452684665465383666120930586045502344702138455034150246214086 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays.12732445425905571452684665465383666120930586045502344702138455034150246214086
Directory /workspace/80.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all.46419974475959759925484988198485815998080967112283342046126107310111188554970
Short name T1366
Test name
Test status
Simulation time 13992004073 ps
CPU time 488.44 seconds
Started Nov 22 03:11:11 PM PST 23
Finished Nov 22 03:19:20 PM PST 23
Peak memory 555880 kb
Host smart-fa9c7797-5714-482f-8685-3651ab29df3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46419974475959759925484988198485815998080967112283342046126107310111188554970 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.46419974475959759925484988198485815998080967112283342046126107310111188554970
Directory /workspace/80.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.68672286222721890600996324036941522153527016384962644409523756051775330631914
Short name T1779
Test name
Test status
Simulation time 13999524073 ps
CPU time 481.32 seconds
Started Nov 22 03:11:21 PM PST 23
Finished Nov 22 03:19:23 PM PST 23
Peak memory 555728 kb
Host smart-47503a3f-a87e-4a6d-96de-826c4cf06bcc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68672286222721890600996324036941522153527016384962644409523756051775330631914 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.68672286222721890600996324036941522153527016384962644409523756051775330631914
Directory /workspace/80.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.52811746748790745241056823386375979833403123192655962302835830813217180065934
Short name T603
Test name
Test status
Simulation time 4815189184 ps
CPU time 350.17 seconds
Started Nov 22 03:11:09 PM PST 23
Finished Nov 22 03:17:00 PM PST 23
Peak memory 557320 kb
Host smart-42781770-3030-4dad-aa3a-b5bd6609dc99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52811746748790745241056823386375979833403123192655962302835830813217180065934 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_rand_reset.52811746748790745241056823386375979833403123192655962302835830
813217180065934
Directory /workspace/80.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.81026043812490711415463027315376188878163955006676666889968806133954283949529
Short name T1103
Test name
Test status
Simulation time 4815189184 ps
CPU time 324.44 seconds
Started Nov 22 03:11:12 PM PST 23
Finished Nov 22 03:16:37 PM PST 23
Peak memory 559660 kb
Host smart-001a2522-983c-424f-bc36-60a4d5386a37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81026043812490711415463027315376188878163955006676666889968806133954283949529 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_reset_error.810260438124907114154630273153761888781639550066766668899688
06133954283949529
Directory /workspace/80.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.33585739273571631856600314878844212201391100516369691949320137717945570361524
Short name T1122
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.93 seconds
Started Nov 22 03:11:13 PM PST 23
Finished Nov 22 03:12:03 PM PST 23
Peak memory 553628 kb
Host smart-3875f7ff-da02-497f-9236-054fb4e0504a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33585739273571631856600314878844212201391100516369691949320137717945570361524 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.33585739273571631856600314878844212201391100516369691949320137717945570361524
Directory /workspace/80.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device.2411544926742177431253094772449791097011217231122116652082152188026317494713
Short name T422
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.07 seconds
Started Nov 22 03:11:24 PM PST 23
Finished Nov 22 03:13:13 PM PST 23
Peak memory 554736 kb
Host smart-eb21797b-3c7f-4b2f-b884-68b9b73a9b3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411544926742177431253094772449791097011217231122116652082152188026317494713 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.2411544926742177431253094772449791097011217231122116652082152188026317494713
Directory /workspace/81.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.111059107760237588260013402735557009869695575084532859798064098284121387405260
Short name T1269
Test name
Test status
Simulation time 115195295727 ps
CPU time 2057.11 seconds
Started Nov 22 03:11:24 PM PST 23
Finished Nov 22 03:45:42 PM PST 23
Peak memory 554792 kb
Host smart-55483722-d465-497f-9e2e-6c7c5d42b029
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111059107760237588260013402735557009869695575084532859798064098284121387405260 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device_slow_rsp.111059107760237588260013402735557009869695575084532859798064098284121387405260
Directory /workspace/81.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.89312923173219351392971444916394995564599701659216665673390482226030917735405
Short name T211
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.2 seconds
Started Nov 22 03:11:27 PM PST 23
Finished Nov 22 03:12:13 PM PST 23
Peak memory 553500 kb
Host smart-886b5877-c436-435b-b861-593e1514820f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89312923173219351392971444916394995564599701659216665673390482226030917735405 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr.89312923173219351392971444916394995564599701659216665673390482226030917735405
Directory /workspace/81.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_random.115684982389335311401959760419191592426737602858245485524159396600901244938348
Short name T1409
Test name
Test status
Simulation time 2231375727 ps
CPU time 81.77 seconds
Started Nov 22 03:11:22 PM PST 23
Finished Nov 22 03:12:44 PM PST 23
Peak memory 553492 kb
Host smart-acb20dfd-a7a1-4470-8c9d-14a95cd1a7c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115684982389335311401959760419191592426737602858245485524159396600901244938348 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 81.xbar_error_random.115684982389335311401959760419191592426737602858245485524159396600901244938348
Directory /workspace/81.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random.4402125879457537682197775568549097288630244408697169086546002333336466361526
Short name T1241
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.28 seconds
Started Nov 22 03:11:12 PM PST 23
Finished Nov 22 03:12:32 PM PST 23
Peak memory 553812 kb
Host smart-9f83c0ba-2928-40e1-974f-561beed28dde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4402125879457537682197775568549097288630244408697169086546002333336466361526 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 81.xbar_random.4402125879457537682197775568549097288630244408697169086546002333336466361526
Directory /workspace/81.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.80613135279439297725163509748684519959138795256676546323258546624917648183662
Short name T1706
Test name
Test status
Simulation time 97702135727 ps
CPU time 1166.17 seconds
Started Nov 22 03:11:12 PM PST 23
Finished Nov 22 03:30:39 PM PST 23
Peak memory 553652 kb
Host smart-af55bee4-7df1-46a4-a2fd-f26da85650de
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80613135279439297725163509748684519959138795256676546323258546624917648183662 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.80613135279439297725163509748684519959138795256676546323258546624917648183662
Directory /workspace/81.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.102809595229609687762781714541116893656302661457672164976477657320089850595929
Short name T441
Test name
Test status
Simulation time 60576345727 ps
CPU time 1111 seconds
Started Nov 22 03:11:22 PM PST 23
Finished Nov 22 03:29:54 PM PST 23
Peak memory 553816 kb
Host smart-697aeb1a-14e3-4e5d-96c8-b3e2cee6d626
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102809595229609687762781714541116893656302661457672164976477657320089850595929 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.102809595229609687762781714541116893656302661457672164976477657320089850595929
Directory /workspace/81.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.88714157955777574921072489489878309262747715440092506944479044341122764249438
Short name T1219
Test name
Test status
Simulation time 556965727 ps
CPU time 46.17 seconds
Started Nov 22 03:11:23 PM PST 23
Finished Nov 22 03:12:10 PM PST 23
Peak memory 553624 kb
Host smart-ca8aaae3-4978-4622-9419-2f9f19c7bfca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88714157955777574921072489489878309262747715440092506944479044341122764249438 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_delays.88714157955777574921072489489878309262747715440092506944479044341122764249438
Directory /workspace/81.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_same_source.24794796868521009838285483633652057938986632393275224991266278950367815347891
Short name T556
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.35 seconds
Started Nov 22 03:11:21 PM PST 23
Finished Nov 22 03:12:38 PM PST 23
Peak memory 553712 kb
Host smart-98b60c15-39c4-470d-8e34-514f3fbd4cfc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794796868521009838285483633652057938986632393275224991266278950367815347891 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.24794796868521009838285483633652057938986632393275224991266278950367815347891
Directory /workspace/81.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke.50028303478654662790178256951423193426617833289861527971373700911347693529078
Short name T1386
Test name
Test status
Simulation time 196985727 ps
CPU time 8.94 seconds
Started Nov 22 03:11:21 PM PST 23
Finished Nov 22 03:11:31 PM PST 23
Peak memory 552480 kb
Host smart-c520723c-acd2-467f-9924-1f09aaf01989
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50028303478654662790178256951423193426617833289861527971373700911347693529078 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 81.xbar_smoke.50028303478654662790178256951423193426617833289861527971373700911347693529078
Directory /workspace/81.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.71912143131072036832661025823321483705547327234226170998096330260642073544800
Short name T1640
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.26 seconds
Started Nov 22 03:11:12 PM PST 23
Finished Nov 22 03:12:43 PM PST 23
Peak memory 552408 kb
Host smart-28c76a32-2585-47f7-a0b5-c1a988b40f1e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71912143131072036832661025823321483705547327234226170998096330260642073544800 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.71912143131072036832661025823321483705547327234226170998096330260642073544800
Directory /workspace/81.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.13563059667096962143541338839217316861141709993275457634032619844820402329682
Short name T1918
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.54 seconds
Started Nov 22 03:11:23 PM PST 23
Finished Nov 22 03:12:51 PM PST 23
Peak memory 552412 kb
Host smart-85967ac5-45e9-4b05-9151-b97931d94782
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13563059667096962143541338839217316861141709993275457634032619844820402329682 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.13563059667096962143541338839217316861141709993275457634032619844820402329682
Directory /workspace/81.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.13859329368913687911454897933406062950818743682148318893037279633831085764230
Short name T1247
Test name
Test status
Simulation time 45555727 ps
CPU time 5.77 seconds
Started Nov 22 03:11:21 PM PST 23
Finished Nov 22 03:11:28 PM PST 23
Peak memory 552348 kb
Host smart-e64d7af2-7b00-4e1d-bbb1-4b7a1e0f55c8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13859329368913687911454897933406062950818743682148318893037279633831085764230 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.13859329368913687911454897933406062950818743682148318893037279633831085764230
Directory /workspace/81.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all.12808388455746665607481591410211780037247770428514076344053174478055065139866
Short name T386
Test name
Test status
Simulation time 13992004073 ps
CPU time 543.54 seconds
Started Nov 22 03:11:22 PM PST 23
Finished Nov 22 03:20:27 PM PST 23
Peak memory 555912 kb
Host smart-19d00021-0b43-45e4-85c3-dc0d4aaef801
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12808388455746665607481591410211780037247770428514076344053174478055065139866 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.12808388455746665607481591410211780037247770428514076344053174478055065139866
Directory /workspace/81.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.26473313647018436309505419948791915765106513679052965189155919819937285726001
Short name T1288
Test name
Test status
Simulation time 13999524073 ps
CPU time 472.36 seconds
Started Nov 22 03:11:24 PM PST 23
Finished Nov 22 03:19:17 PM PST 23
Peak memory 555724 kb
Host smart-e9c8e972-64c1-44e4-aaad-b81ef8c8dc5f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26473313647018436309505419948791915765106513679052965189155919819937285726001 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.26473313647018436309505419948791915765106513679052965189155919819937285726001
Directory /workspace/81.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.102317876936335202597043543944945098970242553953005862358819524691761531091722
Short name T1395
Test name
Test status
Simulation time 4815189184 ps
CPU time 374.45 seconds
Started Nov 22 03:11:24 PM PST 23
Finished Nov 22 03:17:39 PM PST 23
Peak memory 557240 kb
Host smart-24c36ab0-af83-4cdd-922f-bd56821b6061
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102317876936335202597043543944945098970242553953005862358819524691761531091722 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_rand_reset.1023178769363352025970435439449450989702425539530058623588195
24691761531091722
Directory /workspace/81.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.94130212782486236557050692813466962626473130119455746230317857757268840186675
Short name T1617
Test name
Test status
Simulation time 4815189184 ps
CPU time 317.12 seconds
Started Nov 22 03:11:25 PM PST 23
Finished Nov 22 03:16:43 PM PST 23
Peak memory 559704 kb
Host smart-1d3b6819-fb4b-4289-9c76-a59230bed0f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94130212782486236557050692813466962626473130119455746230317857757268840186675 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_reset_error.941302127824862365570506928134669626264731301194557462303178
57757268840186675
Directory /workspace/81.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.12551830171126597443035449955544475551981475206314601812585718004318898471293
Short name T1846
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.72 seconds
Started Nov 22 03:11:24 PM PST 23
Finished Nov 22 03:12:13 PM PST 23
Peak memory 553692 kb
Host smart-74d9b93f-c65a-4789-8305-d0cf31ef63f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12551830171126597443035449955544475551981475206314601812585718004318898471293 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.12551830171126597443035449955544475551981475206314601812585718004318898471293
Directory /workspace/81.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device.39668366464407746824220528887913694879908324375687387774595967891533899070781
Short name T545
Test name
Test status
Simulation time 2590995727 ps
CPU time 117.51 seconds
Started Nov 22 03:11:28 PM PST 23
Finished Nov 22 03:13:26 PM PST 23
Peak memory 554740 kb
Host smart-61fc7879-411f-4bdf-a271-3fc4ecb5cd2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39668366464407746824220528887913694879908324375687387774595967891533899070781 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.39668366464407746824220528887913694879908324375687387774595967891533899070781
Directory /workspace/82.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.33990945477276687660147604479575207325937707568731905302971708714253360984734
Short name T530
Test name
Test status
Simulation time 115195295727 ps
CPU time 2091.36 seconds
Started Nov 22 03:11:22 PM PST 23
Finished Nov 22 03:46:14 PM PST 23
Peak memory 554780 kb
Host smart-0ee94742-29e8-4bf8-bd6c-1793e8b967fd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33990945477276687660147604479575207325937707568731905302971708714253360984734 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device_slow_rsp.33990945477276687660147604479575207325937707568731905302971708714253360984734
Directory /workspace/82.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.31484472114771954372358584007844909661539020544341688934587320774839165946233
Short name T1910
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.24 seconds
Started Nov 22 03:11:28 PM PST 23
Finished Nov 22 03:12:13 PM PST 23
Peak memory 553444 kb
Host smart-64473ef0-cf66-47af-ac69-cbcfe32f8d60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31484472114771954372358584007844909661539020544341688934587320774839165946233 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr.31484472114771954372358584007844909661539020544341688934587320774839165946233
Directory /workspace/82.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_random.106949563464981714918006222130986198363595162071340401379131543309617954635091
Short name T666
Test name
Test status
Simulation time 2231375727 ps
CPU time 71.01 seconds
Started Nov 22 03:11:29 PM PST 23
Finished Nov 22 03:12:41 PM PST 23
Peak memory 553532 kb
Host smart-ed5370cd-9aeb-4286-83fb-c33b29b05c38
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106949563464981714918006222130986198363595162071340401379131543309617954635091 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 82.xbar_error_random.106949563464981714918006222130986198363595162071340401379131543309617954635091
Directory /workspace/82.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random.33210837889229911221101931070502011855736219838495309502686408098570190600907
Short name T1041
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.91 seconds
Started Nov 22 03:11:27 PM PST 23
Finished Nov 22 03:12:44 PM PST 23
Peak memory 553764 kb
Host smart-bc83d990-fe30-4d27-8a57-1686cf6fe490
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210837889229911221101931070502011855736219838495309502686408098570190600907 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 82.xbar_random.33210837889229911221101931070502011855736219838495309502686408098570190600907
Directory /workspace/82.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.62277975996516413741224647927596185324314388289163510962565900569813819512582
Short name T1059
Test name
Test status
Simulation time 97702135727 ps
CPU time 1148.07 seconds
Started Nov 22 03:11:28 PM PST 23
Finished Nov 22 03:30:36 PM PST 23
Peak memory 553628 kb
Host smart-d12fe9c2-8ba9-467c-b3d9-4f4483326c0d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62277975996516413741224647927596185324314388289163510962565900569813819512582 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.62277975996516413741224647927596185324314388289163510962565900569813819512582
Directory /workspace/82.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.80716350443211448195568688325298439891757679012325971439996903646940450564679
Short name T1677
Test name
Test status
Simulation time 60576345727 ps
CPU time 1100.73 seconds
Started Nov 22 03:11:27 PM PST 23
Finished Nov 22 03:29:49 PM PST 23
Peak memory 553716 kb
Host smart-2b50e23e-60d3-4cef-a815-f677fa9a5dcc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80716350443211448195568688325298439891757679012325971439996903646940450564679 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.80716350443211448195568688325298439891757679012325971439996903646940450564679
Directory /workspace/82.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.34860238947225902472353663574594978021560669817443151036091150460301300197626
Short name T81
Test name
Test status
Simulation time 556965727 ps
CPU time 47.16 seconds
Started Nov 22 03:11:26 PM PST 23
Finished Nov 22 03:12:14 PM PST 23
Peak memory 553644 kb
Host smart-3416bf1f-0589-45a5-adb8-20d09cf7a671
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34860238947225902472353663574594978021560669817443151036091150460301300197626 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_delays.34860238947225902472353663574594978021560669817443151036091150460301300197626
Directory /workspace/82.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_same_source.109042917271956785110910687715203435639230800539879222867911094451811446092922
Short name T1452
Test name
Test status
Simulation time 2498784073 ps
CPU time 75.36 seconds
Started Nov 22 03:11:23 PM PST 23
Finished Nov 22 03:12:39 PM PST 23
Peak memory 553716 kb
Host smart-bcba8bc4-cc7b-49e5-838d-38b839776f86
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109042917271956785110910687715203435639230800539879222867911094451811446092922 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.109042917271956785110910687715203435639230800539879222867911094451811446092922
Directory /workspace/82.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke.107352239426201491448713918020202482552920271516032704391194066819655279598473
Short name T1536
Test name
Test status
Simulation time 196985727 ps
CPU time 8.76 seconds
Started Nov 22 03:11:24 PM PST 23
Finished Nov 22 03:11:33 PM PST 23
Peak memory 552364 kb
Host smart-eff9d27d-e21f-4ff0-99a6-32b7ec2b0b36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107352239426201491448713918020202482552920271516032704391194066819655279598473 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 82.xbar_smoke.107352239426201491448713918020202482552920271516032704391194066819655279598473
Directory /workspace/82.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.94218409193142022698423992399159097332215579340180345837037393729154942803898
Short name T301
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.85 seconds
Started Nov 22 03:11:30 PM PST 23
Finished Nov 22 03:13:02 PM PST 23
Peak memory 552380 kb
Host smart-a36d519d-cb86-4650-9696-8211337236b2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94218409193142022698423992399159097332215579340180345837037393729154942803898 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.94218409193142022698423992399159097332215579340180345837037393729154942803898
Directory /workspace/82.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.109178817100871251669227163112838776886668425150611854110689269925469817082312
Short name T983
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.34 seconds
Started Nov 22 03:11:27 PM PST 23
Finished Nov 22 03:12:54 PM PST 23
Peak memory 552268 kb
Host smart-2f0195dd-5e77-484f-9e59-1631cfa9643c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109178817100871251669227163112838776886668425150611854110689269925469817082312 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.109178817100871251669227163112838776886668425150611854110689269925469817082312
Directory /workspace/82.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.65522002096079607808522948006853976654590275081446669393504491722185105329101
Short name T1927
Test name
Test status
Simulation time 45555727 ps
CPU time 5.94 seconds
Started Nov 22 03:11:26 PM PST 23
Finished Nov 22 03:11:32 PM PST 23
Peak memory 552236 kb
Host smart-925f5dd8-7eca-452f-ba18-b9d2e65cea7e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65522002096079607808522948006853976654590275081446669393504491722185105329101 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.65522002096079607808522948006853976654590275081446669393504491722185105329101
Directory /workspace/82.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all.57178514833745292000836291097375920914472985047799715252132038022758849545505
Short name T1194
Test name
Test status
Simulation time 13992004073 ps
CPU time 484.22 seconds
Started Nov 22 03:11:30 PM PST 23
Finished Nov 22 03:19:35 PM PST 23
Peak memory 555900 kb
Host smart-49a31650-b053-4af8-a691-26c4c484a8c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57178514833745292000836291097375920914472985047799715252132038022758849545505 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.57178514833745292000836291097375920914472985047799715252132038022758849545505
Directory /workspace/82.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.112255303015278780171090360506376504786176824626460904246943855907553219998612
Short name T776
Test name
Test status
Simulation time 13999524073 ps
CPU time 501.23 seconds
Started Nov 22 03:11:30 PM PST 23
Finished Nov 22 03:19:52 PM PST 23
Peak memory 555724 kb
Host smart-20014289-be28-4d4d-b7c7-dc00e777c0bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112255303015278780171090360506376504786176824626460904246943855907553219998612 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.112255303015278780171090360506376504786176824626460904246943855907553219998612
Directory /workspace/82.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.22630050207665548060642511425479566234758403602089020439517951991629986992190
Short name T313
Test name
Test status
Simulation time 4815189184 ps
CPU time 368.14 seconds
Started Nov 22 03:11:27 PM PST 23
Finished Nov 22 03:17:36 PM PST 23
Peak memory 557212 kb
Host smart-f6b9debf-a953-4046-941b-68d6341b7173
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22630050207665548060642511425479566234758403602089020439517951991629986992190 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_rand_reset.22630050207665548060642511425479566234758403602089020439517951
991629986992190
Directory /workspace/82.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.108401840377134467041821391248975719986816932967624252523910147063846289830313
Short name T1075
Test name
Test status
Simulation time 4815189184 ps
CPU time 316 seconds
Started Nov 22 03:11:25 PM PST 23
Finished Nov 22 03:16:42 PM PST 23
Peak memory 559720 kb
Host smart-931c49f4-b07e-4d54-8e56-f7250f59390d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108401840377134467041821391248975719986816932967624252523910147063846289830313 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_reset_error.10840184037713446704182139124897571998681693296762425252391
0147063846289830313
Directory /workspace/82.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.29450454785271560232403019599193994168762254510201475293911221115103227403487
Short name T1588
Test name
Test status
Simulation time 1176995727 ps
CPU time 44.72 seconds
Started Nov 22 03:11:29 PM PST 23
Finished Nov 22 03:12:15 PM PST 23
Peak memory 553704 kb
Host smart-7eadf544-af5c-41fc-83de-d0bb92f0c6ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29450454785271560232403019599193994168762254510201475293911221115103227403487 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.29450454785271560232403019599193994168762254510201475293911221115103227403487
Directory /workspace/82.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device.78494124958523760970056291652170944636957112588713683922647418968027812944197
Short name T1881
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.09 seconds
Started Nov 22 03:11:46 PM PST 23
Finished Nov 22 03:13:36 PM PST 23
Peak memory 554792 kb
Host smart-607b3820-595b-466a-b576-e53756667cf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78494124958523760970056291652170944636957112588713683922647418968027812944197 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.78494124958523760970056291652170944636957112588713683922647418968027812944197
Directory /workspace/83.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.102457168449144508066888935450951793501561571978770765128520863417145180263880
Short name T1816
Test name
Test status
Simulation time 115195295727 ps
CPU time 1979.83 seconds
Started Nov 22 03:11:43 PM PST 23
Finished Nov 22 03:44:44 PM PST 23
Peak memory 554736 kb
Host smart-b5b2459a-88d7-4dfa-b7fc-0b1dbca4742a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102457168449144508066888935450951793501561571978770765128520863417145180263880 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device_slow_rsp.102457168449144508066888935450951793501561571978770765128520863417145180263880
Directory /workspace/83.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.15582412700346162497584393602759175511332431716640295355996350701258291311623
Short name T463
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.91 seconds
Started Nov 22 03:11:41 PM PST 23
Finished Nov 22 03:12:30 PM PST 23
Peak memory 553520 kb
Host smart-a1738595-b550-4b70-810a-01608d46e066
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15582412700346162497584393602759175511332431716640295355996350701258291311623 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr.15582412700346162497584393602759175511332431716640295355996350701258291311623
Directory /workspace/83.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_random.727529568876009812584382334417308341650482956687822358403207723572698921100
Short name T229
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.72 seconds
Started Nov 22 03:11:48 PM PST 23
Finished Nov 22 03:13:05 PM PST 23
Peak memory 553456 kb
Host smart-60304301-62bb-4b5d-ba85-8cf1cc0fb687
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727529568876009812584382334417308341650482956687822358403207723572698921100 -assert nopostproc +UVM_T
ESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 83.xbar_error_random.727529568876009812584382334417308341650482956687822358403207723572698921100
Directory /workspace/83.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random.79205568579202234886064613292649029636830905293395152405306121648852143943985
Short name T1284
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.17 seconds
Started Nov 22 03:11:48 PM PST 23
Finished Nov 22 03:13:02 PM PST 23
Peak memory 553680 kb
Host smart-7a32169a-efcf-4869-bd3f-837427035d9e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79205568579202234886064613292649029636830905293395152405306121648852143943985 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 83.xbar_random.79205568579202234886064613292649029636830905293395152405306121648852143943985
Directory /workspace/83.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.60631276424971945623181724561245673373137417556693086925698261752537970753390
Short name T465
Test name
Test status
Simulation time 97702135727 ps
CPU time 1110.98 seconds
Started Nov 22 03:11:35 PM PST 23
Finished Nov 22 03:30:07 PM PST 23
Peak memory 553588 kb
Host smart-a3f59ac2-9d2c-4344-825b-b53fcbaae562
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60631276424971945623181724561245673373137417556693086925698261752537970753390 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.60631276424971945623181724561245673373137417556693086925698261752537970753390
Directory /workspace/83.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.108975489290512441746545775066858219078133889482107456755390116260333589365608
Short name T1664
Test name
Test status
Simulation time 60576345727 ps
CPU time 1119.34 seconds
Started Nov 22 03:11:43 PM PST 23
Finished Nov 22 03:30:23 PM PST 23
Peak memory 553724 kb
Host smart-b02a5ec1-f58d-460e-894d-027dc6288fa6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108975489290512441746545775066858219078133889482107456755390116260333589365608 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.108975489290512441746545775066858219078133889482107456755390116260333589365608
Directory /workspace/83.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.43747348387670968634600030236917990561538182583451375429316018132562961098641
Short name T1174
Test name
Test status
Simulation time 556965727 ps
CPU time 49.38 seconds
Started Nov 22 03:11:43 PM PST 23
Finished Nov 22 03:12:33 PM PST 23
Peak memory 553652 kb
Host smart-3e6ce16d-3084-40b3-95e9-ddd721aba404
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43747348387670968634600030236917990561538182583451375429316018132562961098641 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delays.43747348387670968634600030236917990561538182583451375429316018132562961098641
Directory /workspace/83.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_same_source.31543190807172973917347625064240782657755759923933765415980560948225556773091
Short name T400
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.15 seconds
Started Nov 22 03:11:50 PM PST 23
Finished Nov 22 03:13:03 PM PST 23
Peak memory 553656 kb
Host smart-6c1e1b13-b53a-445c-ba0d-a13d55dbb9e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543190807172973917347625064240782657755759923933765415980560948225556773091 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.31543190807172973917347625064240782657755759923933765415980560948225556773091
Directory /workspace/83.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke.58112244565156831502512180257375432474952403186377465954524800588292142986185
Short name T879
Test name
Test status
Simulation time 196985727 ps
CPU time 8.64 seconds
Started Nov 22 03:11:25 PM PST 23
Finished Nov 22 03:11:34 PM PST 23
Peak memory 552304 kb
Host smart-99fea85f-250f-4b8f-9e1d-d32bb7875da0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58112244565156831502512180257375432474952403186377465954524800588292142986185 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 83.xbar_smoke.58112244565156831502512180257375432474952403186377465954524800588292142986185
Directory /workspace/83.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.89443989133494418762335138046571960013400730478691558480554223347575801374809
Short name T1748
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.23 seconds
Started Nov 22 03:11:26 PM PST 23
Finished Nov 22 03:12:56 PM PST 23
Peak memory 552304 kb
Host smart-dd627b72-2d89-460c-b06f-91f6ea92f60b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89443989133494418762335138046571960013400730478691558480554223347575801374809 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.89443989133494418762335138046571960013400730478691558480554223347575801374809
Directory /workspace/83.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.95714893507154420222732254960849543380755298783560341275803923955344586608037
Short name T1498
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.13 seconds
Started Nov 22 03:11:44 PM PST 23
Finished Nov 22 03:13:11 PM PST 23
Peak memory 552304 kb
Host smart-04596e35-1029-4b86-ab30-dc56cece184b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95714893507154420222732254960849543380755298783560341275803923955344586608037 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.95714893507154420222732254960849543380755298783560341275803923955344586608037
Directory /workspace/83.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.112049999862405478502557724023793074630436940498646585528929213337603919071605
Short name T1340
Test name
Test status
Simulation time 45555727 ps
CPU time 5.63 seconds
Started Nov 22 03:11:27 PM PST 23
Finished Nov 22 03:11:33 PM PST 23
Peak memory 552360 kb
Host smart-142f5920-a939-41e5-9bbf-44f592a63e51
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112049999862405478502557724023793074630436940498646585528929213337603919071605 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.112049999862405478502557724023793074630436940498646585528929213337603919071605
Directory /workspace/83.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all.37541633978382167641244681423926597381938072779442516169222408904164313867608
Short name T1233
Test name
Test status
Simulation time 13992004073 ps
CPU time 520.82 seconds
Started Nov 22 03:11:52 PM PST 23
Finished Nov 22 03:20:34 PM PST 23
Peak memory 555920 kb
Host smart-44f53560-d048-4043-97e7-173825690375
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541633978382167641244681423926597381938072779442516169222408904164313867608 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.37541633978382167641244681423926597381938072779442516169222408904164313867608
Directory /workspace/83.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.6543099825809811635500437977258306446020014904440667063815878087965357247449
Short name T1441
Test name
Test status
Simulation time 13999524073 ps
CPU time 495.27 seconds
Started Nov 22 03:11:45 PM PST 23
Finished Nov 22 03:20:01 PM PST 23
Peak memory 555672 kb
Host smart-900cb9a7-133a-483c-b9c4-a3e15d4a3dc0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6543099825809811635500437977258306446020014904440667063815878087965357247449 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.6543099825809811635500437977258306446020014904440667063815878087965357247449
Directory /workspace/83.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.7468673046621425894418219239602732219562201017741675959194241227617204154561
Short name T617
Test name
Test status
Simulation time 4815189184 ps
CPU time 361.41 seconds
Started Nov 22 03:11:53 PM PST 23
Finished Nov 22 03:17:58 PM PST 23
Peak memory 557184 kb
Host smart-8f09b830-7256-41d8-bb91-402a985675a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7468673046621425894418219239602732219562201017741675959194241227617204154561 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_rand_reset.746867304662142589441821923960273221956220101774167595919424122
7617204154561
Directory /workspace/83.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.83411529040168711524721267260251304609767798838463118997403830645769633150033
Short name T865
Test name
Test status
Simulation time 4815189184 ps
CPU time 301.14 seconds
Started Nov 22 03:11:43 PM PST 23
Finished Nov 22 03:16:45 PM PST 23
Peak memory 559664 kb
Host smart-fc333690-1167-493b-9f22-f5a0d199bdf5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83411529040168711524721267260251304609767798838463118997403830645769633150033 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_reset_error.834115290401687115247212672602513046097677988384631189974038
30645769633150033
Directory /workspace/83.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.63418654901342742041818908469552356501111682339310629435176018210743798470057
Short name T206
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.96 seconds
Started Nov 22 03:11:46 PM PST 23
Finished Nov 22 03:12:35 PM PST 23
Peak memory 553716 kb
Host smart-d0fa1a9e-28c2-4af4-8921-c8d0de063489
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63418654901342742041818908469552356501111682339310629435176018210743798470057 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.63418654901342742041818908469552356501111682339310629435176018210743798470057
Directory /workspace/83.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device.45471863931510348060245153947431084910265780505488380043337946868856601176303
Short name T163
Test name
Test status
Simulation time 2590995727 ps
CPU time 108.67 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:13:58 PM PST 23
Peak memory 554852 kb
Host smart-6e44263f-240e-4a0d-8fd4-dd89826da559
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45471863931510348060245153947431084910265780505488380043337946868856601176303 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.45471863931510348060245153947431084910265780505488380043337946868856601176303
Directory /workspace/84.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.67901505186126436022503177499559564358071282694889652573159125680269213328129
Short name T1453
Test name
Test status
Simulation time 115195295727 ps
CPU time 2016.54 seconds
Started Nov 22 03:11:48 PM PST 23
Finished Nov 22 03:45:26 PM PST 23
Peak memory 554700 kb
Host smart-82a372dd-0106-41ef-9871-cf18078fc96a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67901505186126436022503177499559564358071282694889652573159125680269213328129 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device_slow_rsp.67901505186126436022503177499559564358071282694889652573159125680269213328129
Directory /workspace/84.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.25166593549494702414165368274021592006014286327994723403239843305683481595703
Short name T1178
Test name
Test status
Simulation time 1171215727 ps
CPU time 48.15 seconds
Started Nov 22 03:11:51 PM PST 23
Finished Nov 22 03:12:41 PM PST 23
Peak memory 553488 kb
Host smart-207ee34c-8296-4d65-93cc-27528fc68131
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166593549494702414165368274021592006014286327994723403239843305683481595703 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr.25166593549494702414165368274021592006014286327994723403239843305683481595703
Directory /workspace/84.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_random.40940065109616720908990756247786057741304251459936298842478885648702847531446
Short name T1423
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.28 seconds
Started Nov 22 03:11:53 PM PST 23
Finished Nov 22 03:13:10 PM PST 23
Peak memory 553480 kb
Host smart-9c436167-2f08-4ac0-9792-61372685cf2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40940065109616720908990756247786057741304251459936298842478885648702847531446 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 84.xbar_error_random.40940065109616720908990756247786057741304251459936298842478885648702847531446
Directory /workspace/84.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random.17013323627342306555176123559682703344153387495603253772568065051231032942243
Short name T1693
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.78 seconds
Started Nov 22 03:11:42 PM PST 23
Finished Nov 22 03:13:01 PM PST 23
Peak memory 553812 kb
Host smart-a1ba1666-bdbc-4a0d-a516-502810c5cb70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17013323627342306555176123559682703344153387495603253772568065051231032942243 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 84.xbar_random.17013323627342306555176123559682703344153387495603253772568065051231032942243
Directory /workspace/84.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.89245234387921939044721677500686530956379320872011419379754124203930040715655
Short name T50
Test name
Test status
Simulation time 97702135727 ps
CPU time 1184.73 seconds
Started Nov 22 03:11:46 PM PST 23
Finished Nov 22 03:31:32 PM PST 23
Peak memory 553712 kb
Host smart-23424ac9-66c3-4ffa-9f85-9a90079b4383
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89245234387921939044721677500686530956379320872011419379754124203930040715655 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.89245234387921939044721677500686530956379320872011419379754124203930040715655
Directory /workspace/84.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.6434860341549503729728138759236739710620293291468976957925808948088483324537
Short name T1667
Test name
Test status
Simulation time 60576345727 ps
CPU time 1104.04 seconds
Started Nov 22 03:11:53 PM PST 23
Finished Nov 22 03:30:21 PM PST 23
Peak memory 553692 kb
Host smart-156881fb-dcfd-40ca-8457-5e00ff1ecca2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6434860341549503729728138759236739710620293291468976957925808948088483324537 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.6434860341549503729728138759236739710620293291468976957925808948088483324537
Directory /workspace/84.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.12628919865924798381610115015072472662154562971373313940258554675861356978357
Short name T877
Test name
Test status
Simulation time 556965727 ps
CPU time 45.11 seconds
Started Nov 22 03:11:41 PM PST 23
Finished Nov 22 03:12:27 PM PST 23
Peak memory 553668 kb
Host smart-245c5b9b-9478-4cc7-99cd-3b55d69e7206
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12628919865924798381610115015072472662154562971373313940258554675861356978357 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_delays.12628919865924798381610115015072472662154562971373313940258554675861356978357
Directory /workspace/84.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_same_source.115674701299236611230082037478898108915172038112396581868230248580972791835521
Short name T1189
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.36 seconds
Started Nov 22 03:11:52 PM PST 23
Finished Nov 22 03:13:10 PM PST 23
Peak memory 553740 kb
Host smart-6aade497-1c8f-44ee-9ab0-5d91c658a66a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115674701299236611230082037478898108915172038112396581868230248580972791835521 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.115674701299236611230082037478898108915172038112396581868230248580972791835521
Directory /workspace/84.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke.54621495828420550524788468958290366460302897418242814028615946830109932147977
Short name T438
Test name
Test status
Simulation time 196985727 ps
CPU time 8.04 seconds
Started Nov 22 03:11:41 PM PST 23
Finished Nov 22 03:11:49 PM PST 23
Peak memory 552364 kb
Host smart-a2af0ba7-b17d-4c42-9c05-52362f84b1e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54621495828420550524788468958290366460302897418242814028615946830109932147977 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 84.xbar_smoke.54621495828420550524788468958290366460302897418242814028615946830109932147977
Directory /workspace/84.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.22086746339436951854457004697721124266479034921241500398694077200312109823022
Short name T1722
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.22 seconds
Started Nov 22 03:11:45 PM PST 23
Finished Nov 22 03:13:18 PM PST 23
Peak memory 552476 kb
Host smart-8ad8c023-f0ce-4b2a-ac5d-a2b0c3284d6c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22086746339436951854457004697721124266479034921241500398694077200312109823022 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.22086746339436951854457004697721124266479034921241500398694077200312109823022
Directory /workspace/84.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.8103773051516285996010243930255633889926084489637288992961873431369144766672
Short name T161
Test name
Test status
Simulation time 4856075727 ps
CPU time 80.92 seconds
Started Nov 22 03:11:45 PM PST 23
Finished Nov 22 03:13:06 PM PST 23
Peak memory 552388 kb
Host smart-81e445e2-7510-4f42-b484-ab03f7cdc8ce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8103773051516285996010243930255633889926084489637288992961873431369144766672 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.8103773051516285996010243930255633889926084489637288992961873431369144766672
Directory /workspace/84.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.103235381758119919965557297243797441486699656814266809423890724776860449298992
Short name T1270
Test name
Test status
Simulation time 45555727 ps
CPU time 5.96 seconds
Started Nov 22 03:11:44 PM PST 23
Finished Nov 22 03:11:50 PM PST 23
Peak memory 552260 kb
Host smart-b65be749-48d6-4968-904e-8342bf457388
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103235381758119919965557297243797441486699656814266809423890724776860449298992 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.103235381758119919965557297243797441486699656814266809423890724776860449298992
Directory /workspace/84.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all.99896535215117742556954493506319707204620052259714339895471567517881063251640
Short name T601
Test name
Test status
Simulation time 13992004073 ps
CPU time 524.87 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:20:55 PM PST 23
Peak memory 555920 kb
Host smart-2bae20aa-5b67-4380-92d8-53da3d19ec7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99896535215117742556954493506319707204620052259714339895471567517881063251640 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.99896535215117742556954493506319707204620052259714339895471567517881063251640
Directory /workspace/84.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.26734062244754663600694002641972434257288741431353713662370012912823104966107
Short name T1717
Test name
Test status
Simulation time 13999524073 ps
CPU time 478.51 seconds
Started Nov 22 03:12:02 PM PST 23
Finished Nov 22 03:20:01 PM PST 23
Peak memory 555736 kb
Host smart-5fa728fc-2a57-4ef1-9e41-a5e640e2278c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26734062244754663600694002641972434257288741431353713662370012912823104966107 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.26734062244754663600694002641972434257288741431353713662370012912823104966107
Directory /workspace/84.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.13671495407680292860894524684365065072620299574120803354245550548714275676296
Short name T1630
Test name
Test status
Simulation time 4815189184 ps
CPU time 374.55 seconds
Started Nov 22 03:11:51 PM PST 23
Finished Nov 22 03:18:07 PM PST 23
Peak memory 557308 kb
Host smart-92fa5bd2-1587-4ffb-8974-db51b9616fc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13671495407680292860894524684365065072620299574120803354245550548714275676296 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_rand_reset.13671495407680292860894524684365065072620299574120803354245550
548714275676296
Directory /workspace/84.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.30764225351294138466780810346578915546877660640212982672060390415801539227014
Short name T357
Test name
Test status
Simulation time 4815189184 ps
CPU time 317.09 seconds
Started Nov 22 03:11:52 PM PST 23
Finished Nov 22 03:17:10 PM PST 23
Peak memory 559812 kb
Host smart-676b9877-30ea-45ad-9745-d85b014b30f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30764225351294138466780810346578915546877660640212982672060390415801539227014 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_reset_error.307642253512941384667808103465789155468776606402129826720603
90415801539227014
Directory /workspace/84.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.69354099119413027481077651205117195426940259441176269446556362033336052003386
Short name T1563
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.99 seconds
Started Nov 22 03:11:57 PM PST 23
Finished Nov 22 03:12:46 PM PST 23
Peak memory 553544 kb
Host smart-2453eb23-7759-46b4-8236-a41c8629315a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69354099119413027481077651205117195426940259441176269446556362033336052003386 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.69354099119413027481077651205117195426940259441176269446556362033336052003386
Directory /workspace/84.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device.70261213055635291865471327133630640720154433191831438042497536470702998860893
Short name T937
Test name
Test status
Simulation time 2590995727 ps
CPU time 111.86 seconds
Started Nov 22 03:11:52 PM PST 23
Finished Nov 22 03:13:45 PM PST 23
Peak memory 554776 kb
Host smart-99d231ab-7c65-4e3b-9a4e-08fb2c130735
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70261213055635291865471327133630640720154433191831438042497536470702998860893 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.70261213055635291865471327133630640720154433191831438042497536470702998860893
Directory /workspace/85.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.75891805380514654960612282833473897727395449420133510521983661346403031811774
Short name T79
Test name
Test status
Simulation time 115195295727 ps
CPU time 2054.45 seconds
Started Nov 22 03:12:01 PM PST 23
Finished Nov 22 03:46:17 PM PST 23
Peak memory 554724 kb
Host smart-f2ca575e-dd7d-499d-b820-1527690bea6d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75891805380514654960612282833473897727395449420133510521983661346403031811774 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device_slow_rsp.75891805380514654960612282833473897727395449420133510521983661346403031811774
Directory /workspace/85.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.37848118919030927533237119178635628152065495896349719932115457842523567068622
Short name T243
Test name
Test status
Simulation time 1171215727 ps
CPU time 49.46 seconds
Started Nov 22 03:12:00 PM PST 23
Finished Nov 22 03:12:51 PM PST 23
Peak memory 553572 kb
Host smart-d3eac786-f8e9-47de-89be-ceebb36b3f31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37848118919030927533237119178635628152065495896349719932115457842523567068622 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.37848118919030927533237119178635628152065495896349719932115457842523567068622
Directory /workspace/85.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_random.49358069475169174609296996251872977413478802261327689669888278754985569909231
Short name T452
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.64 seconds
Started Nov 22 03:12:00 PM PST 23
Finished Nov 22 03:13:14 PM PST 23
Peak memory 553448 kb
Host smart-def74961-3e56-4845-aed5-29ad3ec2995b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49358069475169174609296996251872977413478802261327689669888278754985569909231 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 85.xbar_error_random.49358069475169174609296996251872977413478802261327689669888278754985569909231
Directory /workspace/85.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random.54693322214720550019766459947391278004177227546726937160220490440553977783342
Short name T1172
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.2 seconds
Started Nov 22 03:11:56 PM PST 23
Finished Nov 22 03:13:13 PM PST 23
Peak memory 553576 kb
Host smart-1cb01a8a-8e46-443b-af2c-429edfe890d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54693322214720550019766459947391278004177227546726937160220490440553977783342 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 85.xbar_random.54693322214720550019766459947391278004177227546726937160220490440553977783342
Directory /workspace/85.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.36159511529056140694114198438032337064845533991391707195026209167637706758302
Short name T1100
Test name
Test status
Simulation time 97702135727 ps
CPU time 1114.86 seconds
Started Nov 22 03:11:57 PM PST 23
Finished Nov 22 03:30:33 PM PST 23
Peak memory 553496 kb
Host smart-880461e6-fa65-4677-a638-67cb14ff1a24
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36159511529056140694114198438032337064845533991391707195026209167637706758302 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.36159511529056140694114198438032337064845533991391707195026209167637706758302
Directory /workspace/85.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.35457799299053338246859167695482104434836980081433619274843789317017942631170
Short name T118
Test name
Test status
Simulation time 60576345727 ps
CPU time 994.81 seconds
Started Nov 22 03:11:51 PM PST 23
Finished Nov 22 03:28:27 PM PST 23
Peak memory 553676 kb
Host smart-562bee3f-15de-4467-998e-4ec3fd01e66d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35457799299053338246859167695482104434836980081433619274843789317017942631170 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.35457799299053338246859167695482104434836980081433619274843789317017942631170
Directory /workspace/85.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.14344709413275067033632111262810811797868951837964493340982368433386853921515
Short name T543
Test name
Test status
Simulation time 556965727 ps
CPU time 43.84 seconds
Started Nov 22 03:11:58 PM PST 23
Finished Nov 22 03:12:44 PM PST 23
Peak memory 553732 kb
Host smart-471afdcf-3629-4da9-a0c9-44f65eba4ea6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14344709413275067033632111262810811797868951837964493340982368433386853921515 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_delays.14344709413275067033632111262810811797868951837964493340982368433386853921515
Directory /workspace/85.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_same_source.20018601841759941216476139390518947087837553513894723147766893832102445225377
Short name T1603
Test name
Test status
Simulation time 2498784073 ps
CPU time 73.85 seconds
Started Nov 22 03:11:50 PM PST 23
Finished Nov 22 03:13:05 PM PST 23
Peak memory 553640 kb
Host smart-113a5e3d-9300-4f38-ad60-09fec4ce5b28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018601841759941216476139390518947087837553513894723147766893832102445225377 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.20018601841759941216476139390518947087837553513894723147766893832102445225377
Directory /workspace/85.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke.99173287512053798040683588587512876400299878722931746453399409475264286006002
Short name T505
Test name
Test status
Simulation time 196985727 ps
CPU time 8.33 seconds
Started Nov 22 03:11:51 PM PST 23
Finished Nov 22 03:12:00 PM PST 23
Peak memory 552292 kb
Host smart-50b727c8-6393-45a3-a8e4-04b2274c1b03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99173287512053798040683588587512876400299878722931746453399409475264286006002 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 85.xbar_smoke.99173287512053798040683588587512876400299878722931746453399409475264286006002
Directory /workspace/85.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.28472847745067975105811262836324028978429560951968779344900287039673893715283
Short name T788
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.15 seconds
Started Nov 22 03:12:00 PM PST 23
Finished Nov 22 03:13:34 PM PST 23
Peak memory 552204 kb
Host smart-efa9329b-5bc2-42c7-94cc-2833618261ea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28472847745067975105811262836324028978429560951968779344900287039673893715283 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.28472847745067975105811262836324028978429560951968779344900287039673893715283
Directory /workspace/85.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.57724478807150667266853500274832842360792980464669706549294424075400475234516
Short name T764
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.6 seconds
Started Nov 22 03:11:47 PM PST 23
Finished Nov 22 03:13:18 PM PST 23
Peak memory 552412 kb
Host smart-c7de4c3c-ee3e-4fdd-baa2-721502334cde
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57724478807150667266853500274832842360792980464669706549294424075400475234516 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.57724478807150667266853500274832842360792980464669706549294424075400475234516
Directory /workspace/85.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.37065785107920100931118116132639326548795233657984272055109578156057972150863
Short name T953
Test name
Test status
Simulation time 45555727 ps
CPU time 5.79 seconds
Started Nov 22 03:11:51 PM PST 23
Finished Nov 22 03:11:59 PM PST 23
Peak memory 552372 kb
Host smart-5d7f9560-b41d-414b-a60f-aa2fdaeeefee
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37065785107920100931118116132639326548795233657984272055109578156057972150863 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays.37065785107920100931118116132639326548795233657984272055109578156057972150863
Directory /workspace/85.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all.102342479290416126729828206443799229372599822466936574172059628438187579362988
Short name T1056
Test name
Test status
Simulation time 13992004073 ps
CPU time 497.58 seconds
Started Nov 22 03:12:00 PM PST 23
Finished Nov 22 03:20:19 PM PST 23
Peak memory 555908 kb
Host smart-9dd750cf-e463-494f-8ecb-68ba57836ea3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102342479290416126729828206443799229372599822466936574172059628438187579362988 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.102342479290416126729828206443799229372599822466936574172059628438187579362988
Directory /workspace/85.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.113085144382629044717061291329481175864018694447121327261690606575325598122844
Short name T302
Test name
Test status
Simulation time 13999524073 ps
CPU time 492.68 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:20:23 PM PST 23
Peak memory 555724 kb
Host smart-e643e549-7f5d-4456-b5c1-4b66e14f39a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113085144382629044717061291329481175864018694447121327261690606575325598122844 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.113085144382629044717061291329481175864018694447121327261690606575325598122844
Directory /workspace/85.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.55044443394838898468896703955950267839457368459191539001199414767424891091327
Short name T1389
Test name
Test status
Simulation time 4815189184 ps
CPU time 351.56 seconds
Started Nov 22 03:11:52 PM PST 23
Finished Nov 22 03:17:45 PM PST 23
Peak memory 557268 kb
Host smart-9b111584-08cd-485d-aee6-f851c39cc441
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55044443394838898468896703955950267839457368459191539001199414767424891091327 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_rand_reset.55044443394838898468896703955950267839457368459191539001199414
767424891091327
Directory /workspace/85.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.79751300528247813531888586713405714643853949451086810884998071186794820562625
Short name T1042
Test name
Test status
Simulation time 4815189184 ps
CPU time 314.23 seconds
Started Nov 22 03:11:49 PM PST 23
Finished Nov 22 03:17:04 PM PST 23
Peak memory 559644 kb
Host smart-18d00e7f-b634-45f3-91bb-8cc2014c7590
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79751300528247813531888586713405714643853949451086810884998071186794820562625 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_reset_error.797513005282478135318885867134057146438539494510868108849980
71186794820562625
Directory /workspace/85.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.18129753440348483273413324629298189840385682320016354398094740420058130281894
Short name T1497
Test name
Test status
Simulation time 1176995727 ps
CPU time 48 seconds
Started Nov 22 03:11:57 PM PST 23
Finished Nov 22 03:12:46 PM PST 23
Peak memory 553544 kb
Host smart-0d5ca292-8ba7-4375-922b-cb72c7ddeb21
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18129753440348483273413324629298189840385682320016354398094740420058130281894 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.18129753440348483273413324629298189840385682320016354398094740420058130281894
Directory /workspace/85.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device.107492433958156372850138825605659488378098970521736934786944201734659269728666
Short name T1143
Test name
Test status
Simulation time 2590995727 ps
CPU time 108.65 seconds
Started Nov 22 03:11:50 PM PST 23
Finished Nov 22 03:13:39 PM PST 23
Peak memory 554804 kb
Host smart-fa2e0647-8c49-4244-a84d-50da061718d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107492433958156372850138825605659488378098970521736934786944201734659269728666 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device.107492433958156372850138825605659488378098970521736934786944201734659269728666
Directory /workspace/86.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.91956044170548634162026311719518465969530609699714306990185174548048380560384
Short name T1164
Test name
Test status
Simulation time 115195295727 ps
CPU time 2022.33 seconds
Started Nov 22 03:11:59 PM PST 23
Finished Nov 22 03:45:44 PM PST 23
Peak memory 554760 kb
Host smart-5b63a2f8-771e-4385-8559-5e44d3c764c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91956044170548634162026311719518465969530609699714306990185174548048380560384 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device_slow_rsp.91956044170548634162026311719518465969530609699714306990185174548048380560384
Directory /workspace/86.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.15489618452256152595440399705035212961955060584781054392411698958884269844757
Short name T729
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.62 seconds
Started Nov 22 03:12:00 PM PST 23
Finished Nov 22 03:12:45 PM PST 23
Peak memory 553472 kb
Host smart-208ce219-bd5e-4f8e-b363-04ba1d4b9eba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15489618452256152595440399705035212961955060584781054392411698958884269844757 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr.15489618452256152595440399705035212961955060584781054392411698958884269844757
Directory /workspace/86.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_random.106786993276221298155968612448268610689566977457999906939438980444883880200367
Short name T1295
Test name
Test status
Simulation time 2231375727 ps
CPU time 82.16 seconds
Started Nov 22 03:12:00 PM PST 23
Finished Nov 22 03:13:24 PM PST 23
Peak memory 553540 kb
Host smart-5097a8ae-ac70-4ba3-a627-606d392ff2c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106786993276221298155968612448268610689566977457999906939438980444883880200367 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 86.xbar_error_random.106786993276221298155968612448268610689566977457999906939438980444883880200367
Directory /workspace/86.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random.46140376599245248272068954771593641096839745158991061032750153883728222304808
Short name T1899
Test name
Test status
Simulation time 2231375727 ps
CPU time 87.94 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:13:38 PM PST 23
Peak memory 553740 kb
Host smart-71ea2ba8-3eee-4efe-a580-5b8aa74ebf09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46140376599245248272068954771593641096839745158991061032750153883728222304808 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 86.xbar_random.46140376599245248272068954771593641096839745158991061032750153883728222304808
Directory /workspace/86.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.65900166285764629245087755270988294110802009048625036658814125556521521544858
Short name T1118
Test name
Test status
Simulation time 97702135727 ps
CPU time 1171.07 seconds
Started Nov 22 03:11:54 PM PST 23
Finished Nov 22 03:31:29 PM PST 23
Peak memory 553540 kb
Host smart-333b7b7a-4596-4b80-aeec-79e1e580db6c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65900166285764629245087755270988294110802009048625036658814125556521521544858 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.65900166285764629245087755270988294110802009048625036658814125556521521544858
Directory /workspace/86.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.54824571644453500582981981341249237026695981146465367499247568512488224445153
Short name T604
Test name
Test status
Simulation time 60576345727 ps
CPU time 1114.75 seconds
Started Nov 22 03:11:50 PM PST 23
Finished Nov 22 03:30:26 PM PST 23
Peak memory 553700 kb
Host smart-18ef6b4c-b24a-478a-bdd9-74c5916eb2e0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54824571644453500582981981341249237026695981146465367499247568512488224445153 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.54824571644453500582981981341249237026695981146465367499247568512488224445153
Directory /workspace/86.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.38931396959388932416765682587543562335031402054130442834338207512450235609764
Short name T1866
Test name
Test status
Simulation time 556965727 ps
CPU time 53.44 seconds
Started Nov 22 03:12:01 PM PST 23
Finished Nov 22 03:12:56 PM PST 23
Peak memory 553688 kb
Host smart-3fd06004-0fc9-413f-b844-d2c448b675ff
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38931396959388932416765682587543562335031402054130442834338207512450235609764 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_delays.38931396959388932416765682587543562335031402054130442834338207512450235609764
Directory /workspace/86.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_same_source.86382403101578089316911141925225797199586117270088179651757683471154823019809
Short name T407
Test name
Test status
Simulation time 2498784073 ps
CPU time 74.77 seconds
Started Nov 22 03:12:00 PM PST 23
Finished Nov 22 03:13:17 PM PST 23
Peak memory 553700 kb
Host smart-fdc1cb93-9e57-443c-8851-5e8931d6fcd7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86382403101578089316911141925225797199586117270088179651757683471154823019809 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.86382403101578089316911141925225797199586117270088179651757683471154823019809
Directory /workspace/86.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke.28182098580966339604720514427680857410364586917807216840385857750170201613504
Short name T1332
Test name
Test status
Simulation time 196985727 ps
CPU time 8.99 seconds
Started Nov 22 03:12:01 PM PST 23
Finished Nov 22 03:12:11 PM PST 23
Peak memory 552332 kb
Host smart-7909eacb-85d5-48ec-8e66-5df2c9545a7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28182098580966339604720514427680857410364586917807216840385857750170201613504 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 86.xbar_smoke.28182098580966339604720514427680857410364586917807216840385857750170201613504
Directory /workspace/86.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.105728110787642750230276495246073234506015167712611255029449652457691720115990
Short name T938
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.15 seconds
Started Nov 22 03:11:59 PM PST 23
Finished Nov 22 03:13:34 PM PST 23
Peak memory 552404 kb
Host smart-d8a540c2-d2ec-423f-bbcd-1632953b7774
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105728110787642750230276495246073234506015167712611255029449652457691720115990 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.105728110787642750230276495246073234506015167712611255029449652457691720115990
Directory /workspace/86.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.112321098516192127644035958776945583453112908382740596509025614824124443951662
Short name T1063
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.18 seconds
Started Nov 22 03:11:59 PM PST 23
Finished Nov 22 03:13:28 PM PST 23
Peak memory 552408 kb
Host smart-8b3d36d6-d041-4a2c-b2a4-5b54dbd061aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112321098516192127644035958776945583453112908382740596509025614824124443951662 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.112321098516192127644035958776945583453112908382740596509025614824124443951662
Directory /workspace/86.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.101778810115161407643982890351265130072634495297811290933634999367835704697263
Short name T1549
Test name
Test status
Simulation time 45555727 ps
CPU time 6.18 seconds
Started Nov 22 03:11:50 PM PST 23
Finished Nov 22 03:11:57 PM PST 23
Peak memory 552344 kb
Host smart-268c5cfe-bb47-45ee-96a3-e06456e80c83
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101778810115161407643982890351265130072634495297811290933634999367835704697263 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays.101778810115161407643982890351265130072634495297811290933634999367835704697263
Directory /workspace/86.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all.101833396093706336919944839239781680851085918571473701453093490921828330334656
Short name T1604
Test name
Test status
Simulation time 13992004073 ps
CPU time 497.38 seconds
Started Nov 22 03:11:54 PM PST 23
Finished Nov 22 03:20:15 PM PST 23
Peak memory 555856 kb
Host smart-cebfd6b0-d0e8-46ef-88e2-9c16d8e8752e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101833396093706336919944839239781680851085918571473701453093490921828330334656 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.101833396093706336919944839239781680851085918571473701453093490921828330334656
Directory /workspace/86.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.111520128159924206496843097645839574044153550840791488312883106885287587077035
Short name T1033
Test name
Test status
Simulation time 13999524073 ps
CPU time 492.2 seconds
Started Nov 22 03:12:10 PM PST 23
Finished Nov 22 03:20:23 PM PST 23
Peak memory 555724 kb
Host smart-0aa2e272-4c10-4d71-933a-210a6825c5ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111520128159924206496843097645839574044153550840791488312883106885287587077035 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.111520128159924206496843097645839574044153550840791488312883106885287587077035
Directory /workspace/86.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.112766776697542279654776234791643407829936435248555218737887314835230859399659
Short name T827
Test name
Test status
Simulation time 4815189184 ps
CPU time 382.69 seconds
Started Nov 22 03:12:10 PM PST 23
Finished Nov 22 03:18:33 PM PST 23
Peak memory 557168 kb
Host smart-ef48bbd8-0ae0-493f-beb9-9a974c518470
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112766776697542279654776234791643407829936435248555218737887314835230859399659 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_rand_reset.1127667766975422796547762347916434078299364352485552187378873
14835230859399659
Directory /workspace/86.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.31199642585003713076060683325663670672518468844352729669248760945351970464066
Short name T47
Test name
Test status
Simulation time 4815189184 ps
CPU time 307.21 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:17:17 PM PST 23
Peak memory 559716 kb
Host smart-71dc179f-4d6f-43bd-a2b8-b2bcddb64733
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31199642585003713076060683325663670672518468844352729669248760945351970464066 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_reset_error.311996425850037130760606833256636706725184688443527296692487
60945351970464066
Directory /workspace/86.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.80090182470459351611845729599598783831827128050765743947635953353347657384431
Short name T986
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.55 seconds
Started Nov 22 03:11:59 PM PST 23
Finished Nov 22 03:12:50 PM PST 23
Peak memory 553740 kb
Host smart-f6aafda4-5c50-4d63-afd4-39d42084a9ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80090182470459351611845729599598783831827128050765743947635953353347657384431 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.80090182470459351611845729599598783831827128050765743947635953353347657384431
Directory /workspace/86.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device.57615564341001104544968897014633034576191050884662313097261105026084172802854
Short name T1583
Test name
Test status
Simulation time 2590995727 ps
CPU time 109.57 seconds
Started Nov 22 03:12:08 PM PST 23
Finished Nov 22 03:13:59 PM PST 23
Peak memory 554796 kb
Host smart-63666a8c-46ae-4910-af12-1a186e9e1ba6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57615564341001104544968897014633034576191050884662313097261105026084172802854 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device.57615564341001104544968897014633034576191050884662313097261105026084172802854
Directory /workspace/87.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.33590031331543464424303691543432513461015523759921323596242675712007607324004
Short name T786
Test name
Test status
Simulation time 115195295727 ps
CPU time 2037.96 seconds
Started Nov 22 03:12:29 PM PST 23
Finished Nov 22 03:46:31 PM PST 23
Peak memory 554760 kb
Host smart-6aac19b8-07ae-4779-be1c-707b639fa1fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33590031331543464424303691543432513461015523759921323596242675712007607324004 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device_slow_rsp.33590031331543464424303691543432513461015523759921323596242675712007607324004
Directory /workspace/87.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.41662871221351721474096473604725436673585675412595911901702695014169256568838
Short name T654
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.32 seconds
Started Nov 22 03:12:29 PM PST 23
Finished Nov 22 03:13:18 PM PST 23
Peak memory 553472 kb
Host smart-edc64331-2e1c-4a9a-9f58-10d56e65bc3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41662871221351721474096473604725436673585675412595911901702695014169256568838 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr.41662871221351721474096473604725436673585675412595911901702695014169256568838
Directory /workspace/87.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_random.16610874348059840741183632191224185028914797727295030105155293384773805918355
Short name T115
Test name
Test status
Simulation time 2231375727 ps
CPU time 69.7 seconds
Started Nov 22 03:12:10 PM PST 23
Finished Nov 22 03:13:20 PM PST 23
Peak memory 553120 kb
Host smart-94b56867-ed27-403c-81f9-c455564f3394
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16610874348059840741183632191224185028914797727295030105155293384773805918355 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 87.xbar_error_random.16610874348059840741183632191224185028914797727295030105155293384773805918355
Directory /workspace/87.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random.30854516991695161503745448344341110502540844381436690026442155419238374598566
Short name T1655
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.39 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:13:27 PM PST 23
Peak memory 553756 kb
Host smart-5b063a1e-ef07-4c5e-8eb8-b37966e8980a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30854516991695161503745448344341110502540844381436690026442155419238374598566 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 87.xbar_random.30854516991695161503745448344341110502540844381436690026442155419238374598566
Directory /workspace/87.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.38538483809183132016792108410749167190065216596579187807176848881522309760729
Short name T1475
Test name
Test status
Simulation time 97702135727 ps
CPU time 1167.84 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:31:38 PM PST 23
Peak memory 553628 kb
Host smart-6440fb0b-6819-4aaf-8578-a4b0d94e7eba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538483809183132016792108410749167190065216596579187807176848881522309760729 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.38538483809183132016792108410749167190065216596579187807176848881522309760729
Directory /workspace/87.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.66673216710446618682620155620150620352081828944826118128211487385471631232862
Short name T1302
Test name
Test status
Simulation time 60576345727 ps
CPU time 1104.64 seconds
Started Nov 22 03:12:11 PM PST 23
Finished Nov 22 03:30:36 PM PST 23
Peak memory 553676 kb
Host smart-215601ae-9b24-4280-a2dd-1a61d8843b35
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66673216710446618682620155620150620352081828944826118128211487385471631232862 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.66673216710446618682620155620150620352081828944826118128211487385471631232862
Directory /workspace/87.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.35970051106741498300706243277679389383543326062394047949107233647162555497117
Short name T868
Test name
Test status
Simulation time 556965727 ps
CPU time 44.4 seconds
Started Nov 22 03:12:11 PM PST 23
Finished Nov 22 03:12:56 PM PST 23
Peak memory 553676 kb
Host smart-80d5c534-4854-461d-a137-d957cf8b4309
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35970051106741498300706243277679389383543326062394047949107233647162555497117 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_delays.35970051106741498300706243277679389383543326062394047949107233647162555497117
Directory /workspace/87.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_same_source.24443269864998904921386054962144788337737706656394183064784099064762824193683
Short name T540
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.24 seconds
Started Nov 22 03:12:11 PM PST 23
Finished Nov 22 03:13:28 PM PST 23
Peak memory 553764 kb
Host smart-d0279dd0-7cd7-4516-bde7-b0c8405d6ab1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443269864998904921386054962144788337737706656394183064784099064762824193683 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.24443269864998904921386054962144788337737706656394183064784099064762824193683
Directory /workspace/87.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke.111808059642105711453168612455444051074151458164339296953684951691440702294907
Short name T254
Test name
Test status
Simulation time 196985727 ps
CPU time 8.21 seconds
Started Nov 22 03:12:29 PM PST 23
Finished Nov 22 03:12:41 PM PST 23
Peak memory 552352 kb
Host smart-faf22c04-8dbe-421e-b9df-fdc0f0531c79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111808059642105711453168612455444051074151458164339296953684951691440702294907 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 87.xbar_smoke.111808059642105711453168612455444051074151458164339296953684951691440702294907
Directory /workspace/87.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.99924841426374623896178381066969005959448154849366005077787373884199462952914
Short name T1925
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.46 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:13:39 PM PST 23
Peak memory 552404 kb
Host smart-ce1d6b3c-b830-4e24-be80-46c2dc613eb0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99924841426374623896178381066969005959448154849366005077787373884199462952914 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.99924841426374623896178381066969005959448154849366005077787373884199462952914
Directory /workspace/87.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.104832531077073654987837843725245577859335425720974618036696880584533584062536
Short name T1029
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.14 seconds
Started Nov 22 03:12:10 PM PST 23
Finished Nov 22 03:13:38 PM PST 23
Peak memory 552476 kb
Host smart-5caaf0e1-4d27-4566-84d5-ab6698a62ee2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104832531077073654987837843725245577859335425720974618036696880584533584062536 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.104832531077073654987837843725245577859335425720974618036696880584533584062536
Directory /workspace/87.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.11233901231177155797346011037015512862298526291712034781203708138555939714890
Short name T253
Test name
Test status
Simulation time 45555727 ps
CPU time 5.91 seconds
Started Nov 22 03:12:13 PM PST 23
Finished Nov 22 03:12:20 PM PST 23
Peak memory 552188 kb
Host smart-3f60d0e1-d959-4c3d-90cb-95f087146fa5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11233901231177155797346011037015512862298526291712034781203708138555939714890 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays.11233901231177155797346011037015512862298526291712034781203708138555939714890
Directory /workspace/87.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all.24205750988212872030996782446606745299921460446596961395055307108849743491914
Short name T68
Test name
Test status
Simulation time 13992004073 ps
CPU time 482.07 seconds
Started Nov 22 03:12:15 PM PST 23
Finished Nov 22 03:20:17 PM PST 23
Peak memory 555908 kb
Host smart-c4f7121d-194f-4647-9cd9-470e0c14068c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205750988212872030996782446606745299921460446596961395055307108849743491914 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.24205750988212872030996782446606745299921460446596961395055307108849743491914
Directory /workspace/87.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.25471523394918914630972250808581695745100580324924817676023302026682594723373
Short name T1376
Test name
Test status
Simulation time 13999524073 ps
CPU time 476.23 seconds
Started Nov 22 03:12:10 PM PST 23
Finished Nov 22 03:20:07 PM PST 23
Peak memory 555824 kb
Host smart-0ec0fc05-72ea-438d-9301-d536bc1bfd7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25471523394918914630972250808581695745100580324924817676023302026682594723373 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.25471523394918914630972250808581695745100580324924817676023302026682594723373
Directory /workspace/87.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.84492670231632384807811394000169513802968552452895790929292256962703319669815
Short name T96
Test name
Test status
Simulation time 4815189184 ps
CPU time 352.51 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:18:02 PM PST 23
Peak memory 557272 kb
Host smart-ea68d994-8256-4614-a14a-4661e3e950d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84492670231632384807811394000169513802968552452895790929292256962703319669815 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_rand_reset.84492670231632384807811394000169513802968552452895790929292256
962703319669815
Directory /workspace/87.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.40856423482600653246422577958657642298773526329371909746952595673189354954495
Short name T166
Test name
Test status
Simulation time 4815189184 ps
CPU time 297.93 seconds
Started Nov 22 03:12:11 PM PST 23
Finished Nov 22 03:17:09 PM PST 23
Peak memory 559304 kb
Host smart-3b6390dd-73e5-453e-9deb-3314384a49d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40856423482600653246422577958657642298773526329371909746952595673189354954495 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_reset_error.408564234826006532464225779586576422987735263293719097469525
95673189354954495
Directory /workspace/87.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.33278106209811438550390316275641113452338100513771145418269478589379320649984
Short name T467
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.11 seconds
Started Nov 22 03:12:11 PM PST 23
Finished Nov 22 03:13:01 PM PST 23
Peak memory 553696 kb
Host smart-548826f8-a73d-458d-9573-9b2ab6e5431f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33278106209811438550390316275641113452338100513771145418269478589379320649984 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.33278106209811438550390316275641113452338100513771145418269478589379320649984
Directory /workspace/87.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device.52628725366621258327451491459981105529649533061353771969629501850798698689561
Short name T1728
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.26 seconds
Started Nov 22 03:12:28 PM PST 23
Finished Nov 22 03:14:17 PM PST 23
Peak memory 554888 kb
Host smart-5df1afae-ceea-4ce7-b477-b94987833f08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52628725366621258327451491459981105529649533061353771969629501850798698689561 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.52628725366621258327451491459981105529649533061353771969629501850798698689561
Directory /workspace/88.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.24980014236881749289033550279854064137386878948112265468899487755415901082299
Short name T1874
Test name
Test status
Simulation time 115195295727 ps
CPU time 2055.28 seconds
Started Nov 22 03:12:25 PM PST 23
Finished Nov 22 03:46:44 PM PST 23
Peak memory 554884 kb
Host smart-76da2aa7-fe80-4a13-90f7-8d2bdcbf8308
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980014236881749289033550279854064137386878948112265468899487755415901082299 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device_slow_rsp.24980014236881749289033550279854064137386878948112265468899487755415901082299
Directory /workspace/88.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.75135293560876137627662584559462920812990101572175327343976529556408570846210
Short name T1115
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.4 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:13:23 PM PST 23
Peak memory 553576 kb
Host smart-03b0e6ce-b136-4c93-aba4-b46608443fd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75135293560876137627662584559462920812990101572175327343976529556408570846210 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr.75135293560876137627662584559462920812990101572175327343976529556408570846210
Directory /workspace/88.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_random.80609004158057094522032254746914555684682058565696289730410740797284089259359
Short name T815
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.75 seconds
Started Nov 22 03:12:24 PM PST 23
Finished Nov 22 03:13:44 PM PST 23
Peak memory 553576 kb
Host smart-bff1cd5f-e523-467e-96c5-400e0d073aa5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80609004158057094522032254746914555684682058565696289730410740797284089259359 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 88.xbar_error_random.80609004158057094522032254746914555684682058565696289730410740797284089259359
Directory /workspace/88.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random.103227202771316535254142471658523407785901294287312105042453606672416150424528
Short name T906
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.25 seconds
Started Nov 22 03:12:11 PM PST 23
Finished Nov 22 03:13:28 PM PST 23
Peak memory 553776 kb
Host smart-9f763535-c80d-473f-b81b-57888e261b21
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103227202771316535254142471658523407785901294287312105042453606672416150424528 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 88.xbar_random.103227202771316535254142471658523407785901294287312105042453606672416150424528
Directory /workspace/88.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.88186093865555362119417549540795032946189468285407230479226637169194814917986
Short name T836
Test name
Test status
Simulation time 97702135727 ps
CPU time 1147.62 seconds
Started Nov 22 03:12:29 PM PST 23
Finished Nov 22 03:31:40 PM PST 23
Peak memory 553648 kb
Host smart-a8bc57b8-648a-48ff-847a-3837d8896fa4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88186093865555362119417549540795032946189468285407230479226637169194814917986 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.88186093865555362119417549540795032946189468285407230479226637169194814917986
Directory /workspace/88.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.44626826189842588759193078755128761413908016174271649367846677616243849416808
Short name T1352
Test name
Test status
Simulation time 60576345727 ps
CPU time 1123.58 seconds
Started Nov 22 03:12:26 PM PST 23
Finished Nov 22 03:31:12 PM PST 23
Peak memory 553760 kb
Host smart-7575e84e-4fab-4e69-900a-ebd31a38f760
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44626826189842588759193078755128761413908016174271649367846677616243849416808 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.44626826189842588759193078755128761413908016174271649367846677616243849416808
Directory /workspace/88.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.18915320199491129035809195421143817335117224751097484672976131938716896896977
Short name T1674
Test name
Test status
Simulation time 556965727 ps
CPU time 45.54 seconds
Started Nov 22 03:12:15 PM PST 23
Finished Nov 22 03:13:01 PM PST 23
Peak memory 553708 kb
Host smart-0b69d997-188b-4614-b8a0-7f52a1413d9c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18915320199491129035809195421143817335117224751097484672976131938716896896977 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_delays.18915320199491129035809195421143817335117224751097484672976131938716896896977
Directory /workspace/88.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_same_source.47010871918672588255536624541291574442227218484696779179102782795410841066812
Short name T754
Test name
Test status
Simulation time 2498784073 ps
CPU time 78.87 seconds
Started Nov 22 03:12:25 PM PST 23
Finished Nov 22 03:13:47 PM PST 23
Peak memory 553724 kb
Host smart-643995cc-05f4-4c08-940b-a5dd2573dcde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47010871918672588255536624541291574442227218484696779179102782795410841066812 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.47010871918672588255536624541291574442227218484696779179102782795410841066812
Directory /workspace/88.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke.81086631070047948835568565529124694853826221069603868227592537171835693302739
Short name T104
Test name
Test status
Simulation time 196985727 ps
CPU time 8.45 seconds
Started Nov 22 03:12:29 PM PST 23
Finished Nov 22 03:12:41 PM PST 23
Peak memory 552352 kb
Host smart-2a3b4d58-5a85-4f58-806e-3a1a253f6374
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81086631070047948835568565529124694853826221069603868227592537171835693302739 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 88.xbar_smoke.81086631070047948835568565529124694853826221069603868227592537171835693302739
Directory /workspace/88.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.23264204181661952635088898270932889575726597292273267792701903357030305553422
Short name T1345
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.1 seconds
Started Nov 22 03:12:12 PM PST 23
Finished Nov 22 03:13:40 PM PST 23
Peak memory 552352 kb
Host smart-9c21334c-9a40-4559-a020-321fc4901235
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23264204181661952635088898270932889575726597292273267792701903357030305553422 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.23264204181661952635088898270932889575726597292273267792701903357030305553422
Directory /workspace/88.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.107088410013571836955055786897645763131023428219852507316276729237132362787923
Short name T292
Test name
Test status
Simulation time 4856075727 ps
CPU time 83.93 seconds
Started Nov 22 03:12:09 PM PST 23
Finished Nov 22 03:13:33 PM PST 23
Peak memory 552356 kb
Host smart-cf4bb371-09d1-43ca-9922-cab3607282d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107088410013571836955055786897645763131023428219852507316276729237132362787923 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.107088410013571836955055786897645763131023428219852507316276729237132362787923
Directory /workspace/88.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.32967173667072328513630616814886359890124734672248858019897327277385937327942
Short name T439
Test name
Test status
Simulation time 45555727 ps
CPU time 5.97 seconds
Started Nov 22 03:12:29 PM PST 23
Finished Nov 22 03:12:38 PM PST 23
Peak memory 552348 kb
Host smart-4e1c31c4-481c-4dde-ad7b-7c9c8db57154
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32967173667072328513630616814886359890124734672248858019897327277385937327942 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.32967173667072328513630616814886359890124734672248858019897327277385937327942
Directory /workspace/88.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all.34180254348363576239132285257232730420794166687906900059073812437474678127572
Short name T60
Test name
Test status
Simulation time 13992004073 ps
CPU time 537.39 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:21:36 PM PST 23
Peak memory 555908 kb
Host smart-c7ed2a0e-c523-4df7-8113-d5f92aee6716
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34180254348363576239132285257232730420794166687906900059073812437474678127572 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.34180254348363576239132285257232730420794166687906900059073812437474678127572
Directory /workspace/88.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.51995762946630913672207987472818828348409770286432904364272703372826124833254
Short name T1523
Test name
Test status
Simulation time 13999524073 ps
CPU time 495.1 seconds
Started Nov 22 03:12:30 PM PST 23
Finished Nov 22 03:20:48 PM PST 23
Peak memory 555716 kb
Host smart-29bbfcf4-9aeb-4f2b-a707-4c278179a069
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51995762946630913672207987472818828348409770286432904364272703372826124833254 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.51995762946630913672207987472818828348409770286432904364272703372826124833254
Directory /workspace/88.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.89700128935543827426910446671336297177106496575773862504639996508442478107545
Short name T1878
Test name
Test status
Simulation time 4815189184 ps
CPU time 371.96 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:18:50 PM PST 23
Peak memory 557248 kb
Host smart-a5a94d5f-eb7d-46e1-afda-583afb3dbdc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89700128935543827426910446671336297177106496575773862504639996508442478107545 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_rand_reset.89700128935543827426910446671336297177106496575773862504639996
508442478107545
Directory /workspace/88.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.99517152211655906989241246531179317444317525036270043868697009559175391326757
Short name T77
Test name
Test status
Simulation time 4815189184 ps
CPU time 298.16 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:17:36 PM PST 23
Peak memory 559704 kb
Host smart-b1a80bdc-0adc-481a-8293-27b1e90f987d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99517152211655906989241246531179317444317525036270043868697009559175391326757 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_reset_error.995171522116559069892412465311793174443175250362700438686970
09559175391326757
Directory /workspace/88.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.89904378267435247456035271529208836567717140024854030960283281896843827545196
Short name T1546
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.56 seconds
Started Nov 22 03:12:39 PM PST 23
Finished Nov 22 03:13:27 PM PST 23
Peak memory 553720 kb
Host smart-95b23838-309f-46b6-b35e-b8bde905e804
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89904378267435247456035271529208836567717140024854030960283281896843827545196 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.89904378267435247456035271529208836567717140024854030960283281896843827545196
Directory /workspace/88.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device.9171172450025159939796564557863816186685409726265985113117195270849005066071
Short name T889
Test name
Test status
Simulation time 2590995727 ps
CPU time 107.72 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:14:25 PM PST 23
Peak memory 554816 kb
Host smart-70b316d3-9d96-40cd-bbfd-201d3c339c64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9171172450025159939796564557863816186685409726265985113117195270849005066071 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device.9171172450025159939796564557863816186685409726265985113117195270849005066071
Directory /workspace/89.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.86941022223893096506855874094803744023717235930467757386610988227176692426178
Short name T1316
Test name
Test status
Simulation time 115195295727 ps
CPU time 2060.78 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:46:59 PM PST 23
Peak memory 554724 kb
Host smart-4cb2c2a1-9e49-4b6f-bbbd-5965d1909e8e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86941022223893096506855874094803744023717235930467757386610988227176692426178 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device_slow_rsp.86941022223893096506855874094803744023717235930467757386610988227176692426178
Directory /workspace/89.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.47501779374184401444398722297228673745185288535923531545312152096756763170865
Short name T1369
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.24 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:13:24 PM PST 23
Peak memory 553476 kb
Host smart-1ad64cef-f9ef-431a-b142-2cec90b30075
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47501779374184401444398722297228673745185288535923531545312152096756763170865 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr.47501779374184401444398722297228673745185288535923531545312152096756763170865
Directory /workspace/89.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_random.65665783870261718475787927499717211804250536302887990284637808433196509858804
Short name T1064
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.68 seconds
Started Nov 22 03:12:36 PM PST 23
Finished Nov 22 03:13:53 PM PST 23
Peak memory 553488 kb
Host smart-af9f852e-1143-44d2-81e3-187a4cbe489e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65665783870261718475787927499717211804250536302887990284637808433196509858804 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 89.xbar_error_random.65665783870261718475787927499717211804250536302887990284637808433196509858804
Directory /workspace/89.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random.114546915408680304564662159744066312292151300996380163592673399060100455764047
Short name T799
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.51 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:13:59 PM PST 23
Peak memory 553792 kb
Host smart-d6f860af-8bd1-4519-8d4d-4d3bb97e4b7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114546915408680304564662159744066312292151300996380163592673399060100455764047 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 89.xbar_random.114546915408680304564662159744066312292151300996380163592673399060100455764047
Directory /workspace/89.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.87800511389290583522935987197777416647797343713085968229225952829772031521735
Short name T233
Test name
Test status
Simulation time 97702135727 ps
CPU time 1144.35 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:31:42 PM PST 23
Peak memory 553664 kb
Host smart-f54bd4fa-b855-4d60-87eb-8577abeda5db
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87800511389290583522935987197777416647797343713085968229225952829772031521735 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.87800511389290583522935987197777416647797343713085968229225952829772031521735
Directory /workspace/89.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.28578284460231458969936193802098570650996432189137155866106647708714347107514
Short name T291
Test name
Test status
Simulation time 60576345727 ps
CPU time 1121.82 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:31:21 PM PST 23
Peak memory 553608 kb
Host smart-f22fc22b-a21e-4dab-94aa-01d801b7c2ae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28578284460231458969936193802098570650996432189137155866106647708714347107514 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.28578284460231458969936193802098570650996432189137155866106647708714347107514
Directory /workspace/89.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.32074005275463552887538812319902266998181239217600857112750215511873901874727
Short name T453
Test name
Test status
Simulation time 556965727 ps
CPU time 46.59 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:13:26 PM PST 23
Peak memory 553708 kb
Host smart-625c8630-f6b8-402b-a874-336d4e654895
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32074005275463552887538812319902266998181239217600857112750215511873901874727 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delays.32074005275463552887538812319902266998181239217600857112750215511873901874727
Directory /workspace/89.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_same_source.30019056282246686755967507276813510094448774679027250127404642517621000250909
Short name T665
Test name
Test status
Simulation time 2498784073 ps
CPU time 77.55 seconds
Started Nov 22 03:12:36 PM PST 23
Finished Nov 22 03:13:54 PM PST 23
Peak memory 553604 kb
Host smart-7a17266d-1fd4-474b-bbd4-0a677db3745f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30019056282246686755967507276813510094448774679027250127404642517621000250909 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.30019056282246686755967507276813510094448774679027250127404642517621000250909
Directory /workspace/89.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke.13420083110127773037536719063187997475292640541897363329401056619275281674027
Short name T1217
Test name
Test status
Simulation time 196985727 ps
CPU time 8.2 seconds
Started Nov 22 03:12:28 PM PST 23
Finished Nov 22 03:12:38 PM PST 23
Peak memory 552328 kb
Host smart-4d81fd08-49cb-4b88-bf62-2f6ed345e1ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13420083110127773037536719063187997475292640541897363329401056619275281674027 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 89.xbar_smoke.13420083110127773037536719063187997475292640541897363329401056619275281674027
Directory /workspace/89.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.66846975617332162052688020183345300457628440124423094769732953661973052651682
Short name T491
Test name
Test status
Simulation time 7758585727 ps
CPU time 92.4 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:14:11 PM PST 23
Peak memory 552392 kb
Host smart-84c4a231-e805-4779-a708-6aa6949a2fb3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66846975617332162052688020183345300457628440124423094769732953661973052651682 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.66846975617332162052688020183345300457628440124423094769732953661973052651682
Directory /workspace/89.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.106031781495500110768272708395486536763630078167844073457389462585039766845446
Short name T1191
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.2 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:14:06 PM PST 23
Peak memory 552384 kb
Host smart-d95540e8-eab9-446d-8d52-540996d1b3fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106031781495500110768272708395486536763630078167844073457389462585039766845446 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.106031781495500110768272708395486536763630078167844073457389462585039766845446
Directory /workspace/89.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.32247991200113414425670260329639514937363582585774003168174569422539556934576
Short name T867
Test name
Test status
Simulation time 45555727 ps
CPU time 6.16 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:12:44 PM PST 23
Peak memory 552456 kb
Host smart-7b1fc5cd-ca12-4154-9984-3a6b33ee1aa3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247991200113414425670260329639514937363582585774003168174569422539556934576 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays.32247991200113414425670260329639514937363582585774003168174569422539556934576
Directory /workspace/89.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all.82805501003815420866646369654660810596939922231962782278139840670077314237703
Short name T541
Test name
Test status
Simulation time 13992004073 ps
CPU time 504.35 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:21:02 PM PST 23
Peak memory 555888 kb
Host smart-0a68f3be-8ecc-4773-874e-83ccc1373ba2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82805501003815420866646369654660810596939922231962782278139840670077314237703 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.82805501003815420866646369654660810596939922231962782278139840670077314237703
Directory /workspace/89.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.109800980844632457094277492835981054807752464381727490518206567291817677176188
Short name T1483
Test name
Test status
Simulation time 13999524073 ps
CPU time 497.89 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:20:56 PM PST 23
Peak memory 555652 kb
Host smart-20b0df4c-c80e-4337-8dcb-6258b6623cb9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109800980844632457094277492835981054807752464381727490518206567291817677176188 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.109800980844632457094277492835981054807752464381727490518206567291817677176188
Directory /workspace/89.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.84801835226058500910533612001399346355405657241660194733865212379210439906824
Short name T890
Test name
Test status
Simulation time 4815189184 ps
CPU time 372.91 seconds
Started Nov 22 03:12:37 PM PST 23
Finished Nov 22 03:18:51 PM PST 23
Peak memory 557264 kb
Host smart-e39dfe19-891a-479a-9d12-167d1117f1e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84801835226058500910533612001399346355405657241660194733865212379210439906824 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_rand_reset.84801835226058500910533612001399346355405657241660194733865212
379210439906824
Directory /workspace/89.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.52655552867141978001411975332144596766474681062488804808399069170671400799094
Short name T1810
Test name
Test status
Simulation time 4815189184 ps
CPU time 304.56 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:17:43 PM PST 23
Peak memory 559724 kb
Host smart-cc5f385f-9ff8-4a2c-a3da-24eddcc82fa6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52655552867141978001411975332144596766474681062488804808399069170671400799094 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_reset_error.526555528671419780014119753321445967664746810624888048083990
69170671400799094
Directory /workspace/89.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.26751301932379009083051032811372940949284154698304581602942977349565463224557
Short name T1561
Test name
Test status
Simulation time 1176995727 ps
CPU time 46.89 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:13:26 PM PST 23
Peak memory 553696 kb
Host smart-702a7582-c967-4d42-9d98-ea9ac22cee23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26751301932379009083051032811372940949284154698304581602942977349565463224557 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.26751301932379009083051032811372940949284154698304581602942977349565463224557
Directory /workspace/89.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.36999041465034033621352418683934809180701296319836126145045306620894505981035
Short name T44
Test name
Test status
Simulation time 7234930891 ps
CPU time 293.41 seconds
Started Nov 22 03:03:51 PM PST 23
Finished Nov 22 03:08:45 PM PST 23
Peak memory 622512 kb
Host smart-8d5a2069-e62b-4d3d-9432-a5ee38dbe3d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699904146503403362135241868393
4809180701296319836126145045306620894505981035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.3699904146503
4033621352418683934809180701296319836126145045306620894505981035
Directory /workspace/9.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_rw.40526698485919746849683268582220161178865065259388444180936883749745838991847
Short name T1602
Test name
Test status
Simulation time 5924944675 ps
CPU time 480.99 seconds
Started Nov 22 03:03:43 PM PST 23
Finished Nov 22 03:11:45 PM PST 23
Peak memory 580460 kb
Host smart-bae87c7a-bf75-414d-8a76-958fa4956806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40526698485919746849683268582220161178865065259388444180936883749745838991847 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.40526698485919746849683268582220161178865065259388444180936883749745838991847
Directory /workspace/9.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.43881042119459558865395997092245797847637352771387697568673766216585764064308
Short name T1539
Test name
Test status
Simulation time 30604932618 ps
CPU time 3308.85 seconds
Started Nov 22 03:04:00 PM PST 23
Finished Nov 22 03:59:10 PM PST 23
Peak memory 580532 kb
Host smart-cc2b447f-a1b6-42c4-82a0-a9eb31d88bc2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4388104211945955886539599709224579784
7637352771387697568673766216585764064308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.4388104211945955886539599
7092245797847637352771387697568673766216585764064308
Directory /workspace/9.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.chip_tl_errors.40292234789847567946253569988568556591707903354262700253892054319751342148317
Short name T56
Test name
Test status
Simulation time 3069924257 ps
CPU time 217.38 seconds
Started Nov 22 03:03:36 PM PST 23
Finished Nov 22 03:07:15 PM PST 23
Peak memory 580504 kb
Host smart-b03d4c7c-f59f-41e3-af71-a99ab5546467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40292234789847567946253569988568556591707903354262700253892054319751342148317 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.40292234789847567946253569988568556591707903354262700253892054319751342148317
Directory /workspace/9.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device.56411961819276403300123569706543315975888351550093409164061809424414085462553
Short name T433
Test name
Test status
Simulation time 2590995727 ps
CPU time 101.7 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:05:39 PM PST 23
Peak memory 554784 kb
Host smart-6c4595a0-00a6-4498-a04d-5dd27fc086bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56411961819276403300123569706543315975888351550093409164061809424414085462553 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.56411961819276403300123569706543315975888351550093409164061809424414085462553
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.64968521766287699594260225977192763295751253484616097168885303128202240958105
Short name T839
Test name
Test status
Simulation time 115195295727 ps
CPU time 2024.62 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:37:23 PM PST 23
Peak memory 554776 kb
Host smart-29b9cdbb-a83b-448e-bf55-ddc6bbec6487
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64968521766287699594260225977192763295751253484616097168885303128202240958105 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.64968521766287699594260225977192763295751253484616097168885303128202240958105
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2284597074987479386353068260149820796323717081813030374897651284855963388750
Short name T376
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.5 seconds
Started Nov 22 03:03:45 PM PST 23
Finished Nov 22 03:04:30 PM PST 23
Peak memory 553072 kb
Host smart-07ca1f62-07a8-4bcb-9c78-b6ac8e27db3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284597074987479386353068260149820796323717081813030374897651284855963388750 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2284597074987479386353068260149820796323717081813030374897651284855963388750
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_random.52668404867986981417010499217045723142007844390871614282029261505364435859162
Short name T1756
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.42 seconds
Started Nov 22 03:03:47 PM PST 23
Finished Nov 22 03:05:01 PM PST 23
Peak memory 553540 kb
Host smart-eb5e00f6-d1eb-4e15-90fa-c6ae1b68f2c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52668404867986981417010499217045723142007844390871614282029261505364435859162 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.xbar_error_random.52668404867986981417010499217045723142007844390871614282029261505364435859162
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random.7973827629267822758890299585568703576112192415869408036767559393833759110918
Short name T1364
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.28 seconds
Started Nov 22 03:03:42 PM PST 23
Finished Nov 22 03:04:59 PM PST 23
Peak memory 553684 kb
Host smart-63a51e10-714c-4b61-9b4e-d9458f3f8341
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7973827629267822758890299585568703576112192415869408036767559393833759110918 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.xbar_random.7973827629267822758890299585568703576112192415869408036767559393833759110918
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.17844915806698259713958777517996120769695984469809703305093026293622901515594
Short name T1391
Test name
Test status
Simulation time 97702135727 ps
CPU time 1099.23 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:22:16 PM PST 23
Peak memory 553640 kb
Host smart-f9c51d04-f84f-4cb2-aebd-877f3a2f7316
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17844915806698259713958777517996120769695984469809703305093026293622901515594 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.17844915806698259713958777517996120769695984469809703305093026293622901515594
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.61177793835170340234418196283150837544335924750271981716601464584216635361626
Short name T658
Test name
Test status
Simulation time 60576345727 ps
CPU time 1053.03 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:21:30 PM PST 23
Peak memory 553684 kb
Host smart-0aed4ef3-3400-4099-8412-0cf6a4a2ae57
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61177793835170340234418196283150837544335924750271981716601464584216635361626 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.61177793835170340234418196283150837544335924750271981716601464584216635361626
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.111256544604906514687219071197034587850142748722756841631583194747465040935210
Short name T1767
Test name
Test status
Simulation time 556965727 ps
CPU time 44.21 seconds
Started Nov 22 03:03:58 PM PST 23
Finished Nov 22 03:04:43 PM PST 23
Peak memory 553688 kb
Host smart-bfa70492-a73f-4780-b7ad-b9e794ecefc0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111256544604906514687219071197034587850142748722756841631583194747465040935210 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.111256544604906514687219071197034587850142748722756841631583194747465040935210
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_same_source.115714968513942458393094570783340710180604009848078625482959694551101366223247
Short name T1822
Test name
Test status
Simulation time 2498784073 ps
CPU time 69.89 seconds
Started Nov 22 03:03:48 PM PST 23
Finished Nov 22 03:04:59 PM PST 23
Peak memory 553704 kb
Host smart-46cbb584-5599-47e1-a365-a63139e5d7c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115714968513942458393094570783340710180604009848078625482959694551101366223247 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.115714968513942458393094570783340710180604009848078625482959694551101366223247
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke.68749250857910683649843533716396909294696449735817327688436403947106351768615
Short name T1204
Test name
Test status
Simulation time 196985727 ps
CPU time 8.34 seconds
Started Nov 22 03:03:35 PM PST 23
Finished Nov 22 03:03:44 PM PST 23
Peak memory 552364 kb
Host smart-f6888880-991d-43ac-8fbd-1de484aff077
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68749250857910683649843533716396909294696449735817327688436403947106351768615 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.xbar_smoke.68749250857910683649843533716396909294696449735817327688436403947106351768615
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.30947574195968191876743849712493827141057623355798032594055472414620239648803
Short name T792
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.72 seconds
Started Nov 22 03:03:56 PM PST 23
Finished Nov 22 03:05:27 PM PST 23
Peak memory 552500 kb
Host smart-f7dad9a9-0c4f-4f49-a9d8-c75720511e11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30947574195968191876743849712493827141057623355798032594055472414620239648803 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.30947574195968191876743849712493827141057623355798032594055472414620239648803
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.55407115418276009215392199636596347972003730200684916235948464158082994253347
Short name T1098
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.19 seconds
Started Nov 22 03:03:46 PM PST 23
Finished Nov 22 03:05:14 PM PST 23
Peak memory 552188 kb
Host smart-7bb22d33-e1d7-494e-a79b-bb6e96891894
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55407115418276009215392199636596347972003730200684916235948464158082994253347 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.55407115418276009215392199636596347972003730200684916235948464158082994253347
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.87926371558820008306620511227338744327882925848876709723015888062192871525220
Short name T1394
Test name
Test status
Simulation time 45555727 ps
CPU time 6.17 seconds
Started Nov 22 03:03:37 PM PST 23
Finished Nov 22 03:03:44 PM PST 23
Peak memory 552348 kb
Host smart-afe8ee5c-f2b6-4a40-afc6-d5740b6464c8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87926371558820008306620511227338744327882925848876709723015888062192871525220 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.87926371558820008306620511227338744327882925848876709723015888062192871525220
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all.26893645143552629437849502280191961524500188042605271694703592901744023875962
Short name T1433
Test name
Test status
Simulation time 13992004073 ps
CPU time 518.37 seconds
Started Nov 22 03:03:35 PM PST 23
Finished Nov 22 03:12:14 PM PST 23
Peak memory 555896 kb
Host smart-22835539-81ce-433f-b0ec-ff6ffa0adc63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26893645143552629437849502280191961524500188042605271694703592901744023875962 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.26893645143552629437849502280191961524500188042605271694703592901744023875962
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.29297743097524690513798535692130449431315440257465921362886727106122168809313
Short name T417
Test name
Test status
Simulation time 13999524073 ps
CPU time 477.17 seconds
Started Nov 22 03:03:51 PM PST 23
Finished Nov 22 03:11:49 PM PST 23
Peak memory 555724 kb
Host smart-04a1ad58-a798-400f-ad03-ff02be48a2f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297743097524690513798535692130449431315440257465921362886727106122168809313 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.29297743097524690513798535692130449431315440257465921362886727106122168809313
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.76603929381776052979143787451778814749835815907408314526391528768080546416629
Short name T1226
Test name
Test status
Simulation time 4815189184 ps
CPU time 360.58 seconds
Started Nov 22 03:03:58 PM PST 23
Finished Nov 22 03:10:00 PM PST 23
Peak memory 557188 kb
Host smart-96d46f87-d639-4fb6-9380-38960749c32f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76603929381776052979143787451778814749835815907408314526391528768080546416629 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.766039293817760529791437874517788147498358159074083145263915287
68080546416629
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.33695359061688467567968285770612616966793301708644301628905063803339237606193
Short name T178
Test name
Test status
Simulation time 4815189184 ps
CPU time 300.33 seconds
Started Nov 22 03:03:49 PM PST 23
Finished Nov 22 03:08:50 PM PST 23
Peak memory 559708 kb
Host smart-4ac6edd5-b059-49df-a44b-63de7abbdb2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33695359061688467567968285770612616966793301708644301628905063803339237606193 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3369535906168846756796828577061261696679330170864430162890506
3803339237606193
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.24724765543303741294915861645937219316138321503561137359885053909322183270858
Short name T550
Test name
Test status
Simulation time 1176995727 ps
CPU time 44.64 seconds
Started Nov 22 03:03:59 PM PST 23
Finished Nov 22 03:04:44 PM PST 23
Peak memory 553700 kb
Host smart-27ea7b97-3fcb-484f-91a3-bed273b391bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24724765543303741294915861645937219316138321503561137359885053909322183270858 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.24724765543303741294915861645937219316138321503561137359885053909322183270858
Directory /workspace/9.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device.72671469747016169077616232487174358044156012040694933788762946669507463919042
Short name T388
Test name
Test status
Simulation time 2590995727 ps
CPU time 111.5 seconds
Started Nov 22 03:12:46 PM PST 23
Finished Nov 22 03:14:38 PM PST 23
Peak memory 554760 kb
Host smart-62dd51fd-3810-47aa-a093-8bd760299ce2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72671469747016169077616232487174358044156012040694933788762946669507463919042 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.72671469747016169077616232487174358044156012040694933788762946669507463919042
Directory /workspace/90.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.107653532349351639618336807992746103897719851516705300713095290869871645803035
Short name T1121
Test name
Test status
Simulation time 115195295727 ps
CPU time 2001.87 seconds
Started Nov 22 03:12:47 PM PST 23
Finished Nov 22 03:46:10 PM PST 23
Peak memory 554752 kb
Host smart-fbb15f03-b998-4645-b904-cdab95caa426
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107653532349351639618336807992746103897719851516705300713095290869871645803035 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device_slow_rsp.107653532349351639618336807992746103897719851516705300713095290869871645803035
Directory /workspace/90.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.89918915856547575008134637617627727075167519659080484114934728816687647243453
Short name T1438
Test name
Test status
Simulation time 1171215727 ps
CPU time 41.53 seconds
Started Nov 22 03:12:46 PM PST 23
Finished Nov 22 03:13:29 PM PST 23
Peak memory 553464 kb
Host smart-c02d0fbb-87f0-46bf-abe5-b0111b55fedb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89918915856547575008134637617627727075167519659080484114934728816687647243453 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr.89918915856547575008134637617627727075167519659080484114934728816687647243453
Directory /workspace/90.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_random.68153148941610861649199319081328057229656697835675008130897231735163057365752
Short name T1500
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.98 seconds
Started Nov 22 03:12:47 PM PST 23
Finished Nov 22 03:14:08 PM PST 23
Peak memory 553528 kb
Host smart-c6497480-756c-496e-9f93-bd46f9080adc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68153148941610861649199319081328057229656697835675008130897231735163057365752 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 90.xbar_error_random.68153148941610861649199319081328057229656697835675008130897231735163057365752
Directory /workspace/90.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random.61791731105743663410879154638749565281264686274093987970949917674694192236897
Short name T778
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.68 seconds
Started Nov 22 03:12:39 PM PST 23
Finished Nov 22 03:13:56 PM PST 23
Peak memory 553732 kb
Host smart-d61f4453-e077-49ef-aaa1-eb8c102a54f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61791731105743663410879154638749565281264686274093987970949917674694192236897 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 90.xbar_random.61791731105743663410879154638749565281264686274093987970949917674694192236897
Directory /workspace/90.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.83144546456438999376237961129594115828660033695437972312676878102795357285657
Short name T1287
Test name
Test status
Simulation time 97702135727 ps
CPU time 1111.31 seconds
Started Nov 22 03:12:45 PM PST 23
Finished Nov 22 03:31:18 PM PST 23
Peak memory 553660 kb
Host smart-1b328e13-d978-4659-97e0-5238349d7379
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83144546456438999376237961129594115828660033695437972312676878102795357285657 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.83144546456438999376237961129594115828660033695437972312676878102795357285657
Directory /workspace/90.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.89355503707909397819090669921260708492858644896491012356056524938562611391881
Short name T1074
Test name
Test status
Simulation time 60576345727 ps
CPU time 1126.41 seconds
Started Nov 22 03:12:42 PM PST 23
Finished Nov 22 03:31:29 PM PST 23
Peak memory 553684 kb
Host smart-73002d2b-f033-4e56-8b55-b7a9985f6638
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89355503707909397819090669921260708492858644896491012356056524938562611391881 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.89355503707909397819090669921260708492858644896491012356056524938562611391881
Directory /workspace/90.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.106535323620199790667574740590131151620210908145777691986209452365011865747932
Short name T370
Test name
Test status
Simulation time 556965727 ps
CPU time 45.98 seconds
Started Nov 22 03:12:36 PM PST 23
Finished Nov 22 03:13:22 PM PST 23
Peak memory 553708 kb
Host smart-f61be257-a928-407d-8077-df2d96306cf8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106535323620199790667574740590131151620210908145777691986209452365011865747932 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_delays.106535323620199790667574740590131151620210908145777691986209452365011865747932
Directory /workspace/90.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_same_source.7229406255580158343918757943164011825138461185460168124800940162074873893206
Short name T1387
Test name
Test status
Simulation time 2498784073 ps
CPU time 71.53 seconds
Started Nov 22 03:12:47 PM PST 23
Finished Nov 22 03:13:59 PM PST 23
Peak memory 553748 kb
Host smart-c4166be9-4f05-4727-9d1b-1b5517209c4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7229406255580158343918757943164011825138461185460168124800940162074873893206 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.7229406255580158343918757943164011825138461185460168124800940162074873893206
Directory /workspace/90.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke.29094633363834137587722386459380035834011439490320043864912938266484243985362
Short name T390
Test name
Test status
Simulation time 196985727 ps
CPU time 8.91 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:12:48 PM PST 23
Peak memory 552384 kb
Host smart-89e28e60-1291-4490-b0a3-47efb6135cdd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29094633363834137587722386459380035834011439490320043864912938266484243985362 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 90.xbar_smoke.29094633363834137587722386459380035834011439490320043864912938266484243985362
Directory /workspace/90.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.93583430500219034730120320334695325917686494318181240533017965873846363991421
Short name T1538
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.33 seconds
Started Nov 22 03:12:36 PM PST 23
Finished Nov 22 03:14:08 PM PST 23
Peak memory 552384 kb
Host smart-ec14e117-7cf6-4368-aa68-18d723aa25f9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93583430500219034730120320334695325917686494318181240533017965873846363991421 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.93583430500219034730120320334695325917686494318181240533017965873846363991421
Directory /workspace/90.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.9002609622153841956325852123463746188124124143521835566206643471872761537319
Short name T1234
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.49 seconds
Started Nov 22 03:12:38 PM PST 23
Finished Nov 22 03:14:08 PM PST 23
Peak memory 552392 kb
Host smart-6e3e6336-f7ff-4509-9913-8ed858ae90a7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9002609622153841956325852123463746188124124143521835566206643471872761537319 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.9002609622153841956325852123463746188124124143521835566206643471872761537319
Directory /workspace/90.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.26682046667857734670997834304649122978434306321510356314447624909344968067379
Short name T676
Test name
Test status
Simulation time 45555727 ps
CPU time 5.66 seconds
Started Nov 22 03:12:39 PM PST 23
Finished Nov 22 03:12:46 PM PST 23
Peak memory 552336 kb
Host smart-bd39c338-55f2-4caa-87a5-67ff478c0268
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26682046667857734670997834304649122978434306321510356314447624909344968067379 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays.26682046667857734670997834304649122978434306321510356314447624909344968067379
Directory /workspace/90.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all.74492228206495268835899819481900436907673948967492378296575984429274008388371
Short name T361
Test name
Test status
Simulation time 13992004073 ps
CPU time 508.5 seconds
Started Nov 22 03:12:52 PM PST 23
Finished Nov 22 03:21:21 PM PST 23
Peak memory 555844 kb
Host smart-948e0d56-fba8-40aa-8624-71a2571c8bb2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74492228206495268835899819481900436907673948967492378296575984429274008388371 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.74492228206495268835899819481900436907673948967492378296575984429274008388371
Directory /workspace/90.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.50263441158869164964913420680872568708743113274412128108243251513448217309114
Short name T337
Test name
Test status
Simulation time 13999524073 ps
CPU time 475.33 seconds
Started Nov 22 03:12:51 PM PST 23
Finished Nov 22 03:20:47 PM PST 23
Peak memory 555824 kb
Host smart-02fa7549-f6b8-45b4-9bea-c56f732e35ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50263441158869164964913420680872568708743113274412128108243251513448217309114 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.50263441158869164964913420680872568708743113274412128108243251513448217309114
Directory /workspace/90.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.22790532412198330259088013741174711072654722816998222262519405610527018471379
Short name T636
Test name
Test status
Simulation time 4815189184 ps
CPU time 371.94 seconds
Started Nov 22 03:12:47 PM PST 23
Finished Nov 22 03:19:00 PM PST 23
Peak memory 557132 kb
Host smart-04795271-bf98-4ddf-ae30-d17e476ac9c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790532412198330259088013741174711072654722816998222262519405610527018471379 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_rand_reset.22790532412198330259088013741174711072654722816998222262519405
610527018471379
Directory /workspace/90.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.82032888752292110323951716312032845927993520795559077229141047119509842406971
Short name T731
Test name
Test status
Simulation time 4815189184 ps
CPU time 311.08 seconds
Started Nov 22 03:12:47 PM PST 23
Finished Nov 22 03:17:59 PM PST 23
Peak memory 559700 kb
Host smart-b64d0c1d-df98-4f7b-9884-1526fc4354f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82032888752292110323951716312032845927993520795559077229141047119509842406971 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_reset_error.820328887522921103239517163120328459279935207955590772291410
47119509842406971
Directory /workspace/90.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.103178010646566188496015555179476284217263152309115658354643744745844776634256
Short name T1844
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.94 seconds
Started Nov 22 03:12:46 PM PST 23
Finished Nov 22 03:13:34 PM PST 23
Peak memory 553708 kb
Host smart-9b2c708c-1ee8-4bf2-9e18-b3b5f98db4c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103178010646566188496015555179476284217263152309115658354643744745844776634256 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.103178010646566188496015555179476284217263152309115658354643744745844776634256
Directory /workspace/90.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device.84940585703969140766196266090230161808120806353762389235459924559219201837172
Short name T1146
Test name
Test status
Simulation time 2590995727 ps
CPU time 99.63 seconds
Started Nov 22 03:12:49 PM PST 23
Finished Nov 22 03:14:30 PM PST 23
Peak memory 554816 kb
Host smart-c187949c-c5f0-4ee3-8ec8-33e7426273f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84940585703969140766196266090230161808120806353762389235459924559219201837172 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.84940585703969140766196266090230161808120806353762389235459924559219201837172
Directory /workspace/91.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.108525395687523560859725744483840251423227171398330266907042871566337527272805
Short name T1793
Test name
Test status
Simulation time 115195295727 ps
CPU time 2013.42 seconds
Started Nov 22 03:12:51 PM PST 23
Finished Nov 22 03:46:25 PM PST 23
Peak memory 554868 kb
Host smart-80a38090-0101-488c-b75f-d6cf5ced1657
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108525395687523560859725744483840251423227171398330266907042871566337527272805 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device_slow_rsp.108525395687523560859725744483840251423227171398330266907042871566337527272805
Directory /workspace/91.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.104948373266013506184591012325383967978825138652667910458438560761329938143892
Short name T1579
Test name
Test status
Simulation time 1171215727 ps
CPU time 47.02 seconds
Started Nov 22 03:12:47 PM PST 23
Finished Nov 22 03:13:35 PM PST 23
Peak memory 553592 kb
Host smart-352cb49c-1f23-413b-ad5c-00a14e7ca848
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104948373266013506184591012325383967978825138652667910458438560761329938143892 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.104948373266013506184591012325383967978825138652667910458438560761329938143892
Directory /workspace/91.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_random.100148006092087799677264214543480466425521228721416804114583002872259495209760
Short name T529
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.63 seconds
Started Nov 22 03:12:49 PM PST 23
Finished Nov 22 03:14:10 PM PST 23
Peak memory 553448 kb
Host smart-79910ff1-0e02-40a0-af22-ffacdce8f30b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100148006092087799677264214543480466425521228721416804114583002872259495209760 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 91.xbar_error_random.100148006092087799677264214543480466425521228721416804114583002872259495209760
Directory /workspace/91.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random.32627978236068762876838934606211942980641661941779375821129056832352410611100
Short name T1544
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.11 seconds
Started Nov 22 03:12:50 PM PST 23
Finished Nov 22 03:14:10 PM PST 23
Peak memory 553772 kb
Host smart-bbc3f2c8-c069-4015-a6f3-3e2e5653a06d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32627978236068762876838934606211942980641661941779375821129056832352410611100 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 91.xbar_random.32627978236068762876838934606211942980641661941779375821129056832352410611100
Directory /workspace/91.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.26750239983746292888935473831584350199428374498876470798087164198320929527564
Short name T1106
Test name
Test status
Simulation time 97702135727 ps
CPU time 1157.43 seconds
Started Nov 22 03:12:48 PM PST 23
Finished Nov 22 03:32:06 PM PST 23
Peak memory 553664 kb
Host smart-e738b3bd-d5f5-4110-ad6b-1119859997a8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26750239983746292888935473831584350199428374498876470798087164198320929527564 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.26750239983746292888935473831584350199428374498876470798087164198320929527564
Directory /workspace/91.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.41933917530572508099208965851291146427140875488840066121056300651846067511007
Short name T588
Test name
Test status
Simulation time 60576345727 ps
CPU time 1103.39 seconds
Started Nov 22 03:12:49 PM PST 23
Finished Nov 22 03:31:14 PM PST 23
Peak memory 553712 kb
Host smart-49105226-277d-4175-ba22-f05a850fd90f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41933917530572508099208965851291146427140875488840066121056300651846067511007 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.41933917530572508099208965851291146427140875488840066121056300651846067511007
Directory /workspace/91.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.105928433952224932546422905407632052849453812101134062210916069621476639019867
Short name T1114
Test name
Test status
Simulation time 556965727 ps
CPU time 45.07 seconds
Started Nov 22 03:12:48 PM PST 23
Finished Nov 22 03:13:33 PM PST 23
Peak memory 553648 kb
Host smart-696dd57e-49d7-425f-9c7c-aa8e1421f1bc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105928433952224932546422905407632052849453812101134062210916069621476639019867 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delays.105928433952224932546422905407632052849453812101134062210916069621476639019867
Directory /workspace/91.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_same_source.85837059211963434592678147116943929296062537349652183772804161352411275602597
Short name T503
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.66 seconds
Started Nov 22 03:12:49 PM PST 23
Finished Nov 22 03:14:07 PM PST 23
Peak memory 553716 kb
Host smart-5bafea83-cc4c-4c6e-9ad0-801e052ff5fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85837059211963434592678147116943929296062537349652183772804161352411275602597 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.85837059211963434592678147116943929296062537349652183772804161352411275602597
Directory /workspace/91.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke.51419850173244140151608990757312827471764001990375240671030302391782969699141
Short name T949
Test name
Test status
Simulation time 196985727 ps
CPU time 8.19 seconds
Started Nov 22 03:12:50 PM PST 23
Finished Nov 22 03:12:59 PM PST 23
Peak memory 552384 kb
Host smart-4c616e5c-9f8b-4df6-b5d0-b581ef34d2d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51419850173244140151608990757312827471764001990375240671030302391782969699141 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 91.xbar_smoke.51419850173244140151608990757312827471764001990375240671030302391782969699141
Directory /workspace/91.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.20456582944515931738384693873699860203242652171565355068499450535010723267452
Short name T448
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.71 seconds
Started Nov 22 03:12:51 PM PST 23
Finished Nov 22 03:14:22 PM PST 23
Peak memory 552344 kb
Host smart-11eec086-aed5-4820-a094-db2b320da7df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20456582944515931738384693873699860203242652171565355068499450535010723267452 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.20456582944515931738384693873699860203242652171565355068499450535010723267452
Directory /workspace/91.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.90181289151263902371201590860463864599796336347087471730100223761851884473614
Short name T1764
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.25 seconds
Started Nov 22 03:12:57 PM PST 23
Finished Nov 22 03:14:25 PM PST 23
Peak memory 552356 kb
Host smart-89f95b54-b691-477e-8c10-3a636769b3b7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90181289151263902371201590860463864599796336347087471730100223761851884473614 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.90181289151263902371201590860463864599796336347087471730100223761851884473614
Directory /workspace/91.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.114157255256511150455470200438091444008937620316342019307337795465903246485430
Short name T1692
Test name
Test status
Simulation time 45555727 ps
CPU time 6.11 seconds
Started Nov 22 03:12:51 PM PST 23
Finished Nov 22 03:12:58 PM PST 23
Peak memory 552284 kb
Host smart-bdccaaa5-3faa-4b5d-9a48-75f618c30e72
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114157255256511150455470200438091444008937620316342019307337795465903246485430 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays.114157255256511150455470200438091444008937620316342019307337795465903246485430
Directory /workspace/91.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all.108860975364711807370352735202156383507442474830189369456011360758804473131154
Short name T1027
Test name
Test status
Simulation time 13992004073 ps
CPU time 479.21 seconds
Started Nov 22 03:12:49 PM PST 23
Finished Nov 22 03:20:49 PM PST 23
Peak memory 555892 kb
Host smart-4ccb4ee9-d7f3-4485-8f2b-6ea087143fd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108860975364711807370352735202156383507442474830189369456011360758804473131154 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.108860975364711807370352735202156383507442474830189369456011360758804473131154
Directory /workspace/91.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.101132129886937738176118750159718679467422152048444413176714761794540160371382
Short name T1161
Test name
Test status
Simulation time 13999524073 ps
CPU time 475.47 seconds
Started Nov 22 03:12:47 PM PST 23
Finished Nov 22 03:20:43 PM PST 23
Peak memory 555724 kb
Host smart-9fdf883c-280a-4caf-b027-996f70ceac03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101132129886937738176118750159718679467422152048444413176714761794540160371382 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.101132129886937738176118750159718679467422152048444413176714761794540160371382
Directory /workspace/91.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.80916082500663401972534840231148057794650705314993596673160640410202897832361
Short name T1543
Test name
Test status
Simulation time 4815189184 ps
CPU time 368.35 seconds
Started Nov 22 03:12:51 PM PST 23
Finished Nov 22 03:19:00 PM PST 23
Peak memory 557252 kb
Host smart-49c82ac4-8062-4202-8bf6-3192eeb3f387
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80916082500663401972534840231148057794650705314993596673160640410202897832361 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_rand_reset.80916082500663401972534840231148057794650705314993596673160640
410202897832361
Directory /workspace/91.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.87787093545122383033880452578740427695939812953336334368652539615860001531017
Short name T957
Test name
Test status
Simulation time 4815189184 ps
CPU time 314.65 seconds
Started Nov 22 03:12:49 PM PST 23
Finished Nov 22 03:18:04 PM PST 23
Peak memory 559732 kb
Host smart-a31c483e-3f29-4f23-b8ed-376bd7bc0da2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87787093545122383033880452578740427695939812953336334368652539615860001531017 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_reset_error.877870935451223830338804525787404276959398129533363343686525
39615860001531017
Directory /workspace/91.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.114462876712427547769183716377492979653067367880409251688681485901755325908487
Short name T372
Test name
Test status
Simulation time 1176995727 ps
CPU time 47.51 seconds
Started Nov 22 03:12:50 PM PST 23
Finished Nov 22 03:13:38 PM PST 23
Peak memory 553720 kb
Host smart-5779ad93-c7da-4250-9c17-670580726bc3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114462876712427547769183716377492979653067367880409251688681485901755325908487 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.114462876712427547769183716377492979653067367880409251688681485901755325908487
Directory /workspace/91.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device.3685904228202398821847783344025168186715388910831507535305091578325151230748
Short name T154
Test name
Test status
Simulation time 2590995727 ps
CPU time 103.64 seconds
Started Nov 22 03:12:59 PM PST 23
Finished Nov 22 03:14:43 PM PST 23
Peak memory 554788 kb
Host smart-f3b9b39f-3b61-4dd5-ac56-0c060049c793
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685904228202398821847783344025168186715388910831507535305091578325151230748 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device.3685904228202398821847783344025168186715388910831507535305091578325151230748
Directory /workspace/92.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.30089146001950718835931935201230150528024912180657507390207166232482427086433
Short name T192
Test name
Test status
Simulation time 115195295727 ps
CPU time 2028.51 seconds
Started Nov 22 03:12:55 PM PST 23
Finished Nov 22 03:46:45 PM PST 23
Peak memory 554740 kb
Host smart-b9ea390b-3267-4de4-a207-4cce75734fdb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30089146001950718835931935201230150528024912180657507390207166232482427086433 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device_slow_rsp.30089146001950718835931935201230150528024912180657507390207166232482427086433
Directory /workspace/92.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.71615903349644553704524322281829320917567793942115118173504471574030865461665
Short name T770
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.71 seconds
Started Nov 22 03:12:56 PM PST 23
Finished Nov 22 03:13:43 PM PST 23
Peak memory 553500 kb
Host smart-5fea055c-77b5-47e7-9a67-fbb7b9961f63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71615903349644553704524322281829320917567793942115118173504471574030865461665 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr.71615903349644553704524322281829320917567793942115118173504471574030865461665
Directory /workspace/92.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_random.69744017197731115245309631623841954985463407610464363583788052412959802539254
Short name T1799
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.06 seconds
Started Nov 22 03:12:56 PM PST 23
Finished Nov 22 03:14:11 PM PST 23
Peak memory 553412 kb
Host smart-752c06fb-0dc0-470f-a9ed-6d1cdb721dd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69744017197731115245309631623841954985463407610464363583788052412959802539254 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 92.xbar_error_random.69744017197731115245309631623841954985463407610464363583788052412959802539254
Directory /workspace/92.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random.11707311677655573498042348613379312881442902911634335306450734511044142346657
Short name T509
Test name
Test status
Simulation time 2231375727 ps
CPU time 80.04 seconds
Started Nov 22 03:12:58 PM PST 23
Finished Nov 22 03:14:18 PM PST 23
Peak memory 553664 kb
Host smart-109b00e3-7003-432c-99ae-42ae1665a383
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11707311677655573498042348613379312881442902911634335306450734511044142346657 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 92.xbar_random.11707311677655573498042348613379312881442902911634335306450734511044142346657
Directory /workspace/92.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.80778767285273409263083024866751432696957744094983540333850080979820007697629
Short name T339
Test name
Test status
Simulation time 97702135727 ps
CPU time 1150.32 seconds
Started Nov 22 03:12:56 PM PST 23
Finished Nov 22 03:32:07 PM PST 23
Peak memory 553584 kb
Host smart-0ac8d2d6-b72f-41bd-9c0e-55fbfcbe98a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80778767285273409263083024866751432696957744094983540333850080979820007697629 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.80778767285273409263083024866751432696957744094983540333850080979820007697629
Directory /workspace/92.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.109984595743861729786042841745791501140866773364356993624612945136044285882777
Short name T682
Test name
Test status
Simulation time 60576345727 ps
CPU time 1078.67 seconds
Started Nov 22 03:12:57 PM PST 23
Finished Nov 22 03:30:56 PM PST 23
Peak memory 553792 kb
Host smart-104c7815-124b-4641-8e82-c9d3651a5ed3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109984595743861729786042841745791501140866773364356993624612945136044285882777 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.109984595743861729786042841745791501140866773364356993624612945136044285882777
Directory /workspace/92.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.18182596133906320265641595218718864614960099491375776102893720405140347859183
Short name T769
Test name
Test status
Simulation time 556965727 ps
CPU time 43.51 seconds
Started Nov 22 03:12:55 PM PST 23
Finished Nov 22 03:13:40 PM PST 23
Peak memory 553680 kb
Host smart-6404cac5-cec1-4967-9f17-55333b662261
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18182596133906320265641595218718864614960099491375776102893720405140347859183 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_delays.18182596133906320265641595218718864614960099491375776102893720405140347859183
Directory /workspace/92.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_same_source.55944709334640985071054618333152821825322221143047045673199792495767397261742
Short name T531
Test name
Test status
Simulation time 2498784073 ps
CPU time 78.08 seconds
Started Nov 22 03:12:57 PM PST 23
Finished Nov 22 03:14:16 PM PST 23
Peak memory 553728 kb
Host smart-7bfd2a69-8d70-4cdd-bf23-3fbc0604ec55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55944709334640985071054618333152821825322221143047045673199792495767397261742 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.55944709334640985071054618333152821825322221143047045673199792495767397261742
Directory /workspace/92.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke.46918774860492890315725925740145942120191591424920719168641263711826109755632
Short name T1714
Test name
Test status
Simulation time 196985727 ps
CPU time 8.57 seconds
Started Nov 22 03:12:50 PM PST 23
Finished Nov 22 03:12:59 PM PST 23
Peak memory 552380 kb
Host smart-3dd2e8e6-6fd7-4336-a654-d38d58856e3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46918774860492890315725925740145942120191591424920719168641263711826109755632 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 92.xbar_smoke.46918774860492890315725925740145942120191591424920719168641263711826109755632
Directory /workspace/92.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.48260488053435307583683006277766461728349901590184206899301758257477044864090
Short name T385
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.33 seconds
Started Nov 22 03:12:48 PM PST 23
Finished Nov 22 03:14:18 PM PST 23
Peak memory 552352 kb
Host smart-cc8b487c-27d1-409e-841e-1d453b083668
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48260488053435307583683006277766461728349901590184206899301758257477044864090 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.48260488053435307583683006277766461728349901590184206899301758257477044864090
Directory /workspace/92.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.100465127442324778322504863282851364234764056289634244710193684291179655558687
Short name T1741
Test name
Test status
Simulation time 4856075727 ps
CPU time 86.91 seconds
Started Nov 22 03:12:56 PM PST 23
Finished Nov 22 03:14:23 PM PST 23
Peak memory 552400 kb
Host smart-773f8c14-fcc9-4cc1-84a8-14cf4290f8aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100465127442324778322504863282851364234764056289634244710193684291179655558687 -assert nopostpr
oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.100465127442324778322504863282851364234764056289634244710193684291179655558687
Directory /workspace/92.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.85221789977835680706992097909914646053991463801225019056235569732342885219605
Short name T1358
Test name
Test status
Simulation time 45555727 ps
CPU time 5.77 seconds
Started Nov 22 03:12:51 PM PST 23
Finished Nov 22 03:12:57 PM PST 23
Peak memory 552360 kb
Host smart-eafeb649-e7ed-4204-a782-0aa682214553
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85221789977835680706992097909914646053991463801225019056235569732342885219605 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays.85221789977835680706992097909914646053991463801225019056235569732342885219605
Directory /workspace/92.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all.71899695672956942181634926113492385268881108216878611256223556331462995695495
Short name T652
Test name
Test status
Simulation time 13992004073 ps
CPU time 524.97 seconds
Started Nov 22 03:12:57 PM PST 23
Finished Nov 22 03:21:43 PM PST 23
Peak memory 555884 kb
Host smart-6caeaaf4-e62b-43e3-8724-f24c5b07bd6a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71899695672956942181634926113492385268881108216878611256223556331462995695495 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.71899695672956942181634926113492385268881108216878611256223556331462995695495
Directory /workspace/92.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.71139721261231751803841666175102552392334368170513018564704037197002403218310
Short name T483
Test name
Test status
Simulation time 13999524073 ps
CPU time 475.86 seconds
Started Nov 22 03:12:57 PM PST 23
Finished Nov 22 03:20:54 PM PST 23
Peak memory 555728 kb
Host smart-0faeeba7-4e0f-485d-ad01-881e5a0afcbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71139721261231751803841666175102552392334368170513018564704037197002403218310 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.71139721261231751803841666175102552392334368170513018564704037197002403218310
Directory /workspace/92.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.53146257630304598918958471342286791528077183143360598398203150541924727628100
Short name T99
Test name
Test status
Simulation time 4815189184 ps
CPU time 362.53 seconds
Started Nov 22 03:12:58 PM PST 23
Finished Nov 22 03:19:01 PM PST 23
Peak memory 557252 kb
Host smart-6681423d-b9c1-42fb-81c9-926a9849bf0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53146257630304598918958471342286791528077183143360598398203150541924727628100 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_rand_reset.53146257630304598918958471342286791528077183143360598398203150
541924727628100
Directory /workspace/92.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.18492671388818428274806345465872951002236466729905482688030932161776523959916
Short name T459
Test name
Test status
Simulation time 4815189184 ps
CPU time 300.84 seconds
Started Nov 22 03:12:56 PM PST 23
Finished Nov 22 03:17:58 PM PST 23
Peak memory 559708 kb
Host smart-bd319930-3a14-4bdb-87c1-1778955108ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18492671388818428274806345465872951002236466729905482688030932161776523959916 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_reset_error.184926713888184282748063454658729510022364667299054826880309
32161776523959916
Directory /workspace/92.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.60502497881605162102637244651609993913894527744914091301288718763602786428961
Short name T874
Test name
Test status
Simulation time 1176995727 ps
CPU time 45.99 seconds
Started Nov 22 03:12:54 PM PST 23
Finished Nov 22 03:13:40 PM PST 23
Peak memory 553744 kb
Host smart-3f07fae0-8cd1-4c94-96be-b847185bda9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60502497881605162102637244651609993913894527744914091301288718763602786428961 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.60502497881605162102637244651609993913894527744914091301288718763602786428961
Directory /workspace/92.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device.90099088656015066390856536635099972045891124764139288277563083980232321398312
Short name T347
Test name
Test status
Simulation time 2590995727 ps
CPU time 102.62 seconds
Started Nov 22 03:13:00 PM PST 23
Finished Nov 22 03:14:44 PM PST 23
Peak memory 554788 kb
Host smart-fac09ad8-7c7f-4b4b-bc8e-720067fc9322
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90099088656015066390856536635099972045891124764139288277563083980232321398312 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.90099088656015066390856536635099972045891124764139288277563083980232321398312
Directory /workspace/93.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.52924073122649021798053281601616241172496438062916226734896546717164948237100
Short name T1504
Test name
Test status
Simulation time 115195295727 ps
CPU time 2052.48 seconds
Started Nov 22 03:12:59 PM PST 23
Finished Nov 22 03:47:12 PM PST 23
Peak memory 554760 kb
Host smart-f7c73c4e-79c4-4a24-8cf1-bd7042f37b26
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52924073122649021798053281601616241172496438062916226734896546717164948237100 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device_slow_rsp.52924073122649021798053281601616241172496438062916226734896546717164948237100
Directory /workspace/93.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.69118455072938575800109036893704332143388264538761477050604739860484010727525
Short name T1309
Test name
Test status
Simulation time 1171215727 ps
CPU time 44.52 seconds
Started Nov 22 03:13:00 PM PST 23
Finished Nov 22 03:13:46 PM PST 23
Peak memory 553464 kb
Host smart-363fae3b-d201-474c-8ec8-43e52c7fc4f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69118455072938575800109036893704332143388264538761477050604739860484010727525 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr.69118455072938575800109036893704332143388264538761477050604739860484010727525
Directory /workspace/93.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_random.25250493470799912590928358115356664651629141786296906674312895461724610222638
Short name T774
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.44 seconds
Started Nov 22 03:13:02 PM PST 23
Finished Nov 22 03:14:15 PM PST 23
Peak memory 553536 kb
Host smart-8650b63b-d7fd-4dce-9b69-0073abd1061e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25250493470799912590928358115356664651629141786296906674312895461724610222638 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 93.xbar_error_random.25250493470799912590928358115356664651629141786296906674312895461724610222638
Directory /workspace/93.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random.9774107036594616399245727885664230873018651272488659906261375415990596690707
Short name T1254
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.82 seconds
Started Nov 22 03:13:04 PM PST 23
Finished Nov 22 03:14:22 PM PST 23
Peak memory 553756 kb
Host smart-f3c6e621-2708-4e60-bc11-2eccd84bbb30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9774107036594616399245727885664230873018651272488659906261375415990596690707 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 93.xbar_random.9774107036594616399245727885664230873018651272488659906261375415990596690707
Directory /workspace/93.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.51610609749761126434870490736614949368312587790876408759408654709170126275991
Short name T998
Test name
Test status
Simulation time 97702135727 ps
CPU time 1143.33 seconds
Started Nov 22 03:13:02 PM PST 23
Finished Nov 22 03:32:06 PM PST 23
Peak memory 553668 kb
Host smart-7d9b7df8-7595-403d-83af-6cc91b98b711
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51610609749761126434870490736614949368312587790876408759408654709170126275991 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.51610609749761126434870490736614949368312587790876408759408654709170126275991
Directory /workspace/93.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.69896550679588984442873933341542893381419249862577085440349144417284128336828
Short name T745
Test name
Test status
Simulation time 60576345727 ps
CPU time 1131.37 seconds
Started Nov 22 03:12:58 PM PST 23
Finished Nov 22 03:31:50 PM PST 23
Peak memory 553720 kb
Host smart-d32788df-848b-470c-b364-eba258681d48
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69896550679588984442873933341542893381419249862577085440349144417284128336828 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.69896550679588984442873933341542893381419249862577085440349144417284128336828
Directory /workspace/93.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.5683604721557249928532399671569634413283414072502054390501761863785157450187
Short name T1421
Test name
Test status
Simulation time 556965727 ps
CPU time 45.73 seconds
Started Nov 22 03:13:00 PM PST 23
Finished Nov 22 03:13:46 PM PST 23
Peak memory 553828 kb
Host smart-09700ae4-51b9-4f20-a948-48947e83aee7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5683604721557249928532399671569634413283414072502054390501761863785157450187 -assert n
opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_delays.5683604721557249928532399671569634413283414072502054390501761863785157450187
Directory /workspace/93.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_same_source.60554319300665714183811354177273621412535067782063840079718873815238942465813
Short name T783
Test name
Test status
Simulation time 2498784073 ps
CPU time 80.18 seconds
Started Nov 22 03:13:05 PM PST 23
Finished Nov 22 03:14:26 PM PST 23
Peak memory 553736 kb
Host smart-be152f75-1748-4816-ac55-18642265052d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60554319300665714183811354177273621412535067782063840079718873815238942465813 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.60554319300665714183811354177273621412535067782063840079718873815238942465813
Directory /workspace/93.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke.89086514144763954103673116744153799216436283501309234795507686667786347304098
Short name T1864
Test name
Test status
Simulation time 196985727 ps
CPU time 8.94 seconds
Started Nov 22 03:12:57 PM PST 23
Finished Nov 22 03:13:07 PM PST 23
Peak memory 552308 kb
Host smart-37ea6b47-7a83-43a8-ab76-06b5889fc09a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89086514144763954103673116744153799216436283501309234795507686667786347304098 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 93.xbar_smoke.89086514144763954103673116744153799216436283501309234795507686667786347304098
Directory /workspace/93.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.56678283467716164653026390415645193922991531426804293366944898541577018656084
Short name T185
Test name
Test status
Simulation time 7758585727 ps
CPU time 90.82 seconds
Started Nov 22 03:12:59 PM PST 23
Finished Nov 22 03:14:31 PM PST 23
Peak memory 552364 kb
Host smart-daba980c-b540-4369-8045-b8e0d576946d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56678283467716164653026390415645193922991531426804293366944898541577018656084 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.56678283467716164653026390415645193922991531426804293366944898541577018656084
Directory /workspace/93.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.32280804275662863148257256687425142055157036721767078608166646175172750679379
Short name T818
Test name
Test status
Simulation time 4856075727 ps
CPU time 87.87 seconds
Started Nov 22 03:13:03 PM PST 23
Finished Nov 22 03:14:31 PM PST 23
Peak memory 552392 kb
Host smart-3afa072e-0fca-4b16-a15e-11dc021ea16b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32280804275662863148257256687425142055157036721767078608166646175172750679379 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.32280804275662863148257256687425142055157036721767078608166646175172750679379
Directory /workspace/93.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.99144522864384996258866200643609853817478513874274628425738582476754697283471
Short name T1104
Test name
Test status
Simulation time 45555727 ps
CPU time 6.23 seconds
Started Nov 22 03:12:58 PM PST 23
Finished Nov 22 03:13:05 PM PST 23
Peak memory 552312 kb
Host smart-2ddc316b-0dd7-4ea4-9bbc-b89819aac5b6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99144522864384996258866200643609853817478513874274628425738582476754697283471 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays.99144522864384996258866200643609853817478513874274628425738582476754697283471
Directory /workspace/93.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all.42907931261684948681249647258473986175768716488152233100380924973383277967666
Short name T1922
Test name
Test status
Simulation time 13992004073 ps
CPU time 488.18 seconds
Started Nov 22 03:13:01 PM PST 23
Finished Nov 22 03:21:10 PM PST 23
Peak memory 555912 kb
Host smart-e6803ea4-5267-4883-9ff4-933ab239a480
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42907931261684948681249647258473986175768716488152233100380924973383277967666 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.42907931261684948681249647258473986175768716488152233100380924973383277967666
Directory /workspace/93.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.33053091831174796008641181111059777173024496721956607866147854882973545875729
Short name T442
Test name
Test status
Simulation time 13999524073 ps
CPU time 471.82 seconds
Started Nov 22 03:13:02 PM PST 23
Finished Nov 22 03:20:55 PM PST 23
Peak memory 555728 kb
Host smart-225f4258-f8ed-4092-861a-1e051054293c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33053091831174796008641181111059777173024496721956607866147854882973545875729 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.33053091831174796008641181111059777173024496721956607866147854882973545875729
Directory /workspace/93.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.19189844550837349751870124096280512609120454359537026868128250769147173420709
Short name T780
Test name
Test status
Simulation time 4815189184 ps
CPU time 375.48 seconds
Started Nov 22 03:12:59 PM PST 23
Finished Nov 22 03:19:15 PM PST 23
Peak memory 557272 kb
Host smart-7ffbdaf7-9874-4bec-a423-72c5ffc4132b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189844550837349751870124096280512609120454359537026868128250769147173420709 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_rand_reset.19189844550837349751870124096280512609120454359537026868128250
769147173420709
Directory /workspace/93.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4382198911113640363974768044806945266006693891227944374076282162359773947022
Short name T1222
Test name
Test status
Simulation time 4815189184 ps
CPU time 297.06 seconds
Started Nov 22 03:13:04 PM PST 23
Finished Nov 22 03:18:01 PM PST 23
Peak memory 559804 kb
Host smart-f6729620-6f53-4bb7-9034-c4a711941962
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4382198911113640363974768044806945266006693891227944374076282162359773947022 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_reset_error.4382198911113640363974768044806945266006693891227944374076282
162359773947022
Directory /workspace/93.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.94325225537152172008302197293358230495075524738086611393215817981825382916336
Short name T787
Test name
Test status
Simulation time 1176995727 ps
CPU time 49.65 seconds
Started Nov 22 03:13:04 PM PST 23
Finished Nov 22 03:13:54 PM PST 23
Peak memory 553804 kb
Host smart-84128126-8d0b-4dd0-bad6-554ae8e07e51
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94325225537152172008302197293358230495075524738086611393215817981825382916336 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.94325225537152172008302197293358230495075524738086611393215817981825382916336
Directory /workspace/93.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device.53130487115451915717597771059819998482418202827469470010488929306545441430551
Short name T1055
Test name
Test status
Simulation time 2590995727 ps
CPU time 96.44 seconds
Started Nov 22 03:13:21 PM PST 23
Finished Nov 22 03:14:58 PM PST 23
Peak memory 554756 kb
Host smart-5d3e7a6d-3049-4998-8243-ff2b2e7a7124
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53130487115451915717597771059819998482418202827469470010488929306545441430551 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.53130487115451915717597771059819998482418202827469470010488929306545441430551
Directory /workspace/94.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.84678855606947685403391815902099577224048865317110219023996694289752287722024
Short name T672
Test name
Test status
Simulation time 115195295727 ps
CPU time 2067.03 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:47:46 PM PST 23
Peak memory 554884 kb
Host smart-4729c3d1-0048-4584-92c8-6b04fe023a7f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84678855606947685403391815902099577224048865317110219023996694289752287722024 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device_slow_rsp.84678855606947685403391815902099577224048865317110219023996694289752287722024
Directory /workspace/94.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.18631204080207916270185957326281947163738348038113418349574490382126968915788
Short name T1343
Test name
Test status
Simulation time 1171215727 ps
CPU time 45 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:14:05 PM PST 23
Peak memory 553472 kb
Host smart-ce139671-31ce-4d70-b377-16950bd97648
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18631204080207916270185957326281947163738348038113418349574490382126968915788 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr.18631204080207916270185957326281947163738348038113418349574490382126968915788
Directory /workspace/94.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_random.90472178009555411524825257119025530749701663523284480759883574173788103154221
Short name T1167
Test name
Test status
Simulation time 2231375727 ps
CPU time 69.18 seconds
Started Nov 22 03:13:16 PM PST 23
Finished Nov 22 03:14:26 PM PST 23
Peak memory 553540 kb
Host smart-f1385336-9246-4276-ace3-2008fc336695
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90472178009555411524825257119025530749701663523284480759883574173788103154221 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 94.xbar_error_random.90472178009555411524825257119025530749701663523284480759883574173788103154221
Directory /workspace/94.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random.46156949100668043124448576467557247179908818261767376621628217677551615504792
Short name T566
Test name
Test status
Simulation time 2231375727 ps
CPU time 78.29 seconds
Started Nov 22 03:13:27 PM PST 23
Finished Nov 22 03:14:46 PM PST 23
Peak memory 553664 kb
Host smart-07fc3043-48ae-45e4-9cae-64fcb81ede53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46156949100668043124448576467557247179908818261767376621628217677551615504792 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 94.xbar_random.46156949100668043124448576467557247179908818261767376621628217677551615504792
Directory /workspace/94.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.102746440432937415107546636091871638805711983202726170744830775133817383816257
Short name T110
Test name
Test status
Simulation time 97702135727 ps
CPU time 1176.23 seconds
Started Nov 22 03:13:21 PM PST 23
Finished Nov 22 03:32:58 PM PST 23
Peak memory 553652 kb
Host smart-ed2a84b6-8cb3-4441-92e3-b90121687809
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102746440432937415107546636091871638805711983202726170744830775133817383816257 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.102746440432937415107546636091871638805711983202726170744830775133817383816257
Directory /workspace/94.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.27490690301130408231788780730113715784529016060539344805834071182817094645624
Short name T1238
Test name
Test status
Simulation time 60576345727 ps
CPU time 1069.88 seconds
Started Nov 22 03:13:15 PM PST 23
Finished Nov 22 03:31:06 PM PST 23
Peak memory 553672 kb
Host smart-5982fa10-0ab7-4ea1-bffc-e82b56a76d2b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490690301130408231788780730113715784529016060539344805834071182817094645624 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.27490690301130408231788780730113715784529016060539344805834071182817094645624
Directory /workspace/94.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.89792620531905090090413639723762977217262898202295684953681185291068108086862
Short name T1331
Test name
Test status
Simulation time 556965727 ps
CPU time 47.9 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:14:07 PM PST 23
Peak memory 553728 kb
Host smart-7967b808-ff6c-4bdb-abfb-6c6c118d8948
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89792620531905090090413639723762977217262898202295684953681185291068108086862 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_delays.89792620531905090090413639723762977217262898202295684953681185291068108086862
Directory /workspace/94.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_same_source.9142836503162590712469181857368175424768069888825791166411205440469348309723
Short name T735
Test name
Test status
Simulation time 2498784073 ps
CPU time 70.35 seconds
Started Nov 22 03:13:15 PM PST 23
Finished Nov 22 03:14:26 PM PST 23
Peak memory 553716 kb
Host smart-f6fba591-3736-4f0a-92ae-b51d9f99ba60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9142836503162590712469181857368175424768069888825791166411205440469348309723 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.9142836503162590712469181857368175424768069888825791166411205440469348309723
Directory /workspace/94.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke.60602289050961852650645318427256010073072172475713056053202007146716137554047
Short name T645
Test name
Test status
Simulation time 196985727 ps
CPU time 8.42 seconds
Started Nov 22 03:13:04 PM PST 23
Finished Nov 22 03:13:13 PM PST 23
Peak memory 552456 kb
Host smart-342eadcb-ff05-446a-a359-7fc9d5200ae5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60602289050961852650645318427256010073072172475713056053202007146716137554047 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 94.xbar_smoke.60602289050961852650645318427256010073072172475713056053202007146716137554047
Directory /workspace/94.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.73890841456411590265811919761309502515053900691207951817764892648639375859431
Short name T209
Test name
Test status
Simulation time 7758585727 ps
CPU time 86.87 seconds
Started Nov 22 03:13:16 PM PST 23
Finished Nov 22 03:14:44 PM PST 23
Peak memory 552344 kb
Host smart-ff434ad8-d6dd-44dc-993e-649dc7424cc9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73890841456411590265811919761309502515053900691207951817764892648639375859431 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.73890841456411590265811919761309502515053900691207951817764892648639375859431
Directory /workspace/94.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.53178071316451870012126700640140538421066970790573210800441570535661519059017
Short name T210
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.11 seconds
Started Nov 22 03:13:20 PM PST 23
Finished Nov 22 03:14:51 PM PST 23
Peak memory 552480 kb
Host smart-05747db0-9ba1-431b-8960-8086aa108553
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53178071316451870012126700640140538421066970790573210800441570535661519059017 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.53178071316451870012126700640140538421066970790573210800441570535661519059017
Directory /workspace/94.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.16891199399108423789762047011369460056917296014388458840288832203672641737119
Short name T1897
Test name
Test status
Simulation time 45555727 ps
CPU time 6.09 seconds
Started Nov 22 03:13:16 PM PST 23
Finished Nov 22 03:13:23 PM PST 23
Peak memory 552376 kb
Host smart-88c5e0d8-f7a2-4c69-8ca9-e7a8ca0e3948
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16891199399108423789762047011369460056917296014388458840288832203672641737119 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays.16891199399108423789762047011369460056917296014388458840288832203672641737119
Directory /workspace/94.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all.78889276418538327285023784607489447708202605154693547907945865001674185741293
Short name T1848
Test name
Test status
Simulation time 13992004073 ps
CPU time 520.2 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:21:58 PM PST 23
Peak memory 555912 kb
Host smart-6f146225-9a8a-416e-b318-f6ec8873aadf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78889276418538327285023784607489447708202605154693547907945865001674185741293 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.78889276418538327285023784607489447708202605154693547907945865001674185741293
Directory /workspace/94.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.37565868113033812300729411078065554263198865812890832055062871522941870296508
Short name T1614
Test name
Test status
Simulation time 13999524073 ps
CPU time 464.85 seconds
Started Nov 22 03:13:27 PM PST 23
Finished Nov 22 03:21:13 PM PST 23
Peak memory 555548 kb
Host smart-59291ed4-1616-490d-a3a4-ac8dd2bf98af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565868113033812300729411078065554263198865812890832055062871522941870296508 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.37565868113033812300729411078065554263198865812890832055062871522941870296508
Directory /workspace/94.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.53557429463353831566690087967612240994669048909955826422321082161574653387658
Short name T168
Test name
Test status
Simulation time 4815189184 ps
CPU time 351.49 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:19:10 PM PST 23
Peak memory 557256 kb
Host smart-2f9c63f7-47e1-489a-ace4-022cb8f65597
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53557429463353831566690087967612240994669048909955826422321082161574653387658 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_rand_reset.53557429463353831566690087967612240994669048909955826422321082
161574653387658
Directory /workspace/94.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.6652807408728934905679348393149405837340119847589346098072246846900148516884
Short name T996
Test name
Test status
Simulation time 4815189184 ps
CPU time 303.99 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:18:22 PM PST 23
Peak memory 559624 kb
Host smart-9ca2a429-c9d0-4660-ac76-9df7e6d322ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6652807408728934905679348393149405837340119847589346098072246846900148516884 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_reset_error.6652807408728934905679348393149405837340119847589346098072246
846900148516884
Directory /workspace/94.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.70865223441074078899259185468224510796762681690758578314071771527234995769515
Short name T1047
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.26 seconds
Started Nov 22 03:13:21 PM PST 23
Finished Nov 22 03:14:09 PM PST 23
Peak memory 553608 kb
Host smart-e1e5505f-9ae4-4562-8584-1f7fe60b39f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70865223441074078899259185468224510796762681690758578314071771527234995769515 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.70865223441074078899259185468224510796762681690758578314071771527234995769515
Directory /workspace/94.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device.29416179735437498863756470856422260632609261494764015468567733930712579442837
Short name T1510
Test name
Test status
Simulation time 2590995727 ps
CPU time 104.72 seconds
Started Nov 22 03:13:17 PM PST 23
Finished Nov 22 03:15:02 PM PST 23
Peak memory 554820 kb
Host smart-fe00bc48-5189-4bec-befe-7ff4734e5463
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29416179735437498863756470856422260632609261494764015468567733930712579442837 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.29416179735437498863756470856422260632609261494764015468567733930712579442837
Directory /workspace/95.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.64406488046604966892526495291529345199256839127071957623787182633278978204527
Short name T553
Test name
Test status
Simulation time 115195295727 ps
CPU time 2033.85 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:47:13 PM PST 23
Peak memory 554884 kb
Host smart-60961609-7221-4b23-a9d6-b7f3f7673834
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64406488046604966892526495291529345199256839127071957623787182633278978204527 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device_slow_rsp.64406488046604966892526495291529345199256839127071957623787182633278978204527
Directory /workspace/95.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.72200277322486475709635833982926501037996088768160802409301813502663821037821
Short name T1619
Test name
Test status
Simulation time 1171215727 ps
CPU time 43.51 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:14:03 PM PST 23
Peak memory 553392 kb
Host smart-b2407a9d-f9c2-46d7-803f-a5b5e860b9c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72200277322486475709635833982926501037996088768160802409301813502663821037821 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr.72200277322486475709635833982926501037996088768160802409301813502663821037821
Directory /workspace/95.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_random.93789759161603447127795140944381399170300079594825369371274033834563492142582
Short name T363
Test name
Test status
Simulation time 2231375727 ps
CPU time 66.13 seconds
Started Nov 22 03:13:17 PM PST 23
Finished Nov 22 03:14:24 PM PST 23
Peak memory 553620 kb
Host smart-81d3ddc9-9dc6-4667-8951-8d7aaf19a6ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93789759161603447127795140944381399170300079594825369371274033834563492142582 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 95.xbar_error_random.93789759161603447127795140944381399170300079594825369371274033834563492142582
Directory /workspace/95.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random.73286498768880623698611661213986433555968094487735272030909790233928137185291
Short name T920
Test name
Test status
Simulation time 2231375727 ps
CPU time 79.4 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:14:39 PM PST 23
Peak memory 553740 kb
Host smart-baa972e1-e331-47b9-baa2-99b991df1edb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73286498768880623698611661213986433555968094487735272030909790233928137185291 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 95.xbar_random.73286498768880623698611661213986433555968094487735272030909790233928137185291
Directory /workspace/95.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.20030253315758613536503755391119364759390067800064829236584180807385444008051
Short name T260
Test name
Test status
Simulation time 97702135727 ps
CPU time 1161.91 seconds
Started Nov 22 03:13:17 PM PST 23
Finished Nov 22 03:32:40 PM PST 23
Peak memory 553600 kb
Host smart-eca6eac9-c4be-4845-96c4-4bc93e05d47f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20030253315758613536503755391119364759390067800064829236584180807385444008051 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.20030253315758613536503755391119364759390067800064829236584180807385444008051
Directory /workspace/95.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.87990528932571643319510972910580606129476346969904833479842402406316023793798
Short name T981
Test name
Test status
Simulation time 60576345727 ps
CPU time 1119.08 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:31:58 PM PST 23
Peak memory 553712 kb
Host smart-2594089b-1c87-4259-a9a4-174a237dc7c5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87990528932571643319510972910580606129476346969904833479842402406316023793798 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.87990528932571643319510972910580606129476346969904833479842402406316023793798
Directory /workspace/95.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.29214553392540979764902223157134924136282278241025515354024209630770961733265
Short name T1757
Test name
Test status
Simulation time 556965727 ps
CPU time 46.89 seconds
Started Nov 22 03:13:27 PM PST 23
Finished Nov 22 03:14:15 PM PST 23
Peak memory 553716 kb
Host smart-be4c0985-8cab-4012-8907-c30497a0544c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29214553392540979764902223157134924136282278241025515354024209630770961733265 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_delays.29214553392540979764902223157134924136282278241025515354024209630770961733265
Directory /workspace/95.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_same_source.46414012332640813725668698897087601827389347673584736192915237588617329941420
Short name T416
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.19 seconds
Started Nov 22 03:13:17 PM PST 23
Finished Nov 22 03:14:34 PM PST 23
Peak memory 553704 kb
Host smart-3c104d62-c1de-4eec-a8e3-f72d5887b96a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46414012332640813725668698897087601827389347673584736192915237588617329941420 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.46414012332640813725668698897087601827389347673584736192915237588617329941420
Directory /workspace/95.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke.31349940377211929273711004015938174172036255439584107148113204013842372152344
Short name T934
Test name
Test status
Simulation time 196985727 ps
CPU time 8.81 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:13:27 PM PST 23
Peak memory 552280 kb
Host smart-2328345d-7030-4d0b-8aba-d272c0ceef51
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31349940377211929273711004015938174172036255439584107148113204013842372152344 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 95.xbar_smoke.31349940377211929273711004015938174172036255439584107148113204013842372152344
Directory /workspace/95.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.43308438071547042505734198073907780434007659620637112780578739042120029716005
Short name T1656
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.88 seconds
Started Nov 22 03:13:20 PM PST 23
Finished Nov 22 03:14:52 PM PST 23
Peak memory 552364 kb
Host smart-ac310490-a050-46e5-8ede-6f52c4c192df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43308438071547042505734198073907780434007659620637112780578739042120029716005 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.43308438071547042505734198073907780434007659620637112780578739042120029716005
Directory /workspace/95.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.80434047956834552601297131176228041518041997982758353714311784258877271934058
Short name T378
Test name
Test status
Simulation time 4856075727 ps
CPU time 89.48 seconds
Started Nov 22 03:13:17 PM PST 23
Finished Nov 22 03:14:47 PM PST 23
Peak memory 552452 kb
Host smart-9514588d-22b8-4703-962f-ea5705ece7c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80434047956834552601297131176228041518041997982758353714311784258877271934058 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.80434047956834552601297131176228041518041997982758353714311784258877271934058
Directory /workspace/95.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.56127689319655709293851177930507203538873577415938597430445528283539545741838
Short name T723
Test name
Test status
Simulation time 45555727 ps
CPU time 6.22 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:13:25 PM PST 23
Peak memory 552372 kb
Host smart-57859be9-c913-49a6-a48f-ce75a005cc97
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56127689319655709293851177930507203538873577415938597430445528283539545741838 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays.56127689319655709293851177930507203538873577415938597430445528283539545741838
Directory /workspace/95.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.36521277491775055627117635606021365575460751384831217655424720097971883534968
Short name T626
Test name
Test status
Simulation time 13999524073 ps
CPU time 466.31 seconds
Started Nov 22 03:13:26 PM PST 23
Finished Nov 22 03:21:13 PM PST 23
Peak memory 555836 kb
Host smart-7b0fe10a-afa8-47ca-95e3-dba590be3920
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36521277491775055627117635606021365575460751384831217655424720097971883534968 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.36521277491775055627117635606021365575460751384831217655424720097971883534968
Directory /workspace/95.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.6124807634240546649478255932340081977205338528256592319294146941551983127377
Short name T1154
Test name
Test status
Simulation time 4815189184 ps
CPU time 365.66 seconds
Started Nov 22 03:13:16 PM PST 23
Finished Nov 22 03:19:22 PM PST 23
Peak memory 557200 kb
Host smart-6ef65de5-b41d-45ad-96c1-a0742d07ec86
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6124807634240546649478255932340081977205338528256592319294146941551983127377 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_rand_reset.612480763424054664947825593234008197720533852825659231929414694
1551983127377
Directory /workspace/95.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.61313876163685421549207306595802774124832425201810346384699638510820625849902
Short name T473
Test name
Test status
Simulation time 4815189184 ps
CPU time 295.3 seconds
Started Nov 22 03:13:20 PM PST 23
Finished Nov 22 03:18:16 PM PST 23
Peak memory 559708 kb
Host smart-f03d6c4d-dab6-4eaf-9c4e-5fa770b1db91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61313876163685421549207306595802774124832425201810346384699638510820625849902 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_reset_error.613138761636854215492073065958027741248324252018103463846996
38510820625849902
Directory /workspace/95.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.37939007646612713934112834201937000022333084634097245455974634504455390986949
Short name T1829
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.68 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:14:09 PM PST 23
Peak memory 553624 kb
Host smart-98298f9f-5908-4fbb-82a1-405ea2943c73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939007646612713934112834201937000022333084634097245455974634504455390986949 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.37939007646612713934112834201937000022333084634097245455974634504455390986949
Directory /workspace/95.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device.101867111388817871641196704947519745203201007631603667766179611122525307582852
Short name T1144
Test name
Test status
Simulation time 2590995727 ps
CPU time 100.42 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:15:00 PM PST 23
Peak memory 554764 kb
Host smart-869d2815-85b1-4479-99cb-009d72ffea6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101867111388817871641196704947519745203201007631603667766179611122525307582852 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.101867111388817871641196704947519745203201007631603667766179611122525307582852
Directory /workspace/96.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.20076097826465512552315984601304606973393214875561169372281259834011363705498
Short name T817
Test name
Test status
Simulation time 115195295727 ps
CPU time 2091.45 seconds
Started Nov 22 03:13:32 PM PST 23
Finished Nov 22 03:48:24 PM PST 23
Peak memory 554692 kb
Host smart-da9e75e8-3bf2-4299-bbde-0071150bb84b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20076097826465512552315984601304606973393214875561169372281259834011363705498 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device_slow_rsp.20076097826465512552315984601304606973393214875561169372281259834011363705498
Directory /workspace/96.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.74727027250937960015985057194340768269144070103741855099594291230718111257794
Short name T1773
Test name
Test status
Simulation time 1171215727 ps
CPU time 46.02 seconds
Started Nov 22 03:13:22 PM PST 23
Finished Nov 22 03:14:09 PM PST 23
Peak memory 553508 kb
Host smart-cd3ba58f-e3dd-4536-8ce6-d8bfde9d5128
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74727027250937960015985057194340768269144070103741855099594291230718111257794 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr.74727027250937960015985057194340768269144070103741855099594291230718111257794
Directory /workspace/96.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_random.39969632329635846159238562409423296606766956649631804761659876836350443151185
Short name T1182
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.51 seconds
Started Nov 22 03:13:23 PM PST 23
Finished Nov 22 03:14:37 PM PST 23
Peak memory 553544 kb
Host smart-fab6a664-6514-4453-bf3d-cbb7ade8e2b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39969632329635846159238562409423296606766956649631804761659876836350443151185 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 96.xbar_error_random.39969632329635846159238562409423296606766956649631804761659876836350443151185
Directory /workspace/96.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random.41984586467423387669726167824255887280494305852923987181063749042019763984557
Short name T1909
Test name
Test status
Simulation time 2231375727 ps
CPU time 76.99 seconds
Started Nov 22 03:13:17 PM PST 23
Finished Nov 22 03:14:34 PM PST 23
Peak memory 553716 kb
Host smart-5d5c947f-27be-473d-abb1-a481a9635dc1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984586467423387669726167824255887280494305852923987181063749042019763984557 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 96.xbar_random.41984586467423387669726167824255887280494305852923987181063749042019763984557
Directory /workspace/96.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.85577280451010913280315446300016082523461277391694334554014183456920459859782
Short name T257
Test name
Test status
Simulation time 97702135727 ps
CPU time 1165.43 seconds
Started Nov 22 03:13:29 PM PST 23
Finished Nov 22 03:32:55 PM PST 23
Peak memory 553612 kb
Host smart-92ec677f-a5c3-4246-aadc-253e510f4264
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85577280451010913280315446300016082523461277391694334554014183456920459859782 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.85577280451010913280315446300016082523461277391694334554014183456920459859782
Directory /workspace/96.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.58733200251698961967675130127422196489344773672493851726470592838339327454399
Short name T307
Test name
Test status
Simulation time 60576345727 ps
CPU time 1071.09 seconds
Started Nov 22 03:13:15 PM PST 23
Finished Nov 22 03:31:07 PM PST 23
Peak memory 553664 kb
Host smart-9ac7e614-c5b6-4630-a7ca-fcf1623ebc9e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58733200251698961967675130127422196489344773672493851726470592838339327454399 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.58733200251698961967675130127422196489344773672493851726470592838339327454399
Directory /workspace/96.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.55601925649517334003556118891292088922237329105350446914308536087879153156190
Short name T888
Test name
Test status
Simulation time 556965727 ps
CPU time 46.46 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:14:06 PM PST 23
Peak memory 553696 kb
Host smart-dc903d33-9a76-495f-abc1-a38bd32fa848
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55601925649517334003556118891292088922237329105350446914308536087879153156190 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_delays.55601925649517334003556118891292088922237329105350446914308536087879153156190
Directory /workspace/96.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_same_source.12442250290354313057314016956331753424488635420885620453656293596662194721352
Short name T820
Test name
Test status
Simulation time 2498784073 ps
CPU time 68.12 seconds
Started Nov 22 03:13:29 PM PST 23
Finished Nov 22 03:14:38 PM PST 23
Peak memory 553696 kb
Host smart-6e6f48e2-56de-4a09-831b-d690eb63e19a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12442250290354313057314016956331753424488635420885620453656293596662194721352 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.12442250290354313057314016956331753424488635420885620453656293596662194721352
Directory /workspace/96.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke.56835295334817375126376476384177740193949647178781402640942697231626466591961
Short name T488
Test name
Test status
Simulation time 196985727 ps
CPU time 8.2 seconds
Started Nov 22 03:13:17 PM PST 23
Finished Nov 22 03:13:26 PM PST 23
Peak memory 552404 kb
Host smart-399d2b9a-21e5-4c7f-98ab-78612114ddf3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56835295334817375126376476384177740193949647178781402640942697231626466591961 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 96.xbar_smoke.56835295334817375126376476384177740193949647178781402640942697231626466591961
Directory /workspace/96.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.40663422524103759952189482623690089364639237304007507463229049813179084170159
Short name T911
Test name
Test status
Simulation time 7758585727 ps
CPU time 88.65 seconds
Started Nov 22 03:13:18 PM PST 23
Finished Nov 22 03:14:47 PM PST 23
Peak memory 552384 kb
Host smart-e801a901-061e-4eae-8a32-d7fc66c239c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40663422524103759952189482623690089364639237304007507463229049813179084170159 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.40663422524103759952189482623690089364639237304007507463229049813179084170159
Directory /workspace/96.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.74592459178125971989486156978239108445014517080356771413639985244766392379534
Short name T242
Test name
Test status
Simulation time 4856075727 ps
CPU time 92.95 seconds
Started Nov 22 03:13:32 PM PST 23
Finished Nov 22 03:15:05 PM PST 23
Peak memory 552308 kb
Host smart-fa5515d3-058b-4c9e-b81f-e6a091ccba10
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74592459178125971989486156978239108445014517080356771413639985244766392379534 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.74592459178125971989486156978239108445014517080356771413639985244766392379534
Directory /workspace/96.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.63860988428135175058207931844454001729132981864821595399623243724697865276390
Short name T1401
Test name
Test status
Simulation time 45555727 ps
CPU time 6 seconds
Started Nov 22 03:13:20 PM PST 23
Finished Nov 22 03:13:27 PM PST 23
Peak memory 552252 kb
Host smart-72573b25-c405-4f44-b559-bd4322029177
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63860988428135175058207931844454001729132981864821595399623243724697865276390 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays.63860988428135175058207931844454001729132981864821595399623243724697865276390
Directory /workspace/96.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all.40387942636977658801045308818342251022888613713623116881901547035809612807590
Short name T1398
Test name
Test status
Simulation time 13992004073 ps
CPU time 516.62 seconds
Started Nov 22 03:13:29 PM PST 23
Finished Nov 22 03:22:07 PM PST 23
Peak memory 555840 kb
Host smart-bc3bde76-e3a1-475a-b1ac-3ca2593ade82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387942636977658801045308818342251022888613713623116881901547035809612807590 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.40387942636977658801045308818342251022888613713623116881901547035809612807590
Directory /workspace/96.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.93786101129845523413218143958826459577544127086593756911966367737323183156900
Short name T644
Test name
Test status
Simulation time 13999524073 ps
CPU time 479.21 seconds
Started Nov 22 03:13:30 PM PST 23
Finished Nov 22 03:21:29 PM PST 23
Peak memory 555724 kb
Host smart-7475296a-c8a4-495b-961f-6b7564a2e7a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93786101129845523413218143958826459577544127086593756911966367737323183156900 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.93786101129845523413218143958826459577544127086593756911966367737323183156900
Directory /workspace/96.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.103537289190797733518347209422240393744815442705256120765469227787065674034819
Short name T341
Test name
Test status
Simulation time 4815189184 ps
CPU time 362.41 seconds
Started Nov 22 03:13:33 PM PST 23
Finished Nov 22 03:19:37 PM PST 23
Peak memory 557144 kb
Host smart-9ab37c9b-fea9-4a69-bad0-0cc298ad3e91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103537289190797733518347209422240393744815442705256120765469227787065674034819 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_rand_reset.1035372891907977335183472094222403937448154427052561207654692
27787065674034819
Directory /workspace/96.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.32591126812609004336465192875561289637435387213663947857431076197627455499004
Short name T373
Test name
Test status
Simulation time 4815189184 ps
CPU time 309.65 seconds
Started Nov 22 03:13:33 PM PST 23
Finished Nov 22 03:18:44 PM PST 23
Peak memory 559604 kb
Host smart-e6d2c0e5-bbb9-4bb5-955b-58048063c44e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591126812609004336465192875561289637435387213663947857431076197627455499004 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_reset_error.325911268126090043364651928755612896374353872136639478574310
76197627455499004
Directory /workspace/96.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.99387942978368313839614786479310432011641504476363553331610200956508856149544
Short name T790
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.82 seconds
Started Nov 22 03:13:20 PM PST 23
Finished Nov 22 03:14:12 PM PST 23
Peak memory 553704 kb
Host smart-491677f3-39e5-4ed5-bcec-3f3e559f7676
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99387942978368313839614786479310432011641504476363553331610200956508856149544 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.99387942978368313839614786479310432011641504476363553331610200956508856149544
Directory /workspace/96.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device.44374630064071467319630623260637109105401801115779847088374791725179109436570
Short name T494
Test name
Test status
Simulation time 2590995727 ps
CPU time 114.65 seconds
Started Nov 22 03:13:46 PM PST 23
Finished Nov 22 03:15:41 PM PST 23
Peak memory 554784 kb
Host smart-f831c4cb-f090-47fd-ae67-17c497a5c1da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44374630064071467319630623260637109105401801115779847088374791725179109436570 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.44374630064071467319630623260637109105401801115779847088374791725179109436570
Directory /workspace/97.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3795220119835072619373376657233995196235637372878549330717104964642489163229
Short name T1036
Test name
Test status
Simulation time 115195295727 ps
CPU time 2002.16 seconds
Started Nov 22 03:13:43 PM PST 23
Finished Nov 22 03:47:07 PM PST 23
Peak memory 554772 kb
Host smart-73b1024c-2020-400d-8027-3c711b74389f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795220119835072619373376657233995196235637372878549330717104964642489163229 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device_slow_rsp.3795220119835072619373376657233995196235637372878549330717104964642489163229
Directory /workspace/97.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.13522221228776880445949626929851071681815152325822052989310844089020873656000
Short name T1913
Test name
Test status
Simulation time 1171215727 ps
CPU time 45.43 seconds
Started Nov 22 03:13:43 PM PST 23
Finished Nov 22 03:14:29 PM PST 23
Peak memory 553464 kb
Host smart-b274cbde-03c3-40ed-a312-1877e2e823e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13522221228776880445949626929851071681815152325822052989310844089020873656000 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr.13522221228776880445949626929851071681815152325822052989310844089020873656000
Directory /workspace/97.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_random.54085224490725102895879044359307708780095505740682017590409048133735122744175
Short name T630
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.43 seconds
Started Nov 22 03:13:45 PM PST 23
Finished Nov 22 03:14:59 PM PST 23
Peak memory 553480 kb
Host smart-0145c1aa-6c32-4905-97b6-72869f5adb29
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54085224490725102895879044359307708780095505740682017590409048133735122744175 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 97.xbar_error_random.54085224490725102895879044359307708780095505740682017590409048133735122744175
Directory /workspace/97.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random.62888873780578714898536957564050183763749468180080227729335050375870455336693
Short name T1870
Test name
Test status
Simulation time 2231375727 ps
CPU time 75.65 seconds
Started Nov 22 03:13:51 PM PST 23
Finished Nov 22 03:15:08 PM PST 23
Peak memory 553852 kb
Host smart-5872d83d-9895-47a2-b4d9-2be68da7e4b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62888873780578714898536957564050183763749468180080227729335050375870455336693 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 97.xbar_random.62888873780578714898536957564050183763749468180080227729335050375870455336693
Directory /workspace/97.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.23520795508655059373449285945017014532163780883517031585128605560971348610262
Short name T880
Test name
Test status
Simulation time 97702135727 ps
CPU time 1171.57 seconds
Started Nov 22 03:13:44 PM PST 23
Finished Nov 22 03:33:16 PM PST 23
Peak memory 553628 kb
Host smart-cf290e50-2623-48cf-8fc4-dc688437e6e8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23520795508655059373449285945017014532163780883517031585128605560971348610262 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.23520795508655059373449285945017014532163780883517031585128605560971348610262
Directory /workspace/97.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.44941996600764088198121066361862070615432058111760572429703003622101129456109
Short name T861
Test name
Test status
Simulation time 60576345727 ps
CPU time 1101.43 seconds
Started Nov 22 03:13:52 PM PST 23
Finished Nov 22 03:32:14 PM PST 23
Peak memory 553736 kb
Host smart-68317941-4e53-4064-b9e8-4f60bc32a56c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44941996600764088198121066361862070615432058111760572429703003622101129456109 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.44941996600764088198121066361862070615432058111760572429703003622101129456109
Directory /workspace/97.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.53618226581364040090211606069029173840380894515747723104017550877279831251024
Short name T1322
Test name
Test status
Simulation time 556965727 ps
CPU time 48.09 seconds
Started Nov 22 03:13:34 PM PST 23
Finished Nov 22 03:14:23 PM PST 23
Peak memory 553708 kb
Host smart-0b2d52d3-835c-4333-a85c-8bb932468334
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53618226581364040090211606069029173840380894515747723104017550877279831251024 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_delays.53618226581364040090211606069029173840380894515747723104017550877279831251024
Directory /workspace/97.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_same_source.64878462415396734561081016282798684859198622959066699287624764606506140129973
Short name T461
Test name
Test status
Simulation time 2498784073 ps
CPU time 79.91 seconds
Started Nov 22 03:13:42 PM PST 23
Finished Nov 22 03:15:03 PM PST 23
Peak memory 553828 kb
Host smart-6cc916cf-417f-4014-8a97-03fc858da980
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64878462415396734561081016282798684859198622959066699287624764606506140129973 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.64878462415396734561081016282798684859198622959066699287624764606506140129973
Directory /workspace/97.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke.88120782287537798398281420892271600497101824723633564450197987998430802414980
Short name T151
Test name
Test status
Simulation time 196985727 ps
CPU time 8.21 seconds
Started Nov 22 03:13:21 PM PST 23
Finished Nov 22 03:13:30 PM PST 23
Peak memory 552368 kb
Host smart-6c7ab1c3-7fc3-430b-8cf9-6009eb872d43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88120782287537798398281420892271600497101824723633564450197987998430802414980 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 97.xbar_smoke.88120782287537798398281420892271600497101824723633564450197987998430802414980
Directory /workspace/97.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.114244155865105793463651941407740189329987375382375022369095458465743393406899
Short name T567
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.76 seconds
Started Nov 22 03:13:30 PM PST 23
Finished Nov 22 03:15:00 PM PST 23
Peak memory 552380 kb
Host smart-d88af49b-9c8f-4339-a777-74a129adf5f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114244155865105793463651941407740189329987375382375022369095458465743393406899 -assert nopo
stproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.114244155865105793463651941407740189329987375382375022369095458465743393406899
Directory /workspace/97.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.71305186304517887949048791120199662599219301062100022463283265946463176847173
Short name T1062
Test name
Test status
Simulation time 4856075727 ps
CPU time 84.12 seconds
Started Nov 22 03:13:32 PM PST 23
Finished Nov 22 03:14:57 PM PST 23
Peak memory 552412 kb
Host smart-7552ec59-72f4-4d12-b258-3af2f1474f19
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71305186304517887949048791120199662599219301062100022463283265946463176847173 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.71305186304517887949048791120199662599219301062100022463283265946463176847173
Directory /workspace/97.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.72844890543693316789081086429615441782804981975423617299858895706957139146594
Short name T784
Test name
Test status
Simulation time 45555727 ps
CPU time 5.81 seconds
Started Nov 22 03:13:19 PM PST 23
Finished Nov 22 03:13:25 PM PST 23
Peak memory 552360 kb
Host smart-ed6a45e1-db42-4b29-a727-c8257da07ef2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72844890543693316789081086429615441782804981975423617299858895706957139146594 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays.72844890543693316789081086429615441782804981975423617299858895706957139146594
Directory /workspace/97.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all.76231275838031190201037300122567370940799358851334115274732039706508416796177
Short name T391
Test name
Test status
Simulation time 13992004073 ps
CPU time 475.81 seconds
Started Nov 22 03:13:44 PM PST 23
Finished Nov 22 03:21:41 PM PST 23
Peak memory 555900 kb
Host smart-b8e26058-1732-4d32-bc90-9a0c91ba6625
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76231275838031190201037300122567370940799358851334115274732039706508416796177 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.76231275838031190201037300122567370940799358851334115274732039706508416796177
Directory /workspace/97.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.42279512309635674130070146787164249972348192856812675400742185137575823319368
Short name T527
Test name
Test status
Simulation time 13999524073 ps
CPU time 466.64 seconds
Started Nov 22 03:13:54 PM PST 23
Finished Nov 22 03:21:41 PM PST 23
Peak memory 555636 kb
Host smart-1bf07266-8b42-4876-b3da-5c8e5e1e3cc5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42279512309635674130070146787164249972348192856812675400742185137575823319368 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.42279512309635674130070146787164249972348192856812675400742185137575823319368
Directory /workspace/97.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.35714431678834843676545721030504109601902736095258218146794967597486428943284
Short name T128
Test name
Test status
Simulation time 4815189184 ps
CPU time 350.13 seconds
Started Nov 22 03:13:42 PM PST 23
Finished Nov 22 03:19:34 PM PST 23
Peak memory 557284 kb
Host smart-6134226f-ed38-4206-b389-12bf28fc03d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35714431678834843676545721030504109601902736095258218146794967597486428943284 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_rand_reset.35714431678834843676545721030504109601902736095258218146794967
597486428943284
Directory /workspace/97.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.70801993866221276291034346707811889402177971152890698307071895026942073084939
Short name T171
Test name
Test status
Simulation time 4815189184 ps
CPU time 306.32 seconds
Started Nov 22 03:13:34 PM PST 23
Finished Nov 22 03:18:41 PM PST 23
Peak memory 559676 kb
Host smart-15e969e7-af1a-4d22-abb6-b391c9ac740f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70801993866221276291034346707811889402177971152890698307071895026942073084939 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_reset_error.708019938662212762910343467078118894021779711528906983070718
95026942073084939
Directory /workspace/97.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.39310010623874980492597087786162480612530405982365510549490648333621375043372
Short name T579
Test name
Test status
Simulation time 1176995727 ps
CPU time 50.11 seconds
Started Nov 22 03:13:33 PM PST 23
Finished Nov 22 03:14:24 PM PST 23
Peak memory 553712 kb
Host smart-aa0c2957-fdc2-4b23-9697-906e3c858e89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39310010623874980492597087786162480612530405982365510549490648333621375043372 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.39310010623874980492597087786162480612530405982365510549490648333621375043372
Directory /workspace/97.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device.21812762054070477101287158850087956043515297262654604509658766798411080025327
Short name T1548
Test name
Test status
Simulation time 2590995727 ps
CPU time 105.03 seconds
Started Nov 22 03:13:47 PM PST 23
Finished Nov 22 03:15:32 PM PST 23
Peak memory 554756 kb
Host smart-974bca45-bd72-4551-b858-6019042dbcf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812762054070477101287158850087956043515297262654604509658766798411080025327 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.21812762054070477101287158850087956043515297262654604509658766798411080025327
Directory /workspace/98.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.51965464153018362471780974358971934289751881643513760344276661746366430088575
Short name T1037
Test name
Test status
Simulation time 115195295727 ps
CPU time 2066.81 seconds
Started Nov 22 03:13:53 PM PST 23
Finished Nov 22 03:48:21 PM PST 23
Peak memory 554788 kb
Host smart-b606e298-e74b-4fac-aa6e-f951c0afdde0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51965464153018362471780974358971934289751881643513760344276661746366430088575 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device_slow_rsp.51965464153018362471780974358971934289751881643513760344276661746366430088575
Directory /workspace/98.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1943723496775523571856813710469163762195037575428419345871723609294408016545
Short name T1280
Test name
Test status
Simulation time 1171215727 ps
CPU time 41.8 seconds
Started Nov 22 03:13:45 PM PST 23
Finished Nov 22 03:14:28 PM PST 23
Peak memory 553472 kb
Host smart-9f062810-cdb9-453c-af43-71e026284b6f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943723496775523571856813710469163762195037575428419345871723609294408016545 -assert nopostproc +UVM_
TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr.1943723496775523571856813710469163762195037575428419345871723609294408016545
Directory /workspace/98.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_random.53686291419990844533289326829502569433272827431013360642538172651504671282102
Short name T481
Test name
Test status
Simulation time 2231375727 ps
CPU time 67.28 seconds
Started Nov 22 03:13:46 PM PST 23
Finished Nov 22 03:14:54 PM PST 23
Peak memory 553576 kb
Host smart-d3cf40bb-5ec2-4ff6-b64e-a3ada03c974d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53686291419990844533289326829502569433272827431013360642538172651504671282102 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 98.xbar_error_random.53686291419990844533289326829502569433272827431013360642538172651504671282102
Directory /workspace/98.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random.26574980527409538851373494598023287987900476852075258275291672630784652720640
Short name T1488
Test name
Test status
Simulation time 2231375727 ps
CPU time 77.22 seconds
Started Nov 22 03:13:52 PM PST 23
Finished Nov 22 03:15:10 PM PST 23
Peak memory 553756 kb
Host smart-df9dd895-15ad-4a96-a8d1-1715582d8cfe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26574980527409538851373494598023287987900476852075258275291672630784652720640 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 98.xbar_random.26574980527409538851373494598023287987900476852075258275291672630784652720640
Directory /workspace/98.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.40703431404419760132981903528598951463391716107748825913860066826611311254080
Short name T1895
Test name
Test status
Simulation time 97702135727 ps
CPU time 1147.68 seconds
Started Nov 22 03:13:34 PM PST 23
Finished Nov 22 03:32:42 PM PST 23
Peak memory 553728 kb
Host smart-75d558d9-53aa-4b88-86ac-53723d4eaf7d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40703431404419760132981903528598951463391716107748825913860066826611311254080 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.40703431404419760132981903528598951463391716107748825913860066826611311254080
Directory /workspace/98.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.3964287770287320133069855646593374916417199589978939179013385240146212594208
Short name T1742
Test name
Test status
Simulation time 60576345727 ps
CPU time 1067.57 seconds
Started Nov 22 03:13:43 PM PST 23
Finished Nov 22 03:31:32 PM PST 23
Peak memory 553704 kb
Host smart-1c8e520a-9623-4476-86a6-28249d9e43c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964287770287320133069855646593374916417199589978939179013385240146212594208 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.3964287770287320133069855646593374916417199589978939179013385240146212594208
Directory /workspace/98.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.77723301191073572158107079521699589782380266630922866646853694379674454422883
Short name T1639
Test name
Test status
Simulation time 556965727 ps
CPU time 44.92 seconds
Started Nov 22 03:13:34 PM PST 23
Finished Nov 22 03:14:20 PM PST 23
Peak memory 553708 kb
Host smart-ce7da90b-9c73-4b57-88db-fc1a1841de62
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77723301191073572158107079521699589782380266630922866646853694379674454422883 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delays.77723301191073572158107079521699589782380266630922866646853694379674454422883
Directory /workspace/98.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_same_source.68366319556474824786113370627138455662654022718421080192273036102063257187181
Short name T107
Test name
Test status
Simulation time 2498784073 ps
CPU time 76.66 seconds
Started Nov 22 03:13:55 PM PST 23
Finished Nov 22 03:15:13 PM PST 23
Peak memory 553744 kb
Host smart-18a542ec-6719-44ad-aeab-312d7e95de8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68366319556474824786113370627138455662654022718421080192273036102063257187181 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.68366319556474824786113370627138455662654022718421080192273036102063257187181
Directory /workspace/98.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke.81814137728986036310203634652877824947548885624554354461351194072774192415404
Short name T1727
Test name
Test status
Simulation time 196985727 ps
CPU time 8.63 seconds
Started Nov 22 03:13:44 PM PST 23
Finished Nov 22 03:13:54 PM PST 23
Peak memory 552372 kb
Host smart-88dbe8be-07b6-4f63-aec0-51a75aeeb742
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81814137728986036310203634652877824947548885624554354461351194072774192415404 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 98.xbar_smoke.81814137728986036310203634652877824947548885624554354461351194072774192415404
Directory /workspace/98.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.61498720091484209181724359282554491375477213131535153729890588088398922697747
Short name T203
Test name
Test status
Simulation time 7758585727 ps
CPU time 89.7 seconds
Started Nov 22 03:13:34 PM PST 23
Finished Nov 22 03:15:04 PM PST 23
Peak memory 552384 kb
Host smart-d8c5b2b5-3618-4e73-a855-014ea43cff8c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61498720091484209181724359282554491375477213131535153729890588088398922697747 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.61498720091484209181724359282554491375477213131535153729890588088398922697747
Directory /workspace/98.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.12843896333679858662084168172373700570482980345223134418634347192486305346740
Short name T901
Test name
Test status
Simulation time 4856075727 ps
CPU time 90.56 seconds
Started Nov 22 03:13:44 PM PST 23
Finished Nov 22 03:15:15 PM PST 23
Peak memory 552392 kb
Host smart-0f3d90ff-c2d8-4cf9-be84-aa1b283dd1f5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12843896333679858662084168172373700570482980345223134418634347192486305346740 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.12843896333679858662084168172373700570482980345223134418634347192486305346740
Directory /workspace/98.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.49716325880197401859543268864291221213415742247215797010052640110585838249520
Short name T948
Test name
Test status
Simulation time 45555727 ps
CPU time 5.9 seconds
Started Nov 22 03:13:45 PM PST 23
Finished Nov 22 03:13:52 PM PST 23
Peak memory 552328 kb
Host smart-27734792-4d5d-4e70-bcf3-26ce0bb7f027
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49716325880197401859543268864291221213415742247215797010052640110585838249520 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays.49716325880197401859543268864291221213415742247215797010052640110585838249520
Directory /workspace/98.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all.86096723260172819212256720559680685598525593383239230900747062527813467158351
Short name T334
Test name
Test status
Simulation time 13992004073 ps
CPU time 501.3 seconds
Started Nov 22 03:13:55 PM PST 23
Finished Nov 22 03:22:17 PM PST 23
Peak memory 555932 kb
Host smart-7c13aa93-c407-4765-8f39-7530303d6a6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86096723260172819212256720559680685598525593383239230900747062527813467158351 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.86096723260172819212256720559680685598525593383239230900747062527813467158351
Directory /workspace/98.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.57598613659322701049501010209997051380024215938913718095325985697771615023718
Short name T1378
Test name
Test status
Simulation time 13999524073 ps
CPU time 518.3 seconds
Started Nov 22 03:13:53 PM PST 23
Finished Nov 22 03:22:32 PM PST 23
Peak memory 555784 kb
Host smart-4676c399-d8c1-4bb3-8ad2-61d1b64d593b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57598613659322701049501010209997051380024215938913718095325985697771615023718 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.57598613659322701049501010209997051380024215938913718095325985697771615023718
Directory /workspace/98.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.80669545995074332916037978696711946759801990684846243704677221329092346028191
Short name T952
Test name
Test status
Simulation time 4815189184 ps
CPU time 368.59 seconds
Started Nov 22 03:13:42 PM PST 23
Finished Nov 22 03:19:53 PM PST 23
Peak memory 557276 kb
Host smart-a9d23ac2-4941-46b1-bf4d-7bfae772b93a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80669545995074332916037978696711946759801990684846243704677221329092346028191 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_rand_reset.80669545995074332916037978696711946759801990684846243704677221
329092346028191
Directory /workspace/98.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.111164303514379533863906952252798786163394655725853699812389797655285097654085
Short name T694
Test name
Test status
Simulation time 4815189184 ps
CPU time 308.29 seconds
Started Nov 22 03:13:53 PM PST 23
Finished Nov 22 03:19:02 PM PST 23
Peak memory 559744 kb
Host smart-484cf2bb-6d72-473f-a87e-8dc305c610c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111164303514379533863906952252798786163394655725853699812389797655285097654085 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_reset_error.11116430351437953386390695225279878616339465572585369981238
9797655285097654085
Directory /workspace/98.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.50648884031367411017728873640297856230324668388906601155391036137473670757723
Short name T1017
Test name
Test status
Simulation time 1176995727 ps
CPU time 48.14 seconds
Started Nov 22 03:13:43 PM PST 23
Finished Nov 22 03:14:33 PM PST 23
Peak memory 553688 kb
Host smart-14e4d76d-ac30-4bf7-aa3b-864844e63c69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50648884031367411017728873640297856230324668388906601155391036137473670757723 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.50648884031367411017728873640297856230324668388906601155391036137473670757723
Directory /workspace/98.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device.77499298046261060741087377827353474202720138610234453968647805140245647883796
Short name T1426
Test name
Test status
Simulation time 2590995727 ps
CPU time 104.97 seconds
Started Nov 22 03:13:52 PM PST 23
Finished Nov 22 03:15:37 PM PST 23
Peak memory 554820 kb
Host smart-e73a4064-9859-4822-acb3-e880b08f57ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77499298046261060741087377827353474202720138610234453968647805140245647883796 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.77499298046261060741087377827353474202720138610234453968647805140245647883796
Directory /workspace/99.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.49708130146561902313962038753435628929839414785165526555912171800989169621286
Short name T538
Test name
Test status
Simulation time 115195295727 ps
CPU time 2086.32 seconds
Started Nov 22 03:13:44 PM PST 23
Finished Nov 22 03:48:31 PM PST 23
Peak memory 554776 kb
Host smart-a6258c62-59cd-42b1-97f0-40001bd13272
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49708130146561902313962038753435628929839414785165526555912171800989169621286 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device_slow_rsp.49708130146561902313962038753435628929839414785165526555912171800989169621286
Directory /workspace/99.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.31374877126748265786401588703680836329264379887638027004305032394896405110741
Short name T609
Test name
Test status
Simulation time 1171215727 ps
CPU time 42.44 seconds
Started Nov 22 03:13:58 PM PST 23
Finished Nov 22 03:14:41 PM PST 23
Peak memory 553472 kb
Host smart-f69a9de3-105f-47fb-b1da-50a0122c283e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31374877126748265786401588703680836329264379887638027004305032394896405110741 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr.31374877126748265786401588703680836329264379887638027004305032394896405110741
Directory /workspace/99.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_random.101420038443731812412937515723923158689975870004329329369078449704377940239955
Short name T532
Test name
Test status
Simulation time 2231375727 ps
CPU time 73.5 seconds
Started Nov 22 03:13:46 PM PST 23
Finished Nov 22 03:15:01 PM PST 23
Peak memory 553528 kb
Host smart-7d1f06e4-0890-42c4-a675-b40ed4c727d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101420038443731812412937515723923158689975870004329329369078449704377940239955 -assert nopostproc +UV
M_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 99.xbar_error_random.101420038443731812412937515723923158689975870004329329369078449704377940239955
Directory /workspace/99.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random.63089620120595934733353098165258938612275309936920513051363313237465504621564
Short name T1355
Test name
Test status
Simulation time 2231375727 ps
CPU time 72.99 seconds
Started Nov 22 03:13:58 PM PST 23
Finished Nov 22 03:15:12 PM PST 23
Peak memory 553740 kb
Host smart-eda7f7da-2882-4946-8f72-0ad4279c8e18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63089620120595934733353098165258938612275309936920513051363313237465504621564 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 99.xbar_random.63089620120595934733353098165258938612275309936920513051363313237465504621564
Directory /workspace/99.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.96861050246094361635358614772313071111415823291821397921380098829391846270634
Short name T282
Test name
Test status
Simulation time 97702135727 ps
CPU time 1172.54 seconds
Started Nov 22 03:13:47 PM PST 23
Finished Nov 22 03:33:20 PM PST 23
Peak memory 553704 kb
Host smart-a458e4a3-86d5-4c61-8ddc-6ab5f6238e3e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96861050246094361635358614772313071111415823291821397921380098829391846270634 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.96861050246094361635358614772313071111415823291821397921380098829391846270634
Directory /workspace/99.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2561342009088755481007747968193066413860997013860042805942456134927490911840
Short name T643
Test name
Test status
Simulation time 60576345727 ps
CPU time 1061.07 seconds
Started Nov 22 03:13:42 PM PST 23
Finished Nov 22 03:31:25 PM PST 23
Peak memory 553700 kb
Host smart-ab6a3ca7-2002-42d0-b9b0-1641e845bcab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561342009088755481007747968193066413860997013860042805942456134927490911840 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2561342009088755481007747968193066413860997013860042805942456134927490911840
Directory /workspace/99.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.28687480332157859495848365496652316135417017372056638250937894734011620107622
Short name T1138
Test name
Test status
Simulation time 556965727 ps
CPU time 46.04 seconds
Started Nov 22 03:13:56 PM PST 23
Finished Nov 22 03:14:42 PM PST 23
Peak memory 553732 kb
Host smart-1f90d892-bc23-42d2-a8d7-d974fb6a0f50
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28687480332157859495848365496652316135417017372056638250937894734011620107622 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delays.28687480332157859495848365496652316135417017372056638250937894734011620107622
Directory /workspace/99.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_same_source.40429325775355124287342823705020565268199579356569746050626850470781839809417
Short name T177
Test name
Test status
Simulation time 2498784073 ps
CPU time 72.27 seconds
Started Nov 22 03:13:47 PM PST 23
Finished Nov 22 03:15:00 PM PST 23
Peak memory 553716 kb
Host smart-860d93a3-30f1-447b-9421-d0d078f66970
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40429325775355124287342823705020565268199579356569746050626850470781839809417 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.40429325775355124287342823705020565268199579356569746050626850470781839809417
Directory /workspace/99.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke.82743142592640267178596923086655164570593941346472869767326756685029738193737
Short name T1601
Test name
Test status
Simulation time 196985727 ps
CPU time 8.89 seconds
Started Nov 22 03:13:46 PM PST 23
Finished Nov 22 03:13:55 PM PST 23
Peak memory 552328 kb
Host smart-059eead6-606a-4458-a2d5-d45efae0a411
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82743142592640267178596923086655164570593941346472869767326756685029738193737 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 99.xbar_smoke.82743142592640267178596923086655164570593941346472869767326756685029738193737
Directory /workspace/99.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.99363823741854083130796332691030210945280497578558717445487806404243394364862
Short name T1435
Test name
Test status
Simulation time 7758585727 ps
CPU time 91.82 seconds
Started Nov 22 03:13:54 PM PST 23
Finished Nov 22 03:15:26 PM PST 23
Peak memory 552372 kb
Host smart-eba35e5c-0caa-4d50-9813-e6a71973353b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99363823741854083130796332691030210945280497578558717445487806404243394364862 -assert nopos
tproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.99363823741854083130796332691030210945280497578558717445487806404243394364862
Directory /workspace/99.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.83982851537905643799846516540373399400184727693753017969130383461243299830146
Short name T152
Test name
Test status
Simulation time 4856075727 ps
CPU time 88.53 seconds
Started Nov 22 03:13:52 PM PST 23
Finished Nov 22 03:15:21 PM PST 23
Peak memory 552376 kb
Host smart-339c2b1e-1022-4741-b00b-0ab48d700831
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83982851537905643799846516540373399400184727693753017969130383461243299830146 -assert nopostpro
c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.83982851537905643799846516540373399400184727693753017969130383461243299830146
Directory /workspace/99.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.87327902646699540984399206212020211292946206527071495170088783506969968293017
Short name T94
Test name
Test status
Simulation time 45555727 ps
CPU time 5.63 seconds
Started Nov 22 03:13:42 PM PST 23
Finished Nov 22 03:13:50 PM PST 23
Peak memory 552384 kb
Host smart-b7080056-2cf8-43a5-a60a-d9fa2cbefec0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87327902646699540984399206212020211292946206527071495170088783506969968293017 -assert
nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays.87327902646699540984399206212020211292946206527071495170088783506969968293017
Directory /workspace/99.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all.105335395319251797921768180391916250417037529357798085987464778708343992723810
Short name T176
Test name
Test status
Simulation time 13992004073 ps
CPU time 530.5 seconds
Started Nov 22 03:13:44 PM PST 23
Finished Nov 22 03:22:35 PM PST 23
Peak memory 555848 kb
Host smart-70ce4f1c-9417-413d-95ca-380e888b7964
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105335395319251797921768180391916250417037529357798085987464778708343992723810 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.105335395319251797921768180391916250417037529357798085987464778708343992723810
Directory /workspace/99.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.89589606834110729472520982294660237038765345271142560510177467711269041367816
Short name T748
Test name
Test status
Simulation time 13999524073 ps
CPU time 451.79 seconds
Started Nov 22 03:13:54 PM PST 23
Finished Nov 22 03:21:27 PM PST 23
Peak memory 555736 kb
Host smart-eb8a7762-4035-47e0-8a08-e82938b8efed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89589606834110729472520982294660237038765345271142560510177467711269041367816 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.89589606834110729472520982294660237038765345271142560510177467711269041367816
Directory /workspace/99.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.29553488036433582368999810992908433750981010978078239284195985655185988458860
Short name T1099
Test name
Test status
Simulation time 4815189184 ps
CPU time 360.14 seconds
Started Nov 22 03:13:56 PM PST 23
Finished Nov 22 03:19:56 PM PST 23
Peak memory 557264 kb
Host smart-30799ba4-f794-49cb-b21a-f5e14d66eb2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553488036433582368999810992908433750981010978078239284195985655185988458860 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_rand_reset.29553488036433582368999810992908433750981010978078239284195985
655185988458860
Directory /workspace/99.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.55806286470612239654182378039167004689212653146428302505166065701938047153744
Short name T1232
Test name
Test status
Simulation time 4815189184 ps
CPU time 292.24 seconds
Started Nov 22 03:13:54 PM PST 23
Finished Nov 22 03:18:47 PM PST 23
Peak memory 559700 kb
Host smart-e72cf197-a2c0-4054-b068-3bc75e6ad23c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55806286470612239654182378039167004689212653146428302505166065701938047153744 -assert nopostproc +UVM
_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_reset_error.558062864706122396541823780391670046892126531464283025051660
65701938047153744
Directory /workspace/99.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.102138576580049382324004230558810649274531430864815134308805502311078038143962
Short name T1703
Test name
Test status
Simulation time 1176995727 ps
CPU time 44.8 seconds
Started Nov 22 03:13:52 PM PST 23
Finished Nov 22 03:14:37 PM PST 23
Peak memory 553716 kb
Host smart-4d9120c0-19b6-44f9-a328-5f3e4b3b3d30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102138576580049382324004230558810649274531430864815134308805502311078038143962 -assert nopostproc +UV
M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.102138576580049382324004230558810649274531430864815134308805502311078038143962
Directory /workspace/99.xbar_unmapped_addr/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.15139171564599780679480516071123447978156046882236599645932690976109075184740
Short name T20
Test name
Test status
Simulation time 19824942265 ps
CPU time 1805.97 seconds
Started Nov 22 03:00:10 PM PST 23
Finished Nov 22 03:30:16 PM PST 23
Peak memory 587416 kb
Host smart-212903e5-058a-4077-aeb8-204dd9ae6891
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15139171564599780679480516071123447978156046882236599645932690976
109075184740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_csr_rw.151391715645997806794805160711234479781560468822365996459326909
76109075184740
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.48880388062736064776935427759863199800108558758047205985076848487667201346204
Short name T17
Test name
Test status
Simulation time 12899942265 ps
CPU time 1174.38 seconds
Started Nov 22 03:00:02 PM PST 23
Finished Nov 22 03:19:37 PM PST 23
Peak memory 587344 kb
Host smart-ffe506ac-0dd1-4f6e-9d8e-d047ff8f5c87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48880388062736064776935427759863199800108558758047205985076848487667201346204 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.48880388062736064776935427759863199800108558758047205985076848487667201346204
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.90363197671015480043228336017794682121948800602284237437000415410528226275015
Short name T36
Test name
Test status
Simulation time 19824942265 ps
CPU time 1957.19 seconds
Started Nov 22 03:01:35 PM PST 23
Finished Nov 22 03:34:13 PM PST 23
Peak memory 587424 kb
Host smart-45ea3312-0f1f-42e5-9aff-6caf1db9d83d
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90363197671015480043228336017794682121948800602284237437000415410
528226275015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_csr_rw.903631976710154800432283360177946821219488006022842374370004154
10528226275015
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.42796706793683884131005246545330886657934376219926404274909948844476748462764
Short name T18
Test name
Test status
Simulation time 12899942265 ps
CPU time 1155.22 seconds
Started Nov 22 03:01:35 PM PST 23
Finished Nov 22 03:20:51 PM PST 23
Peak memory 587344 kb
Host smart-6f214c78-4a48-407c-a0b1-10c85b2d90f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42796706793683884131005246545330886657934376219926404274909948844476748462764 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.42796706793683884131005246545330886657934376219926404274909948844476748462764
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.83179476081569904360126467825112907954638681985474551093207759574275181087863
Short name T30
Test name
Test status
Simulation time 4139861104 ps
CPU time 226.43 seconds
Started Nov 22 02:56:58 PM PST 23
Finished Nov 22 03:00:45 PM PST 23
Peak memory 632480 kb
Host smart-751f1b09-fe2c-4cc9-928b-d7d614e90bf4
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831794760815699043601264678251129079546386819854745510932077595742
75181087863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 0.chip_padctrl_attributes.831794760815699043601264678251129079546
38681985474551093207759574275181087863
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.100830255475954012778996288874847680199153870598825656413973604185287994218286
Short name T29
Test name
Test status
Simulation time 4139861104 ps
CPU time 220.35 seconds
Started Nov 22 02:56:48 PM PST 23
Finished Nov 22 03:00:30 PM PST 23
Peak memory 632348 kb
Host smart-6bfeb48d-0d76-4691-93b2-401503840613
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100830255475954012778996288874847680199153870598825656413973604185
287994218286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 1.chip_padctrl_attributes.10083025547595401277899628887484768019
9153870598825656413973604185287994218286
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.112266305908233085513206898716635866217449999173828557466816788802817848361025
Short name T34
Test name
Test status
Simulation time 4139861104 ps
CPU time 226.07 seconds
Started Nov 22 02:57:06 PM PST 23
Finished Nov 22 03:00:52 PM PST 23
Peak memory 632480 kb
Host smart-c1639f73-8857-4ce0-aa68-b68eea56893f
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112266305908233085513206898716635866217449999173828557466816788802
817848361025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 2.chip_padctrl_attributes.11226630590823308551320689871663586621
7449999173828557466816788802817848361025
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.52982201090226764670109832624800317726471762534712374620081399705501217396462
Short name T33
Test name
Test status
Simulation time 4139861104 ps
CPU time 211.21 seconds
Started Nov 22 02:56:47 PM PST 23
Finished Nov 22 03:00:19 PM PST 23
Peak memory 632468 kb
Host smart-d45822bf-400d-4f97-a15b-29dc2bcdeb9f
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529822010902267646701098326248003177264717625347123746200813997055
01217396462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 3.chip_padctrl_attributes.529822010902267646701098326248003177264
71762534712374620081399705501217396462
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2663858252819695666369638169812672701881305138511738108811859519051076821738
Short name T31
Test name
Test status
Simulation time 4139861104 ps
CPU time 219.64 seconds
Started Nov 22 02:57:03 PM PST 23
Finished Nov 22 03:00:44 PM PST 23
Peak memory 632488 kb
Host smart-f3b31535-4001-47f0-a288-d8c8a9ad43dd
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266385825281969566636963816981267270188130513851173810881185951905
1076821738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 5.chip_padctrl_attributes.2663858252819695666369638169812672701881
305138511738108811859519051076821738
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.35556829400896023535424209760458212166642657190595437894710840070627992238258
Short name T15
Test name
Test status
Simulation time 4139861104 ps
CPU time 215.08 seconds
Started Nov 22 02:56:47 PM PST 23
Finished Nov 22 03:00:23 PM PST 23
Peak memory 632476 kb
Host smart-e8495683-9034-475a-917b-92f790be07cc
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355568294008960235354242097604582121666426571905954378947108400706
27992238258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 6.chip_padctrl_attributes.355568294008960235354242097604582121666
42657190595437894710840070627992238258
Directory /workspace/6.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.100084258760626221546000911195997771922774770662475218262312802707628534957812
Short name T32
Test name
Test status
Simulation time 4139861104 ps
CPU time 204.42 seconds
Started Nov 22 02:56:52 PM PST 23
Finished Nov 22 03:00:17 PM PST 23
Peak memory 632376 kb
Host smart-d9b834df-a315-4dae-b93c-8b96b2bd80d8
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100084258760626221546000911195997771922774770662475218262312802707
628534957812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 7.chip_padctrl_attributes.10008425876062622154600091119599777192
2774770662475218262312802707628534957812
Directory /workspace/7.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.18253652690566155292930272365901612206804666263626066846258299242032438277295
Short name T35
Test name
Test status
Simulation time 4139861104 ps
CPU time 213.25 seconds
Started Nov 22 02:56:46 PM PST 23
Finished Nov 22 03:00:20 PM PST 23
Peak memory 632456 kb
Host smart-11930821-a65b-46b0-95af-2e93019d84cd
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182536526905661552929302723659016122068046662636260668462582992420
32438277295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 8.chip_padctrl_attributes.182536526905661552929302723659016122068
04666263626066846258299242032438277295
Directory /workspace/8.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.106065033385108934942635365657642025959294250328944258952966673578185348190582
Short name T13
Test name
Test status
Simulation time 4139861104 ps
CPU time 222.68 seconds
Started Nov 22 02:56:48 PM PST 23
Finished Nov 22 03:00:31 PM PST 23
Peak memory 632472 kb
Host smart-87c907a6-9384-4fde-acb2-cee59ec8d78b
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106065033385108934942635365657642025959294250328944258952966673578
185348190582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 9.chip_padctrl_attributes.10606503338510893494263536565764202595
9294250328944258952966673578185348190582
Directory /workspace/9.chip_padctrl_attributes/latest
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