Unified Coverage Report :: Cond split page

Go back

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T11

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       124
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       124
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       5743
 EXPRESSION (mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       5775
 EXPRESSION (mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       5807
 EXPRESSION (mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       5839
 EXPRESSION (mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       5871
 EXPRESSION (mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11
1	1	Covered	T4,T5,T6

 LINE       5903
 EXPRESSION (mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       5935
 EXPRESSION (mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       5967
 EXPRESSION (mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       5999
 EXPRESSION (mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6031
 EXPRESSION (mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11
1	1	Covered	T4,T5,T6

 LINE       6063
 EXPRESSION (mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6095
 EXPRESSION (mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       6127
 EXPRESSION (mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6159
 EXPRESSION (mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6191
 EXPRESSION (mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6223
 EXPRESSION (mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       6255
 EXPRESSION (mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       6287
 EXPRESSION (mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6319
 EXPRESSION (mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       6351
 EXPRESSION (mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11
1	1	Covered	T4,T5,T6

 LINE       6383
 EXPRESSION (mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6415
 EXPRESSION (mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6447
 EXPRESSION (mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11
1	1	Covered	T4,T5,T6

 LINE       6479
 EXPRESSION (mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       6511
 EXPRESSION (mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       6543
 EXPRESSION (mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6575
 EXPRESSION (mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       6607
 EXPRESSION (mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6639
 EXPRESSION (mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       6671
 EXPRESSION (mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6703
 EXPRESSION (mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11
1	1	Covered	T4,T5,T6

 LINE       6735
 EXPRESSION (mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       6767
 EXPRESSION (mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       6799
 EXPRESSION (mio_periph_insel_33_we & mio_periph_insel_regwen_33_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11
1	1	Covered	T4,T5,T6

 LINE       6831
 EXPRESSION (mio_periph_insel_34_we & mio_periph_insel_regwen_34_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6863
 EXPRESSION (mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       6895
 EXPRESSION (mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6927
 EXPRESSION (mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       6959
 EXPRESSION (mio_periph_insel_38_we & mio_periph_insel_regwen_38_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       6991
 EXPRESSION (mio_periph_insel_39_we & mio_periph_insel_regwen_39_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       7023
 EXPRESSION (mio_periph_insel_40_we & mio_periph_insel_regwen_40_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       7055
 EXPRESSION (mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       7087
 EXPRESSION (mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       7119
 EXPRESSION (mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       7151
 EXPRESSION (mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       7183
 EXPRESSION (mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       7215
 EXPRESSION (mio_periph_insel_46_we & mio_periph_insel_regwen_46_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       7247
 EXPRESSION (mio_periph_insel_47_we & mio_periph_insel_regwen_47_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       7279
 EXPRESSION (mio_periph_insel_48_we & mio_periph_insel_regwen_48_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       7311
 EXPRESSION (mio_periph_insel_49_we & mio_periph_insel_regwen_49_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       7343
 EXPRESSION (mio_periph_insel_50_we & mio_periph_insel_regwen_50_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       7375
 EXPRESSION (mio_periph_insel_51_we & mio_periph_insel_regwen_51_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       7407
 EXPRESSION (mio_periph_insel_52_we & mio_periph_insel_regwen_52_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       7439
 EXPRESSION (mio_periph_insel_53_we & mio_periph_insel_regwen_53_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11
1	1	Covered	T3,T4,T5

 LINE       7471
 EXPRESSION (mio_periph_insel_54_we & mio_periph_insel_regwen_54_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3
1	1	Covered	T11,T4,T5

 LINE       7503
 EXPRESSION (mio_periph_insel_55_we & mio_periph_insel_regwen_55_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       7535
 EXPRESSION (mio_periph_insel_56_we & mio_periph_insel_regwen_56_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T4

 LINE       8930
 EXPRESSION (mio_outsel_0_we & mio_outsel_regwen_0_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       8962
 EXPRESSION (mio_outsel_1_we & mio_outsel_regwen_1_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       8994
 EXPRESSION (mio_outsel_2_we & mio_outsel_regwen_2_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9026
 EXPRESSION (mio_outsel_3_we & mio_outsel_regwen_3_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9058
 EXPRESSION (mio_outsel_4_we & mio_outsel_regwen_4_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9090
 EXPRESSION (mio_outsel_5_we & mio_outsel_regwen_5_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9122
 EXPRESSION (mio_outsel_6_we & mio_outsel_regwen_6_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9154
 EXPRESSION (mio_outsel_7_we & mio_outsel_regwen_7_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9186
 EXPRESSION (mio_outsel_8_we & mio_outsel_regwen_8_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9218
 EXPRESSION (mio_outsel_9_we & mio_outsel_regwen_9_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9250
 EXPRESSION (mio_outsel_10_we & mio_outsel_regwen_10_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9282
 EXPRESSION (mio_outsel_11_we & mio_outsel_regwen_11_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9314
 EXPRESSION (mio_outsel_12_we & mio_outsel_regwen_12_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9346
 EXPRESSION (mio_outsel_13_we & mio_outsel_regwen_13_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9378
 EXPRESSION (mio_outsel_14_we & mio_outsel_regwen_14_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9410
 EXPRESSION (mio_outsel_15_we & mio_outsel_regwen_15_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9442
 EXPRESSION (mio_outsel_16_we & mio_outsel_regwen_16_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9474
 EXPRESSION (mio_outsel_17_we & mio_outsel_regwen_17_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9506
 EXPRESSION (mio_outsel_18_we & mio_outsel_regwen_18_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9538
 EXPRESSION (mio_outsel_19_we & mio_outsel_regwen_19_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9570
 EXPRESSION (mio_outsel_20_we & mio_outsel_regwen_20_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9602
 EXPRESSION (mio_outsel_21_we & mio_outsel_regwen_21_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9634
 EXPRESSION (mio_outsel_22_we & mio_outsel_regwen_22_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9666
 EXPRESSION (mio_outsel_23_we & mio_outsel_regwen_23_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9698
 EXPRESSION (mio_outsel_24_we & mio_outsel_regwen_24_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9730
 EXPRESSION (mio_outsel_25_we & mio_outsel_regwen_25_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9762
 EXPRESSION (mio_outsel_26_we & mio_outsel_regwen_26_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9794
 EXPRESSION (mio_outsel_27_we & mio_outsel_regwen_27_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9826
 EXPRESSION (mio_outsel_28_we & mio_outsel_regwen_28_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9858
 EXPRESSION (mio_outsel_29_we & mio_outsel_regwen_29_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9890
 EXPRESSION (mio_outsel_30_we & mio_outsel_regwen_30_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9922
 EXPRESSION (mio_outsel_31_we & mio_outsel_regwen_31_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9954
 EXPRESSION (mio_outsel_32_we & mio_outsel_regwen_32_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9986
 EXPRESSION (mio_outsel_33_we & mio_outsel_regwen_33_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10018
 EXPRESSION (mio_outsel_34_we & mio_outsel_regwen_34_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10050
 EXPRESSION (mio_outsel_35_we & mio_outsel_regwen_35_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10082
 EXPRESSION (mio_outsel_36_we & mio_outsel_regwen_36_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10114
 EXPRESSION (mio_outsel_37_we & mio_outsel_regwen_37_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10146
 EXPRESSION (mio_outsel_38_we & mio_outsel_regwen_38_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10178
 EXPRESSION (mio_outsel_39_we & mio_outsel_regwen_39_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10210
 EXPRESSION (mio_outsel_40_we & mio_outsel_regwen_40_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10242
 EXPRESSION (mio_outsel_41_we & mio_outsel_regwen_41_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10274
 EXPRESSION (mio_outsel_42_we & mio_outsel_regwen_42_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10306
 EXPRESSION (mio_outsel_43_we & mio_outsel_regwen_43_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10338
 EXPRESSION (mio_outsel_44_we & mio_outsel_regwen_44_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10370
 EXPRESSION (mio_outsel_45_we & mio_outsel_regwen_45_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10402
 EXPRESSION (mio_outsel_46_we & mio_outsel_regwen_46_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       11800
 EXPRESSION (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       11953
 EXPRESSION (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       12106
 EXPRESSION (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       12259
 EXPRESSION (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       12412
 EXPRESSION (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       12565
 EXPRESSION (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       12718
 EXPRESSION (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       12871
 EXPRESSION (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       13024
 EXPRESSION (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       13177
 EXPRESSION (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       13330
 EXPRESSION (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       13483
 EXPRESSION (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       13636
 EXPRESSION (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       13789
 EXPRESSION (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       13942
 EXPRESSION (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       14095
 EXPRESSION (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       14248
 EXPRESSION (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       14401
 EXPRESSION (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       14554
 EXPRESSION (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       14707
 EXPRESSION (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       14860
 EXPRESSION (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       15013
 EXPRESSION (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       15166
 EXPRESSION (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       15319
 EXPRESSION (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       15472
 EXPRESSION (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       15625
 EXPRESSION (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       15778
 EXPRESSION (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       15931
 EXPRESSION (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       16084
 EXPRESSION (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       16237
 EXPRESSION (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       16390
 EXPRESSION (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       16543
 EXPRESSION (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       16696
 EXPRESSION (mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       16849
 EXPRESSION (mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       17002
 EXPRESSION (mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       17155
 EXPRESSION (mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       17308
 EXPRESSION (mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       17461
 EXPRESSION (mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       17614
 EXPRESSION (mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       17767
 EXPRESSION (mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       17920
 EXPRESSION (mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       18073
 EXPRESSION (mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       18226
 EXPRESSION (mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       18379
 EXPRESSION (mio_pad_attr_43_we & mio_pad_attr_regwen_43_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       18532
 EXPRESSION (mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       18685
 EXPRESSION (mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       18838
 EXPRESSION (mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       19455
 EXPRESSION (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       19608
 EXPRESSION (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       19761
 EXPRESSION (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       19914
 EXPRESSION (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       20067
 EXPRESSION (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       20220
 EXPRESSION (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       20373
 EXPRESSION (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       20526
 EXPRESSION (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       20679
 EXPRESSION (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       20832
 EXPRESSION (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       20985
 EXPRESSION (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       21138
 EXPRESSION (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       21291
 EXPRESSION (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       21444
 EXPRESSION (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       21597
 EXPRESSION (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6