| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 58.86 | 66.53 | 64.92 | 36.70 | 75.09 | 86.09 | 23.83 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 44.99 | 44.99 | 44.24 | 44.24 | 46.51 | 46.51 | 21.65 | 21.65 | 62.15 | 62.15 | 86.06 | 86.06 | 9.35 | 9.35 | /workspace/coverage/default/1.chip_jtag_csr_rw.2425753731 | ||
| 52.58 | 7.59 | 59.75 | 15.51 | 55.44 | 8.93 | 29.69 | 8.04 | 67.65 | 5.50 | 86.25 | 0.19 | 16.70 | 7.35 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2705422839 | ||
| 57.82 | 5.24 | 65.79 | 6.04 | 63.93 | 8.49 | 33.16 | 3.46 | 74.84 | 7.19 | 86.25 | 0.00 | 22.94 | 6.24 | /workspace/coverage/default/2.chip_jtag_csr_rw.1728691707 | ||
| 58.37 | 0.55 | 66.20 | 0.40 | 64.79 | 0.86 | 34.06 | 0.90 | 75.08 | 0.24 | 86.25 | 0.00 | 23.83 | 0.89 | /workspace/coverage/default/0.chip_jtag_csr_rw.3676581379 | ||
| 58.76 | 0.39 | 66.22 | 0.03 | 64.81 | 0.02 | 36.34 | 2.28 | 75.09 | 0.01 | 86.25 | 0.00 | 23.83 | 0.00 | /workspace/coverage/default/2.chip_jtag_mem_access.1715646344 | ||
| 58.79 | 0.04 | 66.24 | 0.02 | 64.90 | 0.09 | 36.45 | 0.11 | 75.09 | 0.00 | 86.25 | 0.00 | 23.83 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2458193721 | ||
| 58.82 | 0.02 | 66.24 | 0.00 | 64.90 | 0.01 | 36.60 | 0.15 | 75.09 | 0.00 | 86.25 | 0.00 | 23.83 | 0.00 | /workspace/coverage/default/1.chip_jtag_mem_access.1402324722 | ||
| 58.83 | 0.01 | 66.24 | 0.00 | 64.92 | 0.01 | 36.64 | 0.05 | 75.09 | 0.00 | 86.25 | 0.00 | 23.83 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1586770459 | ||
| 58.84 | 0.01 | 66.24 | 0.00 | 64.92 | 0.00 | 36.69 | 0.04 | 75.09 | 0.00 | 86.25 | 0.00 | 23.83 | 0.00 | /workspace/coverage/default/0.chip_jtag_mem_access.109992303 | ||
| 58.84 | 0.01 | 66.24 | 0.00 | 64.92 | 0.01 | 36.70 | 0.01 | 75.09 | 0.00 | 86.25 | 0.00 | 23.83 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3964652373 | ||
| 58.84 | 0.01 | 66.24 | 0.00 | 64.92 | 0.00 | 36.70 | 0.01 | 75.09 | 0.00 | 86.25 | 0.00 | 23.83 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.977499134 | ||
| Name |
|---|
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2422607195 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2330801072 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.531711927 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.784815113 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3680311715 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.chip_jtag_mem_access.1402324722 | Dec 20 01:10:38 PM PST 23 | Dec 20 01:28:42 PM PST 23 | 12755416829 ps | ||
| T2 | /workspace/coverage/default/1.chip_jtag_csr_rw.2425753731 | Dec 20 01:10:35 PM PST 23 | Dec 20 01:41:32 PM PST 23 | 22040500200 ps | ||
| T3 | /workspace/coverage/default/0.chip_jtag_csr_rw.3676581379 | Dec 20 01:09:14 PM PST 23 | Dec 20 01:22:55 PM PST 23 | 9690249735 ps | ||
| T9 | /workspace/coverage/default/2.chip_jtag_mem_access.1715646344 | Dec 20 01:11:24 PM PST 23 | Dec 20 01:27:55 PM PST 23 | 13149428574 ps | ||
| T10 | /workspace/coverage/default/0.chip_jtag_mem_access.109992303 | Dec 20 01:09:14 PM PST 23 | Dec 20 01:28:38 PM PST 23 | 13395559304 ps | ||
| T11 | /workspace/coverage/default/2.chip_jtag_csr_rw.1728691707 | Dec 20 01:11:17 PM PST 23 | Dec 20 01:24:38 PM PST 23 | 9775489194 ps | ||
| T4 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.784815113 | Dec 20 01:08:18 PM PST 23 | Dec 20 01:12:53 PM PST 23 | 4797563928 ps | ||
| T5 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3680311715 | Dec 20 01:08:17 PM PST 23 | Dec 20 01:13:02 PM PST 23 | 4295439547 ps | ||
| T6 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.977499134 | Dec 20 01:08:17 PM PST 23 | Dec 20 01:13:13 PM PST 23 | 4238971620 ps | ||
| T7 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2422607195 | Dec 20 01:08:17 PM PST 23 | Dec 20 01:12:42 PM PST 23 | 4418944664 ps | ||
| T8 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2705422839 | Dec 20 01:08:17 PM PST 23 | Dec 20 01:12:38 PM PST 23 | 5336334691 ps | ||
| T14 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.531711927 | Dec 20 01:08:19 PM PST 23 | Dec 20 01:12:31 PM PST 23 | 4567762481 ps | ||
| T12 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2458193721 | Dec 20 01:08:17 PM PST 23 | Dec 20 01:13:34 PM PST 23 | 5744082161 ps | ||
| T16 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3964652373 | Dec 20 01:08:17 PM PST 23 | Dec 20 01:11:48 PM PST 23 | 4373699857 ps | ||
| T13 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2330801072 | Dec 20 01:08:16 PM PST 23 | Dec 20 01:11:18 PM PST 23 | 4329551952 ps | ||
| T15 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1586770459 | Dec 20 01:08:17 PM PST 23 | Dec 20 01:12:52 PM PST 23 | 4705283340 ps |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.2425753731 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 22040500200 ps |
| CPU time | 1855.26 seconds |
| Started | Dec 20 01:10:35 PM PST 23 |
| Finished | Dec 20 01:41:32 PM PST 23 |
| Peak memory | 588540 kb |
| Host | smart-57846322-48b3-42b5-a371-e6904bc2d186 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425753731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.2425753731 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2705422839 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5336334691 ps |
| CPU time | 254.58 seconds |
| Started | Dec 20 01:08:17 PM PST 23 |
| Finished | Dec 20 01:12:38 PM PST 23 |
| Peak memory | 633744 kb |
| Host | smart-38173d75-ef5e-4ee1-b524-742de081630a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705422839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2705422839 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.1728691707 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9775489194 ps |
| CPU time | 798.28 seconds |
| Started | Dec 20 01:11:17 PM PST 23 |
| Finished | Dec 20 01:24:38 PM PST 23 |
| Peak memory | 588536 kb |
| Host | smart-5d284ee1-3915-4adb-a159-4eb1feeb47d1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728691707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1728691707 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.3676581379 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9690249735 ps |
| CPU time | 819.98 seconds |
| Started | Dec 20 01:09:14 PM PST 23 |
| Finished | Dec 20 01:22:55 PM PST 23 |
| Peak memory | 596144 kb |
| Host | smart-81c1ee2b-a15b-4c4d-b6cc-7fbaefcd69bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676581379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3676581379 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.1715646344 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13149428574 ps |
| CPU time | 984.26 seconds |
| Started | Dec 20 01:11:24 PM PST 23 |
| Finished | Dec 20 01:27:55 PM PST 23 |
| Peak memory | 595856 kb |
| Host | smart-77bfead8-550f-4c8f-921b-ac785ce89421 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715646344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1 715646344 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2458193721 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5744082161 ps |
| CPU time | 310.31 seconds |
| Started | Dec 20 01:08:17 PM PST 23 |
| Finished | Dec 20 01:13:34 PM PST 23 |
| Peak memory | 633688 kb |
| Host | smart-f81db141-4df7-44cd-9864-a7c05cf972a0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458193721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2458193721 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.1402324722 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12755416829 ps |
| CPU time | 1083 seconds |
| Started | Dec 20 01:10:38 PM PST 23 |
| Finished | Dec 20 01:28:42 PM PST 23 |
| Peak memory | 587488 kb |
| Host | smart-ce9fbc9a-c478-47dd-8ed9-3ceb201afe64 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402324722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1 402324722 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1586770459 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4705283340 ps |
| CPU time | 268.4 seconds |
| Started | Dec 20 01:08:17 PM PST 23 |
| Finished | Dec 20 01:12:52 PM PST 23 |
| Peak memory | 632264 kb |
| Host | smart-dc68b4d6-cd55-4b93-b48b-7a1ae8388a0c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586770459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1586770459 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.109992303 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13395559304 ps |
| CPU time | 1163.87 seconds |
| Started | Dec 20 01:09:14 PM PST 23 |
| Finished | Dec 20 01:28:38 PM PST 23 |
| Peak memory | 587380 kb |
| Host | smart-9022433a-751e-4e49-8158-f462f78849cd |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109992303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.109992303 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3964652373 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4373699857 ps |
| CPU time | 204.22 seconds |
| Started | Dec 20 01:08:17 PM PST 23 |
| Finished | Dec 20 01:11:48 PM PST 23 |
| Peak memory | 633676 kb |
| Host | smart-b3a9adc6-a65d-46f3-b704-9df3c3c76a08 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964652373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3964652373 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.977499134 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4238971620 ps |
| CPU time | 289.21 seconds |
| Started | Dec 20 01:08:17 PM PST 23 |
| Finished | Dec 20 01:13:13 PM PST 23 |
| Peak memory | 632484 kb |
| Host | smart-af70c4fe-41e1-44b2-a71c-d0cef6662bdd |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977499134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.977499134 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2422607195 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4418944664 ps |
| CPU time | 258.51 seconds |
| Started | Dec 20 01:08:17 PM PST 23 |
| Finished | Dec 20 01:12:42 PM PST 23 |
| Peak memory | 626200 kb |
| Host | smart-dc7b8ab0-8158-485a-84a4-8ea1aa3371a7 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422607195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.2422607195 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2330801072 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4329551952 ps |
| CPU time | 174.16 seconds |
| Started | Dec 20 01:08:16 PM PST 23 |
| Finished | Dec 20 01:11:18 PM PST 23 |
| Peak memory | 625408 kb |
| Host | smart-472821cc-0432-4cca-ae38-3407e13282cc |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330801072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.2330801072 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.531711927 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4567762481 ps |
| CPU time | 247.36 seconds |
| Started | Dec 20 01:08:19 PM PST 23 |
| Finished | Dec 20 01:12:31 PM PST 23 |
| Peak memory | 618140 kb |
| Host | smart-da31c595-f333-412c-9114-f94f4134efb7 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531711927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 6.chip_padctrl_attributes.531711927 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.784815113 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4797563928 ps |
| CPU time | 269.8 seconds |
| Started | Dec 20 01:08:18 PM PST 23 |
| Finished | Dec 20 01:12:53 PM PST 23 |
| Peak memory | 633664 kb |
| Host | smart-9ae011be-33b5-43de-9126-8391fd9202ba |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784815113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.784815113 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3680311715 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4295439547 ps |
| CPU time | 278.64 seconds |
| Started | Dec 20 01:08:17 PM PST 23 |
| Finished | Dec 20 01:13:02 PM PST 23 |
| Peak memory | 633772 kb |
| Host | smart-f85572d6-4918-42bb-917a-eddb8f3e5572 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680311715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.3680311715 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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