Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	154717	1			T14	32		T15	5		T16	35
values[2]	5017	1			T16	1		T33	15		T74	4
values[3]	2469	1			T33	13		T81	92		T87	1
values[4]	1725	1			T33	10		T81	40		T64	14
values[5]	1448	1			T33	32		T81	17		T64	14
values[6]	1274	1			T33	32		T81	2		T64	12
values[7]	1091	1			T33	23		T81	3		T64	2
values[8]	1139	1			T33	29		T64	2		T96	23
values[9]	922	1			T33	24		T64	2		T96	9
values[10]	834	1			T33	17		T64	3		T96	15
values[11]	743	1			T33	15		T64	4		T96	22
values[12]	682	1			T33	7		T64	6		T96	24
values[13]	528	1			T33	6		T64	2		T96	9
values[14]	348	1			T33	2		T64	7		T96	7
values[15]	278	1			T33	3		T64	3		T96	2
values[16]	270	1			T33	13		T64	8		T97	19
values[17]	244	1			T33	8		T64	13		T97	21
values[18]	247	1			T33	18		T64	8		T97	36
values[19]	280	1			T33	13		T64	6		T97	36
values[20]	269	1			T33	20		T64	5		T97	17
values[21]	263	1			T33	16		T64	1		T97	17
values[22]	241	1			T33	7		T64	11		T97	30
values[23]	169	1			T33	5		T64	6		T97	20
values[24]	139	1			T33	11		T64	12		T97	18
values[25]	144	1			T33	20		T64	23		T97	7
values[26]	117	1			T33	6		T64	18		T97	4
values[27]	122	1			T33	6		T64	20		T97	1
values[28]	121	1			T33	11		T64	18		T97	4
values[29]	124	1			T33	26		T64	14		T97	3
values[30]	115	1			T33	16		T64	22		T97	4
values[31]	130	1			T33	16		T64	27		T97	8
values[32]	136	1			T33	24		T64	16		T97	22
values[33]	161	1			T33	21		T64	20		T97	44
values[34]	136	1			T33	3		T64	14		T97	53
values[35]	98	1			T64	16		T97	30		T368	3
values[36]	112	1			T64	27		T97	34		T368	2
values[37]	112	1			T64	38		T97	19		T368	4
values[38]	89	1			T64	6		T97	14		T368	5
values[39]	96	1			T64	22		T97	8		T368	2
values[40]	70	1			T64	9		T97	5		T368	3
values[41]	50	1			T64	3		T97	2		T368	4
values[42]	56	1			T64	9		T368	1		T91	3
values[43]	62	1			T64	9		T368	4		T91	1
values[44]	60	1			T64	7		T368	3		T91	1
values[45]	50	1			T368	3		T91	1		T376	2
values[46]	46	1			T368	1		T91	1		T376	2
values[47]	47	1			T368	4		T91	5		T376	2
values[48]	50	1			T368	4		T91	1		T376	2
values[49]	35	1			T368	2		T91	1		T376	2
values[50]	43	1			T368	2		T91	4		T376	2
values[51]	40	1			T368	4		T91	3		T376	2
values[52]	40	1			T368	5		T91	1		T376	2
values[53]	48	1			T368	2		T91	3		T376	2
values[54]	57	1			T368	3		T91	3		T376	3
values[55]	53	1			T368	4		T91	3		T376	2
values[56]	36	1			T368	3		T91	2		T376	2
values[57]	32	1			T368	2		T91	4		T376	2
values[58]	38	1			T368	4		T91	1		T376	2
values[59]	43	1			T368	2		T91	2		T376	2
values[60]	45	1			T368	1		T91	1		T376	2
values[61]	40	1			T368	1		T91	3		T376	2
values[62]	31	1			T368	2		T91	1		T376	2
values[63]	34	1			T368	2		T91	2		T376	2
values[64]	35	1			T368	1		T91	1		T376	2
values[65]	40	1			T368	1		T91	3		T376	2
values[66]	35	1			T368	1		T91	2		T376	2
values[67]	35	1			T368	2		T91	1		T376	2
values[68]	43	1			T368	2		T91	2		T376	2
values[69]	46	1			T368	7		T91	2		T376	2
values[70]	52	1			T368	2		T91	4		T376	3
values[71]	47	1			T368	2		T91	2		T376	11
values[72]	43	1			T368	1		T91	2		T376	4
values[73]	42	1			T368	2		T91	1		T376	4
values[74]	39	1			T368	2		T91	3		T376	4
values[75]	62	1			T368	3		T91	1		T376	9
values[76]	54	1			T368	1		T91	1		T376	6
values[77]	45	1			T368	3		T91	1		T376	3
values[78]	47	1			T368	10		T91	2		T376	2
values[79]	69	1			T368	10		T91	2		T376	6
values[80]	51	1			T368	4		T91	3		T376	5
values[81]	56	1			T368	4		T91	3		T376	6
values[82]	50	1			T368	7		T91	2		T376	7
values[83]	62	1			T368	6		T91	6		T376	7
values[84]	67	1			T368	2		T91	8		T376	4
values[85]	49	1			T368	5		T91	5		T376	4
values[86]	48	1			T368	2		T91	3		T376	6
values[87]	50	1			T368	7		T91	3		T376	3
values[88]	53	1			T368	6		T91	2		T376	3
values[89]	57	1			T368	4		T91	4		T376	2
values[90]	57	1			T368	8		T91	1		T376	3
values[91]	50	1			T368	5		T91	3		T376	3
values[92]	56	1			T368	7		T91	2		T376	4
values[93]	68	1			T368	10		T91	2		T376	8
values[94]	48	1			T368	3		T91	2		T376	3
values[95]	50	1			T368	1		T91	2		T376	2
values[96]	55	1			T368	4		T91	2		T376	3
values[97]	65	1			T368	4		T91	8		T376	5
values[98]	81	1			T368	3		T91	4		T376	3
values[99]	61	1			T368	2		T91	4		T376	5
values[100]	55	1			T368	2		T91	3		T376	5
values[101]	75	1			T368	5		T91	11		T376	2
values[102]	75	1			T368	7		T91	9		T376	3
values[103]	72	1			T368	3		T91	10		T376	3
values[104]	85	1			T368	1		T91	7		T376	10
values[105]	65	1			T368	4		T91	4		T376	9
values[106]	63	1			T368	7		T91	6		T376	2
values[107]	67	1			T368	4		T91	4		T376	3
values[108]	61	1			T368	7		T91	2		T376	4
values[109]	78	1			T368	1		T91	7		T376	6
values[110]	61	1			T368	2		T91	6		T376	4
values[111]	75	1			T368	4		T91	1		T376	6
values[112]	74	1			T368	7		T91	1		T376	7
values[113]	67	1			T368	2		T91	2		T376	9
values[114]	70	1			T368	5		T91	5		T376	5
values[115]	81	1			T368	6		T91	3		T376	8
values[116]	88	1			T368	6		T91	7		T376	3
values[117]	92	1			T368	4		T91	10		T376	6
values[118]	80	1			T368	5		T91	9		T376	3
values[119]	83	1			T368	9		T91	11		T376	4
values[120]	83	1			T368	10		T91	6		T376	2
values[121]	87	1			T368	5		T91	4		T376	6
values[122]	89	1			T368	5		T91	9		T376	4
values[123]	98	1			T368	4		T91	11		T376	4
values[124]	163	1			T368	7		T91	16		T376	2
values[125]	329	1			T368	22		T91	26		T376	3
values[126]	643	1			T368	44		T91	55		T376	27
values[127]	1724	1			T368	22		T91	38		T376	159
values[128]	2967	1			T91	3		T376	417		T121	4