Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	411	1			T223	1		T82	3		T216	2
all_values[1]	462	1			T217	1		T82	1		T81	3
all_values[2]	487	1			T31	1		T33	1		T62	1
all_values[3]	460	1			T33	1		T223	1		T217	1
all_values[4]	449	1			T31	1		T62	1		T217	3
all_values[5]	494	1			T62	1		T82	3		T81	6
all_values[6]	500	1			T223	2		T82	1		T81	3
all_values[7]	435	1			T217	1		T82	2		T81	4
all_values[8]	451	1			T223	2		T217	1		T82	1
all_values[9]	445	1			T31	1		T223	1		T82	1
all_values[10]	471	1			T33	1		T217	1		T81	3
all_values[11]	475	1			T31	1		T33	1		T217	1
all_values[12]	479	1			T223	2		T217	3		T81	5
all_values[13]	468	1			T31	1		T82	5		T216	1
all_values[14]	438	1			T33	1		T82	1		T354	1
all_values[15]	453	1			T217	2		T81	3		T354	1
all_values[16]	462	1			T31	3		T82	1		T81	1
all_values[17]	447	1			T31	1		T223	1		T82	2
all_values[18]	485	1			T31	1		T62	1		T223	1
all_values[19]	500	1			T31	2		T81	6		T108	5
all_values[20]	472	1			T31	1		T33	1		T82	1
all_values[21]	446	1			T62	1		T217	2		T82	3
all_values[22]	480	1			T31	2		T62	1		T223	1
all_values[23]	497	1			T223	2		T217	1		T82	4
all_values[24]	472	1			T31	1		T223	3		T82	1
all_values[25]	446	1			T31	1		T223	1		T81	2
all_values[26]	474	1			T31	1		T33	1		T223	3
all_values[27]	469	1			T223	1		T217	1		T82	1
all_values[28]	443	1			T82	1		T81	4		T218	1
all_values[29]	481	1			T31	2		T223	2		T82	5
all_values[30]	483	1			T31	1		T33	1		T62	1
all_values[31]	454	1			T31	2		T82	2		T81	3
all_values[32]	466	1			T31	1		T82	2		T81	3
all_values[33]	461	1			T82	1		T216	1		T81	2
all_values[34]	446	1			T223	1		T217	1		T82	2
all_values[35]	445	1			T62	1		T82	3		T81	3
all_values[36]	460	1			T33	1		T82	1		T81	1
all_values[37]	486	1			T31	1		T33	1		T62	1
all_values[38]	477	1			T31	1		T223	1		T81	4
all_values[39]	483	1			T31	1		T223	1		T82	1
all_values[40]	473	1			T31	1		T33	1		T223	2
all_values[41]	436	1			T33	2		T62	1		T82	3
all_values[42]	462	1			T62	1		T223	1		T82	2
all_values[43]	467	1			T31	1		T217	1		T82	2
all_values[44]	434	1			T33	2		T217	1		T82	2
all_values[45]	484	1			T31	2		T223	1		T82	2
all_values[46]	436	1			T81	2		T354	2		T218	2
all_values[47]	472	1			T31	1		T217	1		T82	6
all_values[48]	484	1			T62	1		T82	3		T81	6
all_values[49]	435	1			T31	1		T62	1		T217	2