Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3462	1			T31	5		T49	2		T83	1
all_values[1]	3397	1			T17	5		T31	4		T58	2
all_values[2]	3371	1			T17	3		T31	2		T83	1
all_values[3]	3465	1			T17	1		T31	1		T58	2
all_values[4]	3435	1			T17	3		T31	2		T49	3
all_values[5]	3511	1			T17	2		T31	2		T58	1
all_values[6]	3444	1			T17	3		T31	2		T49	1
all_values[7]	3481	1			T17	3		T31	3		T58	1
all_values[8]	3476	1			T17	4		T31	3		T58	4
all_values[9]	3481	1			T17	4		T31	3		T49	2
all_values[10]	3540	1			T17	3		T31	1		T49	2
all_values[11]	3442	1			T17	3		T31	3		T49	1
all_values[12]	3502	1			T17	4		T31	2		T49	2
all_values[13]	3440	1			T17	3		T31	6		T83	2
all_values[14]	3415	1			T17	5		T49	2		T58	4
all_values[15]	3371	1			T17	4		T49	4		T58	4
all_values[16]	3426	1			T17	3		T31	5		T49	1
all_values[17]	3388	1			T17	1		T31	2		T49	2
all_values[18]	3401	1			T17	4		T31	2		T49	2
all_values[19]	3596	1			T17	5		T31	2		T49	2
all_values[20]	3436	1			T17	5		T31	2		T49	1
all_values[21]	3520	1			T17	2		T49	2		T58	3
all_values[22]	3409	1			T17	1		T31	2		T58	1
all_values[23]	3445	1			T17	2		T31	1		T49	1
all_values[24]	3466	1			T17	1		T31	5		T49	3
all_values[25]	3391	1			T17	4		T83	4		T62	6
all_values[26]	3349	1			T17	3		T31	3		T49	2
all_values[27]	3436	1			T17	3		T31	2		T49	2
all_values[28]	3479	1			T17	1		T31	1		T58	2
all_values[29]	3332	1			T17	5		T49	1		T58	3
all_values[30]	3387	1			T17	4		T31	3		T49	2
all_values[31]	3553	1			T31	3		T49	2		T58	2
all_values[32]	3377	1			T31	2		T49	3		T58	1
all_values[33]	3314	1			T17	4		T31	3		T49	5
all_values[34]	3500	1			T17	1		T31	2		T83	1
all_values[35]	3386	1			T17	4		T49	1		T58	6
all_values[36]	3431	1			T17	1		T31	4		T49	1
all_values[37]	3460	1			T17	1		T31	3		T49	1
all_values[38]	3572	1			T17	1		T49	1		T58	1
all_values[39]	3383	1			T17	3		T31	5		T49	2
all_values[40]	3536	1			T17	4		T31	3		T49	1
all_values[41]	3486	1			T17	3		T31	4		T58	3
all_values[42]	3499	1			T17	2		T31	2		T49	1
all_values[43]	3467	1			T17	2		T31	3		T58	1
all_values[44]	3509	1			T31	3		T49	5		T58	2
all_values[45]	3497	1			T17	3		T31	5		T49	2
all_values[46]	3443	1			T17	3		T31	4		T49	4
all_values[47]	3504	1			T17	1		T49	2		T83	1
all_values[48]	3449	1			T17	2		T31	2		T58	7
all_values[49]	3530	1			T17	3		T31	3		T49	1
all_values[50]	3391	1			T17	1		T31	1		T49	1
all_values[51]	3466	1			T17	7		T31	4		T49	3
all_values[52]	3372	1			T17	3		T31	4		T49	2
all_values[53]	3376	1			T17	1		T31	2		T49	2
all_values[54]	3466	1			T17	5		T31	5		T58	1
all_values[55]	3363	1			T31	1		T49	3		T58	2
all_values[56]	3661	1			T17	1		T31	1		T49	1
all_values[57]	3532	1			T17	3		T31	2		T49	2
all_values[58]	3339	1			T17	3		T31	3		T49	1
all_values[59]	3469	1			T17	3		T31	4		T49	1
all_values[60]	3350	1			T17	4		T31	6		T83	1
all_values[61]	3481	1			T17	2		T31	3		T49	2
all_values[62]	3406	1			T17	1		T31	1		T49	2
all_values[63]	3492	1			T17	3		T49	1		T58	1