LINE 35432
EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T16,T17,T49 |
| 1 | 0 | 1 | Covered | T11,T12,T13 |
| 1 | 1 | 0 | Covered | T170,T240,T337 |
| 1 | 1 | 1 | Covered | T13,T75,T68 |
LINE 38842
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T14,T15,T16 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T20,T18 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |